base.hh

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/*
 * Copyright (c) 2013-2014 ARM Limited
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 *
 * Authors: Ron Dreslinski
 *          Mitch Hayenga
 */

#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
#define __MEM_CACHE_PREFETCH_BASE_HH__

#include <cstdint>

#include "arch/isa_traits.hh"
#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
#include "base/types.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/clocked_object.hh"
#include "sim/probe/probe.hh"

class BaseCache;
struct BasePrefetcherParams;

class BasePrefetcher : public ClockedObject
{
    class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
    {
      public:
        PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
                         const std::string &name, bool _isFill = false,
                         bool _miss = false)
            : ProbeListenerArgBase(pm, name),
              parent(_parent), isFill(_isFill), miss(_miss) {}
        void notify(const PacketPtr &pkt) override;
      protected:
        BasePrefetcher &parent;
        const bool isFill;
        const bool miss;
    };

    std::vector<PrefetchListener *> listeners;

  public:

    class PrefetchInfo {
        Addr address;
        Addr pc;
        MasterID masterId;
        bool validPC;
        bool secure;
        unsigned int size;
        bool write;
        Addr paddress;
        bool cacheMiss;
        uint8_t *data;

      public:
        Addr getAddr() const
        {
            return address;
        }

        bool isSecure() const
        {
            return secure;
        }

        Addr getPC() const
        {
            assert(hasPC());
            return pc;
        }

        bool hasPC() const
        {
            return validPC;
        }

        MasterID getMasterId() const
        {
            return masterId;
        }

        unsigned int getSize() const
        {
            return size;
        }

        bool isWrite() const
        {
            return write;
        }

        Addr getPaddr() const
        {
            return paddress;
        }

        bool isCacheMiss() const
        {
            return cacheMiss;
        }

        template <typename T>
        inline T
        get(ByteOrder endian) const
        {
            if (data == nullptr) {
                panic("PrefetchInfo::get called with a request with no data.");
            }
            switch (endian) {
                case BigEndianByteOrder:
                    return betoh(*(T*)data);

                case LittleEndianByteOrder:
                    return letoh(*(T*)data);

                default:
                    panic("Illegal byte order in PrefetchInfo::get()\n");
            };
        }

        bool sameAddr(PrefetchInfo const &pfi) const
        {
            return this->getAddr() == pfi.getAddr() &&
                this->isSecure() == pfi.isSecure();
        }

        PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);

        PrefetchInfo(PrefetchInfo const &pfi, Addr addr);

        ~PrefetchInfo()
        {
            delete[] data;
        }
    };

  protected:

    // PARAMETERS

    BaseCache* cache;

    unsigned blkSize;

    unsigned lBlkSize;

    const bool onMiss;

    const bool onRead;

    const bool onWrite;

    const bool onData;

    const bool onInst;

    const MasterID masterId;

    const Addr pageBytes;

    const bool prefetchOnAccess;

    const bool useVirtualAddresses;

    bool observeAccess(const PacketPtr &pkt, bool miss) const;

    bool inCache(Addr addr, bool is_secure) const;

    bool inMissQueue(Addr addr, bool is_secure) const;

    bool hasBeenPrefetched(Addr addr, bool is_secure) const;

    bool samePage(Addr a, Addr b) const;
    Addr blockAddress(Addr a) const;
    Addr blockIndex(Addr a) const;
    Addr pageAddress(Addr a) const;
    Addr pageOffset(Addr a) const;
    Addr pageIthBlockAddress(Addr page, uint32_t i) const;

    Stats::Scalar pfIssued;

    uint64_t issuedPrefetches;
    uint64_t usefulPrefetches;

    BaseTLB * tlb;

  public:

    BasePrefetcher(const BasePrefetcherParams *p);

    virtual ~BasePrefetcher() {}

    virtual void setCache(BaseCache *_cache);

    virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;

    virtual void notifyFill(const PacketPtr &pkt)
    {}

    virtual PacketPtr getPacket() = 0;

    virtual Tick nextPrefetchReadyTime() const = 0;

    void regStats() override;

    void regProbeListeners() override;

    void probeNotify(const PacketPtr &pkt, bool miss);

    void addEventProbe(SimObject *obj, const char *name);

    void addTLB(BaseTLB *tlb);
};
#endif //__MEM_CACHE_PREFETCH_BASE_HH__