gem5
v19.0.0.0
arch
mips
mmapped_ipr.hh
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_MIPS_MMAPPED_IPR_HH__
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#define __ARCH_MIPS_MMAPPED_IPR_HH__
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#include "
base/types.hh
"
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class
Packet
;
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class
ThreadContext
;
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namespace
MipsISA
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{
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inline
Cycles
handleIprRead
(
ThreadContext
*,
Packet
*) {
return
Cycles
(1); }
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inline
Cycles
handleIprWrite
(
ThreadContext
*,
Packet
*) {
return
Cycles
(1); }
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}
// namespace MipsISA
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#endif
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition:
types.hh:83
MipsISA::handleIprWrite
Cycles handleIprWrite(ThreadContext *, Packet *)
Definition:
mmapped_ipr.hh:49
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition:
thread_context.hh:93
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition:
packet.hh:255
MipsISA::handleIprRead
Cycles handleIprRead(ThreadContext *, Packet *)
Definition:
mmapped_ipr.hh:48
MipsISA
Definition:
decoder.cc:33
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