gem5  v19.0.0.0
smmu_v3_slaveifc.hh
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39 
40 #ifndef __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
41 #define __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
42 
43 #include <list>
44 
46 #include "dev/arm/smmu_v3_defs.hh"
48 #include "dev/arm/smmu_v3_ports.hh"
49 #include "dev/arm/smmu_v3_proc.hh"
50 #include "params/SMMUv3SlaveInterface.hh"
51 #include "sim/clocked_object.hh"
52 
54 class SMMUv3;
55 class SMMUSlavePort;
56 
58 {
59  protected:
60  friend class SMMUTranslationProcess;
61 
62  public:
66 
67  const bool microTLBEnable;
68  const bool mainTLBEnable;
69 
73 
76 
80 
81  // in bytes
82  const unsigned portWidth;
83 
87 
88  const bool prefetchEnable;
90 
93 
97 
98  // Receiving translation requests from the master device
100  bool recvTimingReq(PacketPtr pkt);
101  void schedTimingResp(PacketPtr pkt);
102 
106  void schedAtsTimingResp(PacketPtr pkt);
107 
108  void scheduleDeviceRetry();
109  void sendDeviceRetry();
110  void atsSendDeviceRetry();
111 
114 
116  EventWrapper<
119 
120  Port& getPort(const std::string &name, PortID id) override;
121 
122  public:
123  SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p);
124 
126  {
127  delete microTLB;
128  delete mainTLB;
129  }
130 
131  const SMMUv3SlaveInterfaceParams *
132  params() const
133  {
134  return static_cast<const SMMUv3SlaveInterfaceParams *>(_params);
135  }
136 
137  DrainState drain() override;
138 
139  void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; }
140  void sendRange();
141 };
142 
143 #endif /* __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ */
Ports are used to interface objects to each other.
Definition: port.hh:60
Tick recvAtomic(PacketPtr pkt)
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
SMMUDeviceRetryEvent sendDeviceRetryEvent
DrainState
Object drain/handover states.
Definition: drain.hh:71
void schedAtsTimingResp(PacketPtr pkt)
SMMUSignal dependentReqRemoved
SMMUATSSlavePort atsSlavePort
bool atsSlaveRecvTimingReq(PacketPtr pkt)
std::list< SMMUTranslationProcess * > dependentReads[SMMU_MAX_TRANS_ID]
std::list< SMMUTranslationProcess * > dependentWrites[SMMU_MAX_TRANS_ID]
SMMUSemaphore microTLBSem
bool recvTimingReq(PacketPtr pkt)
const bool prefetchReserveLastWay
const SMMUv3SlaveInterfaceParams * params() const
bool atsMasterRecvTimingResp(PacketPtr pkt)
void setSMMU(SMMUv3 *_smmu)
uint64_t Tick
Tick count type.
Definition: types.hh:63
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p)
ClockedObject declaration and implementation.
SMMUATSMasterPort atsMasterPort
Tick atsSlaveRecvAtomic(PacketPtr pkt)
STL list class.
Definition: stl.hh:54
void schedTimingResp(PacketPtr pkt)
SMMUSignal duplicateReqRemoved
virtual const std::string name() const
Definition: sim_object.hh:120
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
DrainState drain() override
Notify an object that it needs to drain its state.
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:110
const unsigned portWidth
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
SMMUSemaphore mainTLBSem
EventWrapper< SMMUv3SlaveInterface, &SMMUv3SlaveInterface::atsSendDeviceRetry > atsSendDeviceRetryEvent
Bitfield< 0 > p
Port & getPort(const std::string &name, PortID id) override
Get a port with a given name and index.
std::list< SMMUTranslationProcess * > duplicateReqs
SMMUSemaphore slavePortSem
SMMUSlavePort * slavePort

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