#include <types.hh>
Definition at line 75 of file types.hh.
◆ CoreSpecific()
| MipsISA::CoreSpecific::CoreSpecific |
( |
| ) |
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inline |
◆ CP0_Config
| unsigned MipsISA::CoreSpecific::CP0_Config |
◆ CP0_Config1
| unsigned MipsISA::CoreSpecific::CP0_Config1 |
◆ CP0_Config1_C2
| bool MipsISA::CoreSpecific::CP0_Config1_C2 |
◆ CP0_Config1_CA
| bool MipsISA::CoreSpecific::CP0_Config1_CA |
◆ CP0_Config1_DA
| unsigned MipsISA::CoreSpecific::CP0_Config1_DA |
◆ CP0_Config1_DL
| unsigned MipsISA::CoreSpecific::CP0_Config1_DL |
◆ CP0_Config1_DS
| unsigned MipsISA::CoreSpecific::CP0_Config1_DS |
◆ CP0_Config1_EP
| bool MipsISA::CoreSpecific::CP0_Config1_EP |
◆ CP0_Config1_FP
| bool MipsISA::CoreSpecific::CP0_Config1_FP |
◆ CP0_Config1_IA
| unsigned MipsISA::CoreSpecific::CP0_Config1_IA |
◆ CP0_Config1_IL
| unsigned MipsISA::CoreSpecific::CP0_Config1_IL |
◆ CP0_Config1_IS
| unsigned MipsISA::CoreSpecific::CP0_Config1_IS |
◆ CP0_Config1_M
| unsigned MipsISA::CoreSpecific::CP0_Config1_M |
◆ CP0_Config1_MD
| bool MipsISA::CoreSpecific::CP0_Config1_MD |
◆ CP0_Config1_MMU
| unsigned MipsISA::CoreSpecific::CP0_Config1_MMU |
◆ CP0_Config1_PC
| bool MipsISA::CoreSpecific::CP0_Config1_PC |
◆ CP0_Config1_WR
| bool MipsISA::CoreSpecific::CP0_Config1_WR |
◆ CP0_Config2
| unsigned MipsISA::CoreSpecific::CP0_Config2 |
◆ CP0_Config2_M
| bool MipsISA::CoreSpecific::CP0_Config2_M |
◆ CP0_Config2_SA
| unsigned MipsISA::CoreSpecific::CP0_Config2_SA |
◆ CP0_Config2_SL
| unsigned MipsISA::CoreSpecific::CP0_Config2_SL |
◆ CP0_Config2_SS
| unsigned MipsISA::CoreSpecific::CP0_Config2_SS |
◆ CP0_Config2_SU
| unsigned MipsISA::CoreSpecific::CP0_Config2_SU |
◆ CP0_Config2_TA
| unsigned MipsISA::CoreSpecific::CP0_Config2_TA |
◆ CP0_Config2_TL
| unsigned MipsISA::CoreSpecific::CP0_Config2_TL |
◆ CP0_Config2_TS
| unsigned MipsISA::CoreSpecific::CP0_Config2_TS |
◆ CP0_Config2_TU
| unsigned MipsISA::CoreSpecific::CP0_Config2_TU |
◆ CP0_Config3
| unsigned MipsISA::CoreSpecific::CP0_Config3 |
◆ CP0_Config3_DSPP
| bool MipsISA::CoreSpecific::CP0_Config3_DSPP |
◆ CP0_Config3_LPA
| bool MipsISA::CoreSpecific::CP0_Config3_LPA |
◆ CP0_Config3_M
| bool MipsISA::CoreSpecific::CP0_Config3_M |
◆ CP0_Config3_MT
| bool MipsISA::CoreSpecific::CP0_Config3_MT |
◆ CP0_Config3_SM
| bool MipsISA::CoreSpecific::CP0_Config3_SM |
◆ CP0_Config3_SP
| bool MipsISA::CoreSpecific::CP0_Config3_SP |
◆ CP0_Config3_TL
| bool MipsISA::CoreSpecific::CP0_Config3_TL |
◆ CP0_Config3_VEIC
| bool MipsISA::CoreSpecific::CP0_Config3_VEIC |
◆ CP0_Config3_VInt
| bool MipsISA::CoreSpecific::CP0_Config3_VInt |
◆ CP0_Config_AR
| unsigned MipsISA::CoreSpecific::CP0_Config_AR |
◆ CP0_Config_AT
| unsigned MipsISA::CoreSpecific::CP0_Config_AT |
◆ CP0_Config_BE
| unsigned MipsISA::CoreSpecific::CP0_Config_BE |
◆ CP0_Config_MT
| unsigned MipsISA::CoreSpecific::CP0_Config_MT |
◆ CP0_Config_VI
| unsigned MipsISA::CoreSpecific::CP0_Config_VI |
◆ CP0_EBase_CPUNum
| unsigned MipsISA::CoreSpecific::CP0_EBase_CPUNum |
◆ CP0_IntCtl_IPPCI
| unsigned MipsISA::CoreSpecific::CP0_IntCtl_IPPCI |
◆ CP0_IntCtl_IPTI
| unsigned MipsISA::CoreSpecific::CP0_IntCtl_IPTI |
◆ CP0_PerfCtr_M
| bool MipsISA::CoreSpecific::CP0_PerfCtr_M |
◆ CP0_PerfCtr_W
| bool MipsISA::CoreSpecific::CP0_PerfCtr_W |
◆ CP0_PRId
| unsigned MipsISA::CoreSpecific::CP0_PRId |
◆ CP0_PRId_CompanyID
| unsigned MipsISA::CoreSpecific::CP0_PRId_CompanyID |
◆ CP0_PRId_CompanyOptions
| unsigned MipsISA::CoreSpecific::CP0_PRId_CompanyOptions |
◆ CP0_PRId_ProcessorID
| unsigned MipsISA::CoreSpecific::CP0_PRId_ProcessorID |
◆ CP0_PRId_Revision
| unsigned MipsISA::CoreSpecific::CP0_PRId_Revision |
◆ CP0_SrsCtl_HSS
| unsigned MipsISA::CoreSpecific::CP0_SrsCtl_HSS |
◆ CP0_WatchHi_M
| bool MipsISA::CoreSpecific::CP0_WatchHi_M |
The documentation for this struct was generated from the following file: