gem5  v21.0.1.0
cpu.cc
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27 
29 
31 #include "scx/scx.h"
32 #include "sim/serialize.hh"
33 
34 namespace Iris
35 {
36 
37 BaseCPU::BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs) :
38  ::BaseCPU::BaseCPU(params), evs(_evs),
39  evs_base_cpu(dynamic_cast<Iris::BaseCpuEvs *>(_evs))
40 {
41  panic_if(!evs_base_cpu, "EVS should be of type BaseCpuEvs");
42 
43  // Make sure fast model knows we're using debugging mechanisms to control
44  // the simulation, and it shouldn't shut down if simulation time stops
45  // for some reason. Despite the misleading name, this doesn't start a CADI
46  // server because it's first parameter is false.
47  scx::scx_start_cadi_server(false, false, true);
48 }
49 
51 {
52  for (auto &tc: threadContexts)
53  delete tc;
54  threadContexts.clear();
55 }
56 
57 Counter
59 {
60  Counter count = 0;
61  for (auto *tc: threadContexts)
62  count += tc->getCurrentInstCount();
63  return count;
64 }
65 
66 void
68 {
70  for (auto *tc: threadContexts)
71  tc->initMemProxies(tc);
72 }
73 
74 void
76 {
78 }
79 
80 } // namespace Iris
serialize.hh
BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:269
Iris
Definition: cpu.cc:34
sc_core::sc_module
Definition: sc_module.hh:97
Iris::BaseCPU::~BaseCPU
virtual ~BaseCPU()
Definition: cpu.cc:50
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:233
Iris::BaseCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:75
X86ISA::count
count
Definition: misc.hh:703
Iris::BaseCPU::evs_base_cpu
Iris::BaseCpuEvs * evs_base_cpu
Definition: cpu.hh:93
Iris::BaseCPU::totalInsts
Counter totalInsts() const override
Definition: cpu.cc:58
cpu.hh
Counter
int64_t Counter
Statistics counter type.
Definition: types.hh:54
cp
Definition: cprintf.cc:37
BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:269
BaseCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: base.cc:626
Iris::BaseCPU::BaseCPU
BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs)
Definition: cpu.cc:37
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
Iris::BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: cpu.cc:67
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:64
thread_context.hh
Iris::BaseCPU
Definition: cpu.hh:55
Iris::BaseCpuEvs
Definition: cpu.hh:42

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