gem5
v21.0.1.0
arch
arm
linux
process.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2010-2013, 2015, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/arm/linux/process.hh
"
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#include <sys/syscall.h>
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#include "
arch/arm/isa_traits.hh
"
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#include "
arch/arm/linux/linux.hh
"
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#include "
base/loader/object_file.hh
"
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#include "
base/trace.hh
"
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#include "
cpu/thread_context.hh
"
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#include "
kern/linux/linux.hh
"
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#include "
sim/process.hh
"
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#include "
sim/syscall_desc.hh
"
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#include "
sim/syscall_emul.hh
"
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#include "
sim/system.hh
"
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using namespace
ArmISA
;
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const
Addr
ArmLinuxProcess32::commPage
= 0xffff0000;
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void
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ArmLinuxProcess32::initState
()
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{
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ArmProcess32::initState
();
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allocateMem(commPage,
PageBytes
);
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ThreadContext
*tc =
system
->threads[contextIds[0]];
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uint8_t swiNeg1[] = {
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0xff, 0xff, 0xff, 0xef
// swi -1
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};
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// Fill this page with swi -1 so we'll no if we land in it somewhere.
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for
(
Addr
addr
= 0;
addr
<
PageBytes
;
addr
+=
sizeof
(swiNeg1)) {
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tc->
getVirtProxy
().
writeBlob
(commPage +
addr
,
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swiNeg1,
sizeof
(swiNeg1));
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}
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uint8_t memory_barrier[] =
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{
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0x5f, 0xf0, 0x7f, 0xf5,
// dmb
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0x0e, 0xf0, 0xa0, 0xe1
// return
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};
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tc->
getVirtProxy
().
writeBlob
(commPage + 0x0fa0, memory_barrier,
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sizeof
(memory_barrier));
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uint8_t cmpxchg[] =
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{
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0x9f, 0x3f, 0x92, 0xe1,
// ldrex r3, [r2]
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0x00, 0x30, 0x53, 0xe0,
// subs r3, r3, r0
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0x91, 0x3f, 0x82, 0x01,
// strexeq r3, r1, [r2]
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0x01, 0x00, 0x33, 0x03,
// teqeq r3, #1
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0xfa, 0xff, 0xff, 0x0a,
// beq 1b
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0x00, 0x00, 0x73, 0xe2,
// rsbs r0, r3, #0
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0x5f, 0xf0, 0x7f, 0xf5,
// dmb
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0x0e, 0xf0, 0xa0, 0xe1
// return
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};
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tc->
getVirtProxy
().
writeBlob
(commPage + 0x0fc0, cmpxchg,
sizeof
(cmpxchg));
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uint8_t get_tls[] =
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{
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// read user read-only thread id register
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0x70, 0x0f, 0x1d, 0xee,
// mrc p15, 0, r0, c13, c0, 3
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0x0e, 0xf0, 0xa0, 0xe1
// return
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};
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tc->
getVirtProxy
().
writeBlob
(commPage + 0x0fe0, get_tls,
sizeof
(get_tls));
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}
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void
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ArmLinuxProcess64::initState
()
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{
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ArmProcess64::initState
();
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// The 64 bit equivalent of the comm page would be set up here.
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}
ArmProcess64::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition:
process.cc:121
linux.hh
system.hh
ArmISA
Definition:
ccregs.hh:41
ArmProcess32::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition:
process.cc:102
PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition:
port_proxy.hh:187
X86ISA::system
Bitfield< 15 > system
Definition:
misc.hh:997
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
process.hh
ArmLinuxProcess32::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition:
process.cc:62
linux.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:148
X86ISA::addr
Bitfield< 3 > addr
Definition:
types.hh:80
ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
ArmLinuxProcess64::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition:
process.cc:109
ArmISA::PageBytes
const Addr PageBytes
Definition:
isa_traits.hh:53
syscall_emul.hh
ArmLinuxProcess32::commPage
static const Addr commPage
A page to hold "kernel" provided functions. The name might be wrong.
Definition:
process.hh:60
isa_traits.hh
process.hh
trace.hh
object_file.hh
thread_context.hh
syscall_desc.hh
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