gem5  v21.0.1.0
process.cc
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41 
43 
44 #include <sys/syscall.h>
45 
46 #include "arch/arm/isa_traits.hh"
47 #include "arch/arm/linux/linux.hh"
49 #include "base/trace.hh"
50 #include "cpu/thread_context.hh"
51 #include "kern/linux/linux.hh"
52 #include "sim/process.hh"
53 #include "sim/syscall_desc.hh"
54 #include "sim/syscall_emul.hh"
55 #include "sim/system.hh"
56 
57 using namespace ArmISA;
58 
59 const Addr ArmLinuxProcess32::commPage = 0xffff0000;
60 
61 void
63 {
65  allocateMem(commPage, PageBytes);
66  ThreadContext *tc = system->threads[contextIds[0]];
67 
68  uint8_t swiNeg1[] = {
69  0xff, 0xff, 0xff, 0xef // swi -1
70  };
71 
72  // Fill this page with swi -1 so we'll no if we land in it somewhere.
73  for (Addr addr = 0; addr < PageBytes; addr += sizeof(swiNeg1)) {
74  tc->getVirtProxy().writeBlob(commPage + addr,
75  swiNeg1, sizeof(swiNeg1));
76  }
77 
78  uint8_t memory_barrier[] =
79  {
80  0x5f, 0xf0, 0x7f, 0xf5, // dmb
81  0x0e, 0xf0, 0xa0, 0xe1 // return
82  };
83  tc->getVirtProxy().writeBlob(commPage + 0x0fa0, memory_barrier,
84  sizeof(memory_barrier));
85 
86  uint8_t cmpxchg[] =
87  {
88  0x9f, 0x3f, 0x92, 0xe1, // ldrex r3, [r2]
89  0x00, 0x30, 0x53, 0xe0, // subs r3, r3, r0
90  0x91, 0x3f, 0x82, 0x01, // strexeq r3, r1, [r2]
91  0x01, 0x00, 0x33, 0x03, // teqeq r3, #1
92  0xfa, 0xff, 0xff, 0x0a, // beq 1b
93  0x00, 0x00, 0x73, 0xe2, // rsbs r0, r3, #0
94  0x5f, 0xf0, 0x7f, 0xf5, // dmb
95  0x0e, 0xf0, 0xa0, 0xe1 // return
96  };
97  tc->getVirtProxy().writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
98 
99  uint8_t get_tls[] =
100  {
101  // read user read-only thread id register
102  0x70, 0x0f, 0x1d, 0xee, // mrc p15, 0, r0, c13, c0, 3
103  0x0e, 0xf0, 0xa0, 0xe1 // return
104  };
105  tc->getVirtProxy().writeBlob(commPage + 0x0fe0, get_tls, sizeof(get_tls));
106 }
107 
108 void
110 {
112  // The 64 bit equivalent of the comm page would be set up here.
113 }
ArmProcess64::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:121
linux.hh
system.hh
ArmISA
Definition: ccregs.hh:41
ArmProcess32::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:102
PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:187
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
process.hh
ArmLinuxProcess32::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:62
linux.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:80
ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
ArmLinuxProcess64::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:109
ArmISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:53
syscall_emul.hh
ArmLinuxProcess32::commPage
static const Addr commPage
A page to hold "kernel" provided functions. The name might be wrong.
Definition: process.hh:60
isa_traits.hh
process.hh
trace.hh
object_file.hh
thread_context.hh
syscall_desc.hh

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