gpu_static_inst.hh

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/*
 * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
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 * For use for simulation and test purposes only
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#ifndef __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
#define __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
 
#include "arch/gcn3/operand.hh"
#include "arch/gcn3/registers.hh"
#include "gpu-compute/gpu_static_inst.hh"
#include "gpu-compute/scalar_register_file.hh"
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
 
namespace Gcn3ISA
{
    class GCN3GPUStaticInst : public GPUStaticInst
    {
      public:
        GCN3GPUStaticInst(const std::string &opcode);
        ~GCN3GPUStaticInst();
 
        void generateDisassembly() override { disassembly = _opcode; }
 
        bool
        isFlatScratchRegister(int opIdx) override
        {
            return isFlatScratchReg(opIdx);
        }
 
        bool
        isExecMaskRegister(int opIdx) override
        {
            return isExecMask(opIdx);
        }
 
        bool isScalarRegister(int opIdx) override { return false; }
        bool isVectorRegister(int opIdx) override { return false; }
        bool isSrcOperand(int opIdx) override { return false; }
        bool isDstOperand(int opIdx) override { return false; }
        int getOperandSize(int opIdx) override { return 0; }
 
        int
        getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
        {
            return 0;
        }
 
        int coalescerTokenCount() const override { return 1; }
        ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
 
      protected:
        void panicUnimplemented() const;
 
        ScalarRegU32 _srcLiteral;
    }; // class GCN3GPUStaticInst
 
} // namespace Gcn3ISA
#endif //__ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__