gem5  v21.0.1.0
se_workload.cc
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27 
29 
30 #include "arch/sparc/process.hh"
31 #include "arch/sparc/registers.hh"
32 #include "arch/sparc/types.hh"
33 #include "base/logging.hh"
34 #include "cpu/thread_context.hh"
35 
36 namespace SparcISA
37 {
38 
41 };
42 
43 bool
45 {
46  return dynamic_cast<Sparc64Process *>(tc->getProcessPtr());
47 }
48 
49 void
51 {
52  PCState pc = tc->pcState();
53  switch (trapNum) {
54  case 0x01: // Software breakpoint
55  warn("Software breakpoint encountered at pc %#x.", pc.pc());
56  break;
57  case 0x02: // Division by zero
58  warn("Software signaled a division by zero at pc %#x.", pc.pc());
59  break;
60  case 0x03: // Flush window trap
61  flushWindows(tc);
62  break;
63  case 0x04: // Clean windows
64  warn("Ignoring process request for clean register "
65  "windows at pc %#x.", pc.pc());
66  break;
67  case 0x05: // Range check
68  warn("Software signaled a range check at pc %#x.", pc.pc());
69  break;
70  case 0x06: // Fix alignment
71  warn("Ignoring process request for os assisted unaligned accesses "
72  "at pc %#x.", pc.pc());
73  break;
74  case 0x07: // Integer overflow
75  warn("Software signaled an integer overflow at pc %#x.", pc.pc());
76  break;
77  case 0x32: // Get integer condition codes
78  warn("Ignoring process request to get the integer condition codes "
79  "at pc %#x.", pc.pc());
80  break;
81  case 0x33: // Set integer condition codes
82  warn("Ignoring process request to set the integer condition codes "
83  "at pc %#x.", pc.pc());
84  break;
85  default:
86  panic("Unimplemented trap to operating system: trap number %#x.",
87  trapNum);
88  }
89 }
90 
91 void
93 {
94  RegVal Cansave = tc->readIntReg(INTREG_CANSAVE);
95  RegVal Canrestore = tc->readIntReg(INTREG_CANRESTORE);
96  RegVal Otherwin = tc->readIntReg(INTREG_OTHERWIN);
97  RegVal CWP = tc->readMiscReg(MISCREG_CWP);
98  RegVal origCWP = CWP;
99 
100  const bool is_64 = is64(tc);
101  const size_t reg_bytes = is_64 ? 8 : 4;
102  uint8_t bytes[8];
103 
104  CWP = (CWP + Cansave + 2) % NWindows;
105  while (NWindows - 2 - Cansave != 0) {
106  panic_if(Otherwin, "Otherwin non-zero.");
107 
108  tc->setMiscReg(MISCREG_CWP, CWP);
109  // Do the stores
111 
112  Addr addr = is_64 ? sp + 2047 : sp;
113  for (int index = 16; index < 32; index++) {
114  if (is_64) {
115  uint64_t regVal = htobe<uint64_t>(tc->readIntReg(index));
116  memcpy(bytes, &regVal, reg_bytes);
117  } else {
118  uint32_t regVal = htobe<uint32_t>(tc->readIntReg(index));
119  memcpy(bytes, &regVal, reg_bytes);
120  }
121  if (!tc->getVirtProxy().tryWriteBlob(addr, bytes, reg_bytes)) {
122  warn("Failed to save register to the stack when "
123  "flushing windows.");
124  }
125  addr += reg_bytes;
126  }
127  Canrestore--;
128  Cansave++;
129  CWP = (CWP + 1) % NWindows;
130  }
131 
132  tc->setIntReg(INTREG_CANSAVE, Cansave);
133  tc->setIntReg(INTREG_CANRESTORE, Canrestore);
134  tc->setMiscReg(MISCREG_CWP, origCWP);
135 }
136 
137 } // namespace SparcISA
warn
#define warn(...)
Definition: logging.hh:239
process.hh
MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:44
SparcISA::SEWorkload::handleTrap
virtual void handleTrap(ThreadContext *tc, int trapNum)
Definition: se_workload.cc:50
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
GenericISA::DelaySlotUPCState
Definition: types.hh:391
std::vector< int >
ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:41
SparcISA::SEWorkload::flushWindows
virtual void flushWindows(ThreadContext *tc)
Definition: se_workload.cc:92
SparcISA::INTREG_O3
@ INTREG_O3
Definition: registers.hh:62
PortProxy::tryWriteBlob
virtual bool tryWriteBlob(Addr addr, const void *p, int size) const
Write size bytes from p to address.
Definition: port_proxy.hh:152
SparcISA
Definition: asi.cc:31
SparcISA::INTREG_CANRESTORE
@ INTREG_CANRESTORE
Definition: registers.hh:77
SparcISA::INTREG_O4
@ INTREG_O4
Definition: registers.hh:63
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
SparcISA::INTREG_O0
@ INTREG_O0
Definition: registers.hh:62
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
SparcISA::INTREG_O5
@ INTREG_O5
Definition: registers.hh:63
SparcISA::INTREG_O1
@ INTREG_O1
Definition: registers.hh:62
SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: registers.hh:76
SparcISA::SEWorkload::is64
bool is64(ThreadContext *tc)
Definition: se_workload.cc:44
types.hh
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs_types.hh:71
Sparc64Process
Definition: process.hh:100
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
SparcISA::SEWorkload::BaseSyscallABI::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: se_workload.hh:54
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
SparcISA::INTREG_O2
@ INTREG_O2
Definition: registers.hh:62
X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:80
ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
logging.hh
se_workload.hh
registers.hh
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
SparcISA::INTREG_OTHERWIN
@ INTREG_OTHERWIN
Definition: registers.hh:79
thread_context.hh
RegVal
uint64_t RegVal
Definition: types.hh:174
SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: miscregs.hh:65
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
SparcISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:90

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