thread_context.hh

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#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
#define __CPU_CHECKER_THREAD_CONTEXT_HH__
 
#include "arch/types.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Checker.hh"
 
namespace TheISA
{
    class Decoder;
} // namespace TheISA
 
template <class TC>
class CheckerThreadContext : public ThreadContext
{
  public:
    CheckerThreadContext(TC *actual_tc,
                         CheckerCPU *checker_cpu)
        : actualTC(actual_tc), checkerTC(checker_cpu->thread),
          checkerCPU(checker_cpu)
    { }
 
  private:
    TC *actualTC;
    SimpleThread *checkerTC;
    CheckerCPU *checkerCPU;
 
  public:
    bool schedule(PCEvent *e) override { return actualTC->schedule(e); }
    bool remove(PCEvent *e) override { return actualTC->remove(e); }
 
    void
    scheduleInstCountEvent(Event *event, Tick count) override
    {
        actualTC->scheduleInstCountEvent(event, count);
    }
    void
    descheduleInstCountEvent(Event *event) override
    {
        actualTC->descheduleInstCountEvent(event);
    }
    Tick
    getCurrentInstCount() override
    {
        return actualTC->getCurrentInstCount();
    }
 
    BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
 
    uint32_t socketId() const override { return actualTC->socketId(); }
 
    int cpuId() const override { return actualTC->cpuId(); }
 
    ContextID contextId() const override { return actualTC->contextId(); }
 
    void
    setContextId(ContextID id) override
    {
       actualTC->setContextId(id);
       checkerTC->setContextId(id);
    }
 
    int threadId() const override { return actualTC->threadId(); }
    void
    setThreadId(int id) override
    {
        checkerTC->setThreadId(id);
        actualTC->setThreadId(id);
    }
 
    BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
 
    CheckerCPU *
    getCheckerCpuPtr() override
    {
        return checkerCPU;
    }
 
    BaseISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
 
    TheISA::Decoder *
    getDecoderPtr() override
    {
        return actualTC->getDecoderPtr();
    }
 
    System *getSystemPtr() override { return actualTC->getSystemPtr(); }
 
    Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
 
    void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
 
    PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
 
    PortProxy &
    getVirtProxy() override
    {
        return actualTC->getVirtProxy();
    }
 
    void
    initMemProxies(ThreadContext *tc) override
    {
        actualTC->initMemProxies(tc);
    }
 
    void
    connectMemPorts(ThreadContext *tc)
    {
        actualTC->connectMemPorts(tc);
    }
 
    Status status() const override { return actualTC->status(); }
 
    void
    setStatus(Status new_status) override
    {
        actualTC->setStatus(new_status);
        checkerTC->setStatus(new_status);
    }
 
    void activate() override { actualTC->activate(); }
 
    void suspend() override { actualTC->suspend(); }
 
    void halt() override { actualTC->halt(); }
 
    void
    takeOverFrom(ThreadContext *oldContext) override
    {
        actualTC->takeOverFrom(oldContext);
        checkerTC->copyState(oldContext);
    }
 
    void
    regStats(const std::string &name) override
    {
        actualTC->regStats(name);
        checkerTC->regStats(name);
    }
 
    Tick readLastActivate() override { return actualTC->readLastActivate(); }
    Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
 
    // @todo: Do I need this?
    void
    copyArchRegs(ThreadContext *tc) override
    {
        actualTC->copyArchRegs(tc);
        checkerTC->copyArchRegs(tc);
    }
 
    void
    clearArchRegs() override
    {
        actualTC->clearArchRegs();
        checkerTC->clearArchRegs();
    }
 
    //
    // New accessors for new decoder.
    //
    RegVal
    readIntReg(RegIndex reg_idx) const override
    {
        return actualTC->readIntReg(reg_idx);
    }
 
    RegVal
    readFloatReg(RegIndex reg_idx) const override
    {
        return actualTC->readFloatReg(reg_idx);
    }
 
    const TheISA::VecRegContainer &
    readVecReg (const RegId &reg) const override
    {
        return actualTC->readVecReg(reg);
    }
 
    TheISA::VecRegContainer &
    getWritableVecReg (const RegId &reg) override
    {
        return actualTC->getWritableVecReg(reg);
    }
 
    ConstVecLane8
    readVec8BitLaneReg(const RegId &reg) const override
    {
        return actualTC->readVec8BitLaneReg(reg);
    }
 
    ConstVecLane16
    readVec16BitLaneReg(const RegId &reg) const override
    {
        return actualTC->readVec16BitLaneReg(reg);
    }
 
    ConstVecLane32
    readVec32BitLaneReg(const RegId &reg) const override
    {
        return actualTC->readVec32BitLaneReg(reg);
    }
 
    ConstVecLane64
    readVec64BitLaneReg(const RegId &reg) const override
    {
        return actualTC->readVec64BitLaneReg(reg);
    }
 
    virtual void
    setVecLane(const RegId &reg,
               const LaneData<LaneSize::Byte> &val) override
    {
        return actualTC->setVecLane(reg, val);
    }
    virtual void
    setVecLane(const RegId &reg,
               const LaneData<LaneSize::TwoByte> &val) override
    {
        return actualTC->setVecLane(reg, val);
    }
    virtual void
    setVecLane(const RegId &reg,
               const LaneData<LaneSize::FourByte> &val) override
    {
        return actualTC->setVecLane(reg, val);
    }
    virtual void
    setVecLane(const RegId &reg,
               const LaneData<LaneSize::EightByte> &val) override
    {
        return actualTC->setVecLane(reg, val);
    }
    const TheISA::VecElem &
    readVecElem(const RegId& reg) const override
    {
        return actualTC->readVecElem(reg);
    }
 
    const TheISA::VecPredRegContainer &
    readVecPredReg(const RegId& reg) const override
    {
        return actualTC->readVecPredReg(reg);
    }
 
    TheISA::VecPredRegContainer &
    getWritableVecPredReg(const RegId& reg) override
    {
        return actualTC->getWritableVecPredReg(reg);
    }
 
    RegVal
    readCCReg(RegIndex reg_idx) const override
    {
        return actualTC->readCCReg(reg_idx);
    }
 
    void
    setIntReg(RegIndex reg_idx, RegVal val) override
    {
        actualTC->setIntReg(reg_idx, val);
        checkerTC->setIntReg(reg_idx, val);
    }
 
    void
    setFloatReg(RegIndex reg_idx, RegVal val) override
    {
        actualTC->setFloatReg(reg_idx, val);
        checkerTC->setFloatReg(reg_idx, val);
    }
 
    void
    setVecReg(const RegId& reg, const TheISA::VecRegContainer& val) override
    {
        actualTC->setVecReg(reg, val);
        checkerTC->setVecReg(reg, val);
    }
 
    void
    setVecElem(const RegId& reg, const TheISA::VecElem& val) override
    {
        actualTC->setVecElem(reg, val);
        checkerTC->setVecElem(reg, val);
    }
 
    void
    setVecPredReg(const RegId& reg,
            const TheISA::VecPredRegContainer& val) override
    {
        actualTC->setVecPredReg(reg, val);
        checkerTC->setVecPredReg(reg, val);
    }
 
    void
    setCCReg(RegIndex reg_idx, RegVal val) override
    {
        actualTC->setCCReg(reg_idx, val);
        checkerTC->setCCReg(reg_idx, val);
    }
 
    TheISA::PCState pcState() const override { return actualTC->pcState(); }
 
    void
    pcState(const TheISA::PCState &val) override
    {
        DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
                         val, checkerTC->pcState());
        checkerTC->pcState(val);
        checkerCPU->recordPCChange(val);
        return actualTC->pcState(val);
    }
 
    void
    setNPC(Addr val)
    {
        checkerTC->setNPC(val);
        actualTC->setNPC(val);
    }
 
    void
    pcStateNoRecord(const TheISA::PCState &val) override
    {
        return actualTC->pcState(val);
    }
 
    Addr instAddr() const override { return actualTC->instAddr(); }
 
    Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
 
    MicroPC microPC() const override { return actualTC->microPC(); }
 
    RegVal
    readMiscRegNoEffect(RegIndex misc_reg) const override
    {
        return actualTC->readMiscRegNoEffect(misc_reg);
    }
 
    RegVal
    readMiscReg(RegIndex misc_reg) override
    {
        return actualTC->readMiscReg(misc_reg);
    }
 
    void
    setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
    {
        DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                         " and O3..\n", misc_reg);
        checkerTC->setMiscRegNoEffect(misc_reg, val);
        actualTC->setMiscRegNoEffect(misc_reg, val);
    }
 
    void
    setMiscReg(RegIndex misc_reg, RegVal val) override
    {
        DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                         " and O3..\n", misc_reg);
        checkerTC->setMiscReg(misc_reg, val);
        actualTC->setMiscReg(misc_reg, val);
    }
 
    RegId
    flattenRegId(const RegId& regId) const override
    {
        return actualTC->flattenRegId(regId);
    }
 
    unsigned
    readStCondFailures() const override
    {
        return actualTC->readStCondFailures();
    }
 
    void
    setStCondFailures(unsigned sc_failures) override
    {
        actualTC->setStCondFailures(sc_failures);
    }
 
    Counter
    readFuncExeInst() const override
    {
        return actualTC->readFuncExeInst();
    }
 
    RegVal
    readIntRegFlat(RegIndex idx) const override
    {
        return actualTC->readIntRegFlat(idx);
    }
 
    void
    setIntRegFlat(RegIndex idx, RegVal val) override
    {
        actualTC->setIntRegFlat(idx, val);
    }
 
    RegVal
    readFloatRegFlat(RegIndex idx) const override
    {
        return actualTC->readFloatRegFlat(idx);
    }
 
    void
    setFloatRegFlat(RegIndex idx, RegVal val) override
    {
        actualTC->setFloatRegFlat(idx, val);
    }
 
    const TheISA::VecRegContainer &
    readVecRegFlat(RegIndex idx) const override
    {
        return actualTC->readVecRegFlat(idx);
    }
 
    TheISA::VecRegContainer &
    getWritableVecRegFlat(RegIndex idx) override
    {
        return actualTC->getWritableVecRegFlat(idx);
    }
 
    void
    setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer& val) override
    {
        actualTC->setVecRegFlat(idx, val);
    }
 
    const TheISA::VecElem &
    readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
    {
        return actualTC->readVecElemFlat(idx, elem_idx);
    }
 
    void
    setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
            const TheISA::VecElem& val) override
    {
        actualTC->setVecElemFlat(idx, elem_idx, val);
    }
 
    const TheISA::VecPredRegContainer &
    readVecPredRegFlat(RegIndex idx) const override
    {
        return actualTC->readVecPredRegFlat(idx);
    }
 
    TheISA::VecPredRegContainer &
    getWritableVecPredRegFlat(RegIndex idx) override
    {
        return actualTC->getWritableVecPredRegFlat(idx);
    }
 
    void
    setVecPredRegFlat(RegIndex idx,
            const TheISA::VecPredRegContainer& val) override
    {
        actualTC->setVecPredRegFlat(idx, val);
    }
 
    RegVal
    readCCRegFlat(RegIndex idx) const override
    {
        return actualTC->readCCRegFlat(idx);
    }
 
    void
    setCCRegFlat(RegIndex idx, RegVal val) override
    {
        actualTC->setCCRegFlat(idx, val);
    }
 
    // hardware transactional memory
    void
    htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
    {
        panic("function not implemented");
    }
 
    BaseHTMCheckpointPtr&
    getHtmCheckpointPtr() override
    {
        panic("function not implemented");
    }
 
    void
    setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
    {
        panic("function not implemented");
    }
 
};
 
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__