static_inst.hh

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#ifndef __CPU_STATIC_INST_HH__
#define __CPU_STATIC_INST_HH__
 
#include <bitset>
#include <memory>
#include <string>
 
#include "arch/registers.hh"
#include "arch/types.hh"
#include "base/logging.hh"
#include "base/refcnt.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/op_class.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/thread_context.hh"
#include "enums/StaticInstFlags.hh"
#include "sim/byteswap.hh"
 
// forward declarations
class Packet;
 
class ExecContext;
 
namespace Loader
{
class SymbolTable;
} // namespace Loader
 
namespace Trace
{
class InstRecord;
} // namespace Trace
 
class StaticInst : public RefCounted, public StaticInstFlags
{
  public:
    using RegIdArrayPtr = RegId (StaticInst:: *)[];
 
  private:
    RegIdArrayPtr _srcRegIdxPtr = nullptr;
 
    RegIdArrayPtr _destRegIdxPtr = nullptr;
 
  protected:
 
    std::bitset<Num_Flags> flags;
 
    OpClass _opClass;
 
    int8_t _numSrcRegs;
 
    int8_t _numDestRegs;
 
 
    int8_t _numFPDestRegs;
    int8_t _numIntDestRegs;
    int8_t _numCCDestRegs;
 
    int8_t _numVecDestRegs;
    int8_t _numVecElemDestRegs;
    int8_t _numVecPredDestRegs;
  public:
 
 
    int8_t numSrcRegs()  const { return _numSrcRegs; }
    int8_t numDestRegs() const { return _numDestRegs; }
    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
    int8_t numIntDestRegs() const { return _numIntDestRegs; }
    int8_t numVecDestRegs() const { return _numVecDestRegs; }
    int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
    int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
    int8_t numCCDestRegs() const { return _numCCDestRegs; }
 
 
 
    bool isNop()          const { return flags[IsNop]; }
 
    bool
    isMemRef() const
    {
        return flags[IsLoad] || flags[IsStore] || flags[IsAtomic];
    }
    bool isLoad()         const { return flags[IsLoad]; }
    bool isStore()        const { return flags[IsStore]; }
    bool isAtomic()       const { return flags[IsAtomic]; }
    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
    bool isPrefetch()     const { return isInstPrefetch() ||
                                         isDataPrefetch(); }
 
    bool isInteger()      const { return flags[IsInteger]; }
    bool isFloating()     const { return flags[IsFloating]; }
    bool isVector()       const { return flags[IsVector]; }
 
    bool isControl()      const { return flags[IsControl]; }
    bool isCall()         const { return flags[IsCall]; }
    bool isReturn()       const { return flags[IsReturn]; }
    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
    bool isCondCtrl()     const { return flags[IsCondControl]; }
    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 
    bool isSerializing()  const { return flags[IsSerializing] ||
                                      flags[IsSerializeBefore] ||
                                      flags[IsSerializeAfter]; }
    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
    bool isSquashAfter() const { return flags[IsSquashAfter]; }
    bool
    isFullMemBarrier() const
    {
        return flags[IsReadBarrier] && flags[IsWriteBarrier];
    }
    bool isReadBarrier() const { return flags[IsReadBarrier]; }
    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
    bool isQuiesce() const { return flags[IsQuiesce]; }
    bool isUnverifiable() const { return flags[IsUnverifiable]; }
    bool isSyscall() const { return flags[IsSyscall]; }
    bool isMacroop() const { return flags[IsMacroop]; }
    bool isMicroop() const { return flags[IsMicroop]; }
    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
    bool isLastMicroop() const { return flags[IsLastMicroop]; }
    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
    // hardware transactional memory
    // HtmCmds must be identified as such in order
    // to provide them with necessary memory ordering semantics.
    bool isHtmStart() const { return flags[IsHtmStart]; }
    bool isHtmStop() const { return flags[IsHtmStop]; }
    bool isHtmCancel() const { return flags[IsHtmCancel]; }
 
    bool
    isHtmCmd() const
    {
        return isHtmStart() || isHtmStop() || isHtmCancel();
    }
 
    void setFirstMicroop() { flags[IsFirstMicroop] = true; }
    void setLastMicroop() { flags[IsLastMicroop] = true; }
    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
    void setFlag(Flags f) { flags[f] = true; }
 
    OpClass opClass()     const { return _opClass; }
 
 
    const RegId &destRegIdx(int i) const { return (this->*_destRegIdxPtr)[i]; }
 
    void
    setDestRegIdx(int i, const RegId &val)
    {
        (this->*_destRegIdxPtr)[i] = val;
    }
 
    const RegId &srcRegIdx(int i) const { return (this->*_srcRegIdxPtr)[i]; }
 
    void
    setSrcRegIdx(int i, const RegId &val)
    {
        (this->*_srcRegIdxPtr)[i] = val;
    }
 
    static StaticInstPtr nullStaticInstPtr;
 
    static StaticInstPtr nopStaticInstPtr;
 
    const TheISA::ExtMachInst machInst;
 
    virtual uint64_t getEMI() const { return 0; }
 
  protected:
 
    void
    setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)
    {
        _srcRegIdxPtr = src;
        _destRegIdxPtr = dest;
    }
 
    const char *mnemonic;
 
    mutable std::string *cachedDisassembly;
 
    virtual std::string
    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const = 0;
 
    StaticInst(const char *_mnemonic, TheISA::ExtMachInst _machInst,
            OpClass __opClass)
        : _opClass(__opClass),
          _numSrcRegs(0), _numDestRegs(0), _numFPDestRegs(0),
          _numIntDestRegs(0), _numCCDestRegs(0), _numVecDestRegs(0),
          _numVecElemDestRegs(0), _numVecPredDestRegs(0), machInst(_machInst),
          mnemonic(_mnemonic), cachedDisassembly(0)
    { }
 
  public:
    virtual ~StaticInst();
 
    virtual Fault execute(ExecContext *xc,
                          Trace::InstRecord *traceData) const = 0;
 
    virtual Fault initiateAcc(ExecContext *xc,
                              Trace::InstRecord *traceData) const
    {
        panic("initiateAcc not defined!");
    }
 
    virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
                              Trace::InstRecord *traceData) const
    {
        panic("completeAcc not defined!");
    }
 
    virtual void advancePC(TheISA::PCState &pcState) const = 0;
 
    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
 
    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
 
    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
 
    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
                         TheISA::PCState &tgt) const;
 
    virtual const std::string &disassemble(Addr pc,
        const Loader::SymbolTable *symtab=nullptr) const;
 
    void printFlags(std::ostream &outs, const std::string &separator) const;
 
    std::string getName() { return mnemonic; }
 
  protected:
    template<typename T>
    size_t
    simpleAsBytes(void *buf, size_t max_size, const T &t)
    {
        size_t size = sizeof(T);
        if (size <= max_size)
            *reinterpret_cast<T *>(buf) = htole<T>(t);
        return size;
    }
 
  public:
    virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
};
 
#endif // __CPU_STATIC_INST_HH__