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gem5
v21.0.1.0
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#include <cmath>#include <cstdint>#include <sstream>#include <string>#include "arch/riscv/registers.hh"#include "base/types.hh"#include "cpu/reg_class.hh"#include "cpu/static_inst.hh"#include "cpu/thread_context.hh"Go to the source code of this file.
Namespaces | |
| RiscvISA | |
Functions | |
| template<typename T > | |
| bool | RiscvISA::isquietnan (T val) |
| template<> | |
| bool | RiscvISA::isquietnan< float > (float val) |
| template<> | |
| bool | RiscvISA::isquietnan< double > (double val) |
| template<typename T > | |
| bool | RiscvISA::issignalingnan (T val) |
| template<> | |
| bool | RiscvISA::issignalingnan< float > (float val) |
| template<> | |
| bool | RiscvISA::issignalingnan< double > (double val) |
| PCState | RiscvISA::buildRetPC (const PCState &curPC, const PCState &callPC) |
| void | RiscvISA::copyRegs (ThreadContext *src, ThreadContext *dest) |
| std::string | RiscvISA::registerName (RegId reg) |
| void | RiscvISA::advancePC (PCState &pc, const StaticInstPtr &inst) |