|
gem5
v21.0.1.0
|
Public Attributes | |
| uint16_t | fcw |
| uint16_t | fsw |
| uint8_t | ftwx |
| uint8_t | pad0 |
| uint16_t | last_opcode |
| union { | |
| struct { | |
| uint32_t fpu_ip | |
| uint16_t fpu_cs | |
| uint16_t pad1 | |
| uint32_t fpu_dp | |
| uint16_t fpu_ds | |
| uint16_t pad2 | |
| } ctrl32 | |
| struct { | |
| uint64_t fpu_ip | |
| uint64_t fpu_dp | |
| } ctrl64 | |
| }; | |
| uint32_t | mxcsr |
| uint32_t | mxcsr_mask |
| uint8_t | fpr [8][16] |
| uint8_t | xmm [16][16] |
| uint64_t | reserved [12] |
Definition at line 71 of file x86_cpu.cc.
| union { ... } |
| struct { ... } FXSave::ctrl32 |
| struct { ... } FXSave::ctrl64 |
Referenced by X86KvmCPU::updateThreadContextXSave().
| uint16_t FXSave::fcw |
Definition at line 73 of file x86_cpu.cc.
| uint8_t FXSave::fpr[8][16] |
Definition at line 96 of file x86_cpu.cc.
| uint16_t FXSave::fpu_cs |
Definition at line 81 of file x86_cpu.cc.
| uint32_t FXSave::fpu_dp |
Definition at line 83 of file x86_cpu.cc.
| uint64_t FXSave::fpu_dp |
Definition at line 90 of file x86_cpu.cc.
| uint16_t FXSave::fpu_ds |
Definition at line 84 of file x86_cpu.cc.
| uint32_t FXSave::fpu_ip |
Definition at line 80 of file x86_cpu.cc.
| uint64_t FXSave::fpu_ip |
Definition at line 89 of file x86_cpu.cc.
| uint16_t FXSave::fsw |
Definition at line 74 of file x86_cpu.cc.
| uint8_t FXSave::ftwx |
Definition at line 75 of file x86_cpu.cc.
| uint16_t FXSave::last_opcode |
Definition at line 77 of file x86_cpu.cc.
| uint32_t FXSave::mxcsr |
Definition at line 93 of file x86_cpu.cc.
| uint32_t FXSave::mxcsr_mask |
Definition at line 94 of file x86_cpu.cc.
| uint8_t FXSave::pad0 |
Definition at line 76 of file x86_cpu.cc.
| uint16_t FXSave::pad1 |
Definition at line 82 of file x86_cpu.cc.
| uint16_t FXSave::pad2 |
Definition at line 85 of file x86_cpu.cc.
| uint64_t FXSave::reserved[12] |
Definition at line 99 of file x86_cpu.cc.
| uint8_t FXSave::xmm[16][16] |
Definition at line 97 of file x86_cpu.cc.