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gem5
v21.1.0.2
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This is the complete list of members for gem5::ArmISA::MemoryEx64, including all inherited members.
| _destRegIdxPtr | gem5::StaticInst | private |
| _numCCDestRegs | gem5::StaticInst | protected |
| _numDestRegs | gem5::StaticInst | protected |
| _numFPDestRegs | gem5::StaticInst | protected |
| _numIntDestRegs | gem5::StaticInst | protected |
| _numSrcRegs | gem5::StaticInst | protected |
| _numVecDestRegs | gem5::StaticInst | protected |
| _numVecElemDestRegs | gem5::StaticInst | protected |
| _numVecPredDestRegs | gem5::StaticInst | protected |
| _opClass | gem5::StaticInst | protected |
| _srcRegIdxPtr | gem5::StaticInst | private |
| aarch64 | gem5::ArmISA::ArmStaticInst | protected |
| activateBreakpoint(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| AddrMd_Offset enum value | gem5::ArmISA::Memory64 | |
| AddrMd_PostIndex enum value | gem5::ArmISA::Memory64 | |
| AddrMd_PreIndex enum value | gem5::ArmISA::Memory64 | |
| AddrMode enum name | gem5::ArmISA::Memory64 | |
| advancePC(PCState &pcState) const override | gem5::ArmISA::MightBeMicro64 | inlineprotected |
| gem5::StaticInst::advancePC(TheISA::PCState &pc_state) const =0 | gem5::StaticInst | pure virtual |
| advSIMDFPAccessTrap64(ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| annotateFault(ArmFault *fault) | gem5::ArmISA::ArmStaticInst | inlinevirtual |
| ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | gem5::ArmISA::ArmStaticInst | inlineprotected |
| asBytes(void *buf, size_t max_size) override | gem5::ArmISA::ArmStaticInst | inlinevirtual |
| base | gem5::ArmISA::Memory64 | protected |
| baseIsSP | gem5::ArmISA::Memory64 | protected |
| branchTarget(const TheISA::PCState &pc) const | gem5::StaticInst | virtual |
| branchTarget(ThreadContext *tc) const | gem5::StaticInst | virtual |
| buildRetPC(const PCState &curPC, const PCState &callPC) const override | gem5::ArmISA::ArmStaticInst | inlineprotected |
| gem5::StaticInst::buildRetPC(const TheISA::PCState &cur_pc, const TheISA::PCState &call_pc) const | gem5::StaticInst | inlinevirtual |
| cachedDisassembly | gem5::StaticInst | mutableprotected |
| checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const | gem5::ArmISA::ArmStaticInst | protected |
| checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const | gem5::ArmISA::ArmStaticInst | protected |
| checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const | gem5::ArmISA::ArmStaticInst | protected |
| checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | gem5::ArmISA::ArmStaticInst | protected |
| completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const | gem5::StaticInst | inlinevirtual |
| count | gem5::RefCounted | mutableprivate |
| cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| cSwap(T val, bool big) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| cSwap(T val, bool big) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| decref() const | gem5::RefCounted | inline |
| dest | gem5::ArmISA::Memory64 | protected |
| destRegIdx(int i) const | gem5::StaticInst | inline |
| disabledFault() const | gem5::ArmISA::ArmStaticInst | inlineprotected |
| disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const | gem5::StaticInst | virtual |
| encoding() const | gem5::ArmISA::ArmStaticInst | inline |
| execute(ExecContext *xc, Trace::InstRecord *traceData) const =0 | gem5::StaticInst | pure virtual |
| extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const | gem5::ArmISA::ArmStaticInst | protected |
| fetchMicroop(MicroPC microPC) const override | gem5::ArmISA::Memory64 | inlineprotectedvirtual |
| flags | gem5::StaticInst | protected |
| generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) const | gem5::ArmISA::ArmStaticInst | protected |
| generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override | gem5::ArmISA::MemoryEx64 | protectedvirtual |
| getCurSveVecLen(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlinestatic |
| getCurSveVecLenInBits(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | static |
| getCurSveVecLenInQWords(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlinestatic |
| getEMI() const override | gem5::ArmISA::ArmStaticInst | inlineprotectedvirtual |
| getIntWidth() const | gem5::ArmISA::ArmStaticInst | inline |
| getName() | gem5::StaticInst | inline |
| getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const | gem5::ArmISA::ArmStaticInst | protected |
| hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const | gem5::StaticInst | |
| incref() const | gem5::RefCounted | inline |
| initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const | gem5::StaticInst | inlinevirtual |
| instSize() const | gem5::ArmISA::ArmStaticInst | inline |
| intWidth | gem5::ArmISA::ArmStaticInst | protected |
| isAtomic() const | gem5::StaticInst | inline |
| isCall() const | gem5::StaticInst | inline |
| isCondCtrl() const | gem5::StaticInst | inline |
| isControl() const | gem5::StaticInst | inline |
| isDataPrefetch() const | gem5::StaticInst | inline |
| isDelayedCommit() const | gem5::StaticInst | inline |
| isDirectCtrl() const | gem5::StaticInst | inline |
| isFirstMicroop() const | gem5::StaticInst | inline |
| isFloating() const | gem5::StaticInst | inline |
| isFullMemBarrier() const | gem5::StaticInst | inline |
| isHtmCancel() const | gem5::StaticInst | inline |
| isHtmCmd() const | gem5::StaticInst | inline |
| isHtmStart() const | gem5::StaticInst | inline |
| isHtmStop() const | gem5::StaticInst | inline |
| isIndirectCtrl() const | gem5::StaticInst | inline |
| isInstPrefetch() const | gem5::StaticInst | inline |
| isInteger() const | gem5::StaticInst | inline |
| isLastMicroop() const | gem5::StaticInst | inline |
| isLoad() const | gem5::StaticInst | inline |
| isMacroop() const | gem5::StaticInst | inline |
| isMemRef() const | gem5::StaticInst | inline |
| isMicroop() const | gem5::StaticInst | inline |
| isNonSpeculative() const | gem5::StaticInst | inline |
| isNop() const | gem5::StaticInst | inline |
| isPrefetch() const | gem5::StaticInst | inline |
| isQuiesce() const | gem5::StaticInst | inline |
| isReadBarrier() const | gem5::StaticInst | inline |
| isReturn() const | gem5::StaticInst | inline |
| isSerializeAfter() const | gem5::StaticInst | inline |
| isSerializeBefore() const | gem5::StaticInst | inline |
| isSerializing() const | gem5::StaticInst | inline |
| isSquashAfter() const | gem5::StaticInst | inline |
| isStore() const | gem5::StaticInst | inline |
| isStoreConditional() const | gem5::StaticInst | inline |
| isSyscall() const | gem5::StaticInst | inline |
| isUncondCtrl() const | gem5::StaticInst | inline |
| isUnverifiable() const | gem5::StaticInst | inline |
| isVector() const | gem5::StaticInst | inline |
| isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const | gem5::ArmISA::ArmStaticInst | inlineprotected |
| isWriteBarrier() const | gem5::StaticInst | inline |
| machInst | gem5::ArmISA::ArmStaticInst | protected |
| memAccessFlags | gem5::ArmISA::Memory64 | protected |
| Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base) | gem5::ArmISA::Memory64 | inlineprotected |
| MemoryEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result) | gem5::ArmISA::MemoryEx64 | inlineprotected |
| MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | gem5::ArmISA::MightBeMicro64 | inlineprotected |
| mnemonic | gem5::StaticInst | protected |
| nullStaticInstPtr | gem5::StaticInst | static |
| numCCDestRegs() const | gem5::StaticInst | inline |
| numDestRegs() const | gem5::StaticInst | inline |
| numFPDestRegs() const | gem5::StaticInst | inline |
| numIntDestRegs() const | gem5::StaticInst | inline |
| numMicroops | gem5::ArmISA::Memory64 | protectedstatic |
| numSrcRegs() const | gem5::StaticInst | inline |
| numVecDestRegs() const | gem5::StaticInst | inline |
| numVecElemDestRegs() const | gem5::StaticInst | inline |
| numVecPredDestRegs() const | gem5::StaticInst | inline |
| opClass() const | gem5::StaticInst | inline |
| operator=(const RefCounted &) | gem5::RefCounted | private |
| printCCReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const | gem5::ArmISA::ArmStaticInst | protected |
| printDataInst(std::ostream &os, bool withImm) const | gem5::ArmISA::ArmStaticInst | protected |
| printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const | gem5::ArmISA::ArmStaticInst | protected |
| printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const | gem5::ArmISA::ArmStaticInst | protected |
| printFlags(std::ostream &outs, const std::string &separator) const | gem5::StaticInst | |
| printFloatReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const | gem5::ArmISA::ArmStaticInst | protected |
| printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const | gem5::ArmISA::ArmStaticInst | protected |
| printMiscReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const | gem5::ArmISA::ArmStaticInst | protected |
| printPFflags(std::ostream &os, int flag) const | gem5::ArmISA::ArmStaticInst | protected |
| printShiftOperand(std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const | gem5::ArmISA::ArmStaticInst | protected |
| printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) const | gem5::ArmISA::ArmStaticInst | protected |
| printVecPredReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const | gem5::ArmISA::ArmStaticInst | protected |
| readPC(ExecContext *xc) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| RefCounted(const RefCounted &) | gem5::RefCounted | private |
| RefCounted() | gem5::RefCounted | inline |
| RegIdArrayPtr typedef | gem5::StaticInst | |
| result | gem5::ArmISA::MemoryEx64 | protected |
| satInt(int32_t &res, int64_t op, int width) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setAIWNextPC(ExecContext *xc, Addr val) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setDelayedCommit() | gem5::StaticInst | inline |
| setDestRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| setExcAcRel(bool exclusive, bool acrel) | gem5::ArmISA::Memory64 | protected |
| setFirstMicroop() | gem5::StaticInst | inline |
| setFlag(Flags f) | gem5::StaticInst | inline |
| setIWNextPC(ExecContext *xc, Addr val) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setLastMicroop() | gem5::StaticInst | inline |
| setNextPC(ExecContext *xc, Addr val) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest) | gem5::StaticInst | inlineprotected |
| setSrcRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const | gem5::ArmISA::ArmStaticInst | protected |
| simpleAsBytes(void *buf, size_t max_size, const T &t) | gem5::StaticInst | inlineprotected |
| softwareBreakpoint32(ExecContext *xc, uint16_t imm) const | gem5::ArmISA::ArmStaticInst | protected |
| spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| srcRegIdx(int i) const | gem5::StaticInst | inline |
| startDisassembly(std::ostream &os) const | gem5::ArmISA::Memory64 | protected |
| StaticInst(const char *_mnemonic, OpClass op_class) | gem5::StaticInst | inlineprotected |
| sveAccessTrap(ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const | gem5::ArmISA::ArmStaticInst | protected |
| undefinedFault32(ThreadContext *tc, ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| undefinedFault64(ThreadContext *tc, ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| uops | gem5::ArmISA::Memory64 | protected |
| uSatInt(int32_t &res, int64_t op, int width) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| ~Memory64() | gem5::ArmISA::Memory64 | inlineprotectedvirtual |
| ~RefCounted() | gem5::RefCounted | inlinevirtual |
| ~StaticInst() | gem5::StaticInst | inlinevirtual |