#include <static_inst.hh>

Inheritance diagram for gem5::ArmISA::ArmStaticInst:

Public Member Functions
virtual void	annotateFault (ArmFault *fault)

uint8_t	getIntWidth () const

ssize_t	instSize () const
	Returns the byte size of current instruction. More...

MachInst	encoding () const
	Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and contains some instruction metadata, which means it differs from the real opcode. More...

size_t	asBytes (void *buf, size_t max_size) override
	Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More...

Public Member Functions inherited from gem5::StaticInst
int8_t	numSrcRegs () const
	Number of source registers. More...

int8_t	numDestRegs () const
	Number of destination registers. More...

int8_t	numFPDestRegs () const
	Number of floating-point destination regs. More...

int8_t	numIntDestRegs () const
	Number of integer destination regs. More...

int8_t	numVecDestRegs () const
	Number of vector destination regs. More...

int8_t	numVecElemDestRegs () const
	Number of vector element destination regs. More...

int8_t	numVecPredDestRegs () const
	Number of predicate destination regs. More...

int8_t	numCCDestRegs () const
	Number of coprocesor destination regs. More...

bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isVector () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isFullMemBarrier () const

bool	isReadBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isUnverifiable () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isHtmStart () const

bool	isHtmStop () const

bool	isHtmCancel () const

bool	isHtmCmd () const

void	setFirstMicroop ()

void	setLastMicroop ()

void	setDelayedCommit ()

void	setFlag (Flags f)

OpClass	opClass () const
	Operation class. Used to select appropriate function unit in issue. More...

const RegId &	destRegIdx (int i) const
	Return logical index (architectural reg num) of i'th destination reg. More...

void	setDestRegIdx (int i, const RegId &val)

const RegId &	srcRegIdx (int i) const
	Return logical index (architectural reg num) of i'th source reg. More...

void	setSrcRegIdx (int i, const RegId &val)

virtual	~StaticInst ()

virtual Fault	execute (ExecContext xc, Trace::InstRecord traceData) const =0

virtual Fault	initiateAcc (ExecContext xc, Trace::InstRecord traceData) const

virtual Fault	completeAcc (Packet pkt, ExecContext xc, Trace::InstRecord *trace_data) const

virtual void	advancePC (TheISA::PCState &pc_state) const =0

virtual TheISA::PCState	buildRetPC (const TheISA::PCState &cur_pc, const TheISA::PCState &call_pc) const

virtual StaticInstPtr	fetchMicroop (MicroPC upc) const
	Return the microop that goes with a particular micropc. More...

virtual TheISA::PCState	branchTarget (const TheISA::PCState &pc) const
	Return the target address for a PC-relative branch. More...

virtual TheISA::PCState	branchTarget (ThreadContext *tc) const
	Return the target address for an indirect branch (jump). More...

bool	hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
	Return true if the instruction is a control transfer, and if so, return the target address as well. More...

virtual const std::string &	disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const
	Return string representation of disassembled instruction. More...

void	printFlags (std::ostream &outs, const std::string &separator) const
	Print a separator separated list of this instruction's set flag names on the given stream. More...

std::string	getName ()
	Return name of machine instruction. More...

Public Member Functions inherited from gem5::RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...

void	incref () const
	Increment the reference count. More...

void	decref () const
	Decrement the reference count and destroy the object if all references are gone. More...

Static Public Member Functions
static unsigned	getCurSveVecLenInBits (ThreadContext *tc)

static unsigned	getCurSveVecLenInQWords (ThreadContext *tc)

template<typename T >
static unsigned	getCurSveVecLen (ThreadContext *tc)

Protected Member Functions
int32_t	shift_rm_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

int32_t	shift_rm_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

bool	shift_carry_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

bool	shift_carry_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

int64_t	shiftReg64 (uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const

int64_t	extendReg64 (uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const

	ArmStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass)

void	printIntReg (std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
	Print a register name for disassembly given the unique dependence tag number (FP or int). More...

void	printFloatReg (std::ostream &os, RegIndex reg_idx) const

void	printVecReg (std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const

void	printVecPredReg (std::ostream &os, RegIndex reg_idx) const

void	printCCReg (std::ostream &os, RegIndex reg_idx) const

void	printMiscReg (std::ostream &os, RegIndex reg_idx) const

void	printMnemonic (std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const

void	printTarget (std::ostream &os, Addr target, const loader::SymbolTable *symtab) const

void	printCondition (std::ostream &os, unsigned code, bool noImplicit=false) const

void	printMemSymbol (std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const

void	printShiftOperand (std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const

void	printExtendOperand (bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const

void	printPFflags (std::ostream &os, int flag) const

void	printDataInst (std::ostream &os, bool withImm) const

void	printDataInst (std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const

void	advancePC (PCState &pcState) const override

uint64_t	getEMI () const override

PCState	buildRetPC (const PCState &curPC, const PCState &callPC) const override

std::string	generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override
	Internal function to generate disassembly string. More...

Fault	disabledFault () const

bool	isWFxTrapping (ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const

Fault	softwareBreakpoint32 (ExecContext *xc, uint16_t imm) const
	Trigger a Software Breakpoint. More...

Fault	advSIMDFPAccessTrap64 (ExceptionLevel el) const
	Trap an access to Advanced SIMD or FP registers due to access control bits. More...

Fault	checkFPAdvSIMDTrap64 (ThreadContext *tc, CPSR cpsr) const
	Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. More...

Fault	checkFPAdvSIMDEnabled64 (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...

Fault	checkAdvSIMDOrFPEnabled32 (ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
	Check if a VFP/SIMD access from aarch32 should be allowed. More...

Fault	checkForWFxTrap32 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
	Check if WFE/WFI instruction execution in aarch32 should be trapped. More...

Fault	checkForWFxTrap64 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
	Check if WFE/WFI instruction execution in aarch64 should be trapped. More...

Fault	trapWFx (ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const
	WFE/WFI trapping helper function. More...

Fault	checkSETENDEnabled (ThreadContext *tc, CPSR cpsr) const
	Check if SETEND instruction execution in aarch32 should be trapped. More...

Fault	undefinedFault32 (ThreadContext *tc, ExceptionLevel el) const
	UNDEFINED behaviour in AArch32. More...

Fault	undefinedFault64 (ThreadContext *tc, ExceptionLevel el) const
	UNDEFINED behaviour in AArch64. More...

Fault	sveAccessTrap (ExceptionLevel el) const
	Trap an access to SVE registers due to access control bits. More...

Fault	checkSveEnabled (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...

CPSR	getPSTATEFromPSR (ThreadContext *tc, CPSR cpsr, CPSR spsr) const
	Get the new PSTATE from a SPSR register in preparation for an exception return. More...

bool	generalExceptionsToAArch64 (ThreadContext *tc, ExceptionLevel pstateEL) const
	Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2 is using AArch64. More...

Protected Member Functions inherited from gem5::StaticInst
void	setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest)
	Set the pointers which point to the arrays of source and destination register indices. More...

	StaticInst (const char *_mnemonic, OpClass op_class)
	Constructor. More...

template<typename T >
size_t	simpleAsBytes (void *buf, size_t max_size, const T &t)

Static Protected Member Functions
template<int width>
static bool	saturateOp (int32_t &res, int64_t op1, int64_t op2, bool sub=false)

static bool	satInt (int32_t &res, int64_t op, int width)

template<int width>
static bool	uSaturateOp (uint32_t &res, int64_t op1, int64_t op2, bool sub=false)

static bool	uSatInt (int32_t &res, int64_t op, int width)

static void	activateBreakpoint (ThreadContext *tc)

static uint32_t	cpsrWriteByInstr (CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)

static uint32_t	spsrWriteByInstr (uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)

static Addr	readPC (ExecContext *xc)

static void	setNextPC (ExecContext *xc, Addr val)

template<class T >
static T	cSwap (T val, bool big)

template<class T , class E >
static T	cSwap (T val, bool big)

static void	setIWNextPC (ExecContext *xc, Addr val)

static void	setAIWNextPC (ExecContext *xc, Addr val)

Protected Attributes
bool	aarch64

uint8_t	intWidth

ExtMachInst	machInst

Protected Attributes inherited from gem5::StaticInst
std::bitset< Num_Flags >	flags
	Flag values for this instruction. More...

OpClass	_opClass
	See opClass(). More...

int8_t	_numSrcRegs = 0
	See numSrcRegs(). More...

int8_t	_numDestRegs = 0
	See numDestRegs(). More...

int8_t	_numFPDestRegs = 0
	The following are used to track physical register usage for machines with separate int & FP reg files. More...

int8_t	_numIntDestRegs = 0

int8_t	_numCCDestRegs = 0

int8_t	_numVecDestRegs = 0
	To use in architectures with vector register file. More...

int8_t	_numVecElemDestRegs = 0

int8_t	_numVecPredDestRegs = 0

const char *	mnemonic
	Base mnemonic (e.g., "add"). More...

std::unique_ptr< std::string >	cachedDisassembly
	String representation of disassembly (lazily evaluated via disassemble()). More...

Additional Inherited Members
Public Types inherited from gem5::StaticInst
using	RegIdArrayPtr = RegId(StaticInst::*)[]

Static Public Attributes inherited from gem5::StaticInst
static StaticInstPtr	nullStaticInstPtr
	Pointer to a statically allocated "null" instruction object. More...

Detailed Description

Definition at line 63 of file static_inst.hh.

Constructor & Destructor Documentation

◆ ArmStaticInst()

gem5::ArmISA::ArmStaticInst::ArmStaticInst	(	const char *	mnem,
		ExtMachInst	_machInst,
		OpClass	__opClass
	)

inlineprotected

Definition at line 152 of file static_inst.hh.

References aarch64, gem5::bits(), intWidth, and machInst.

Member Function Documentation

◆ activateBreakpoint()

static void gem5::ArmISA::ArmStaticInst::activateBreakpoint ( ThreadContext * tc )

inlinestaticprotected

Definition at line 219 of file static_inst.hh.

References gem5::ArmISA::ISA::getSelfDebug(), and gem5::ArmISA::sd.

Referenced by cpsrWriteByInstr().

◆ advancePC()

void gem5::ArmISA::ArmStaticInst::advancePC ( PCState & pcState ) const

inlineoverrideprotected

Definition at line 200 of file static_inst.hh.

References gem5::GenericISA::SimplePCState< InstWidth >::advance().

◆ advSIMDFPAccessTrap64()

Fault gem5::ArmISA::ArmStaticInst::advSIMDFPAccessTrap64 ( ExceptionLevel el ) const

protected

Trap an access to Advanced SIMD or FP registers due to access control bits.

See aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap in the ARM ARM psueodcode library.

Parameters

el	Target EL for the trap

Definition at line 655 of file static_inst.cc.

References gem5::ArmISA::EC_TRAPPED_SIMD_FP, gem5::ArmISA::el, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, machInst, and panic.

Referenced by checkAdvSIMDOrFPEnabled32(), checkFPAdvSIMDEnabled64(), checkFPAdvSIMDTrap64(), and checkSveEnabled().

◆ annotateFault()

virtual void gem5::ArmISA::ArmStaticInst::annotateFault ( ArmFault * fault )

inlinevirtual

Definition at line 532 of file static_inst.hh.

Referenced by gem5::ArmISA::ArmFault::instrAnnotate().

◆ asBytes()

size_t gem5::ArmISA::ArmStaticInst::asBytes	(	void *	buf,
		size_t	max_size
	)

inlineoverridevirtual

Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

buf is a buffer to hold the bytes. max_size is the size allocated for that buffer by the caller. The return value is how much data was actually put into the buffer, zero if no data was put in the buffer, or the necessary size of the buffer if there wasn't enough space.

Reimplemented from gem5::StaticInst.

Definition at line 560 of file static_inst.hh.

References machInst, and gem5::StaticInst::simpleAsBytes().

◆ buildRetPC()

PCState gem5::ArmISA::ArmStaticInst::buildRetPC	(	const PCState &	curPC,
		const PCState &	callPC
	)		const

inlineoverrideprotected

Definition at line 208 of file static_inst.hh.

◆ checkAdvSIMDOrFPEnabled32()

Fault gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPACR	cpacr,
		NSACR	nsacr,
		FPEXC	fpexc,
		bool	fpexc_check,
		bool	advsimd
	)		const

protected

Check if a VFP/SIMD access from aarch32 should be allowed.

See aarch32/exceptions/traps/AArch32.CheckAdvSIMDOrFPEnabled in the ARM ARM psueodcode library.

Definition at line 726 of file static_inst.cc.

References gem5::ArmISA::advsimd, advSIMDFPAccessTrap64(), checkFPAdvSIMDEnabled64(), checkFPAdvSIMDTrap64(), gem5::ArmISA::currEL(), disabledFault(), gem5::ArmISA::EC_TRAPPED_HCPTR, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::ELIs64(), gem5::ArmSystem::haveSecurity(), gem5::ArmSystem::haveVirtualization(), gem5::ArmISA::isSecure(), machInst, gem5::ArmISA::MISCREG_CPTR_EL3, gem5::ArmISA::MISCREG_HCPTR, gem5::StaticInst::mnemonic, gem5::NoFault, and gem5::ThreadContext::readMiscReg().

◆ checkForWFxTrap32()

Fault gem5::ArmISA::ArmStaticInst::checkForWFxTrap32	(	ThreadContext *	tc,
		ExceptionLevel	tgtEl,
		bool	isWfe
	)		const

protected

Check if WFE/WFI instruction execution in aarch32 should be trapped.

See aarch32/exceptions/traps/AArch32.checkForWFxTrap in the ARM ARM psueodcode library.

Definition at line 830 of file static_inst.cc.

References checkForWFxTrap64(), gem5::ArmISA::EC_TRAPPED_WFI_WFE, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::ELIs64(), gem5::ArmSystem::haveEL(), isWFxTrapping(), machInst, gem5::StaticInst::mnemonic, gem5::NoFault, and panic.

Referenced by trapWFx().

◆ checkForWFxTrap64()

Fault gem5::ArmISA::ArmStaticInst::checkForWFxTrap64	(	ThreadContext *	tc,
		ExceptionLevel	tgtEl,
		bool	isWfe
	)		const

protected

Check if WFE/WFI instruction execution in aarch64 should be trapped.

See aarch64/exceptions/traps/AArch64.checkForWFxTrap in the ARM ARM psueodcode library.

Definition at line 870 of file static_inst.cc.

References gem5::ArmISA::EC_TRAPPED_WFI_WFE, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmSystem::haveEL(), isWFxTrapping(), machInst, gem5::NoFault, and panic.

Referenced by checkForWFxTrap32().

◆ checkFPAdvSIMDEnabled64()

Fault gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPACR	cpacr
	)		const

protected

Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled in the ARM ARM psueodcode library.

Definition at line 714 of file static_inst.cc.

References advSIMDFPAccessTrap64(), checkFPAdvSIMDTrap64(), gem5::ArmISA::currEL(), gem5::ArmISA::el, gem5::ArmISA::EL0, and gem5::ArmISA::EL1.

Referenced by checkAdvSIMDOrFPEnabled32().

◆ checkFPAdvSIMDTrap64()

Fault gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64	(	ThreadContext *	tc,
		CPSR	cpsr
	)		const

protected

Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap in the ARM ARM psueodcode library.

Definition at line 675 of file static_inst.cc.

References advSIMDFPAccessTrap64(), gem5::ArmISA::currEL(), gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::EL3, gem5::ArmSystem::haveSecurity(), gem5::ArmISA::HaveVirtHostExt(), gem5::ArmISA::MISCREG_CPTR_EL2, gem5::ArmISA::MISCREG_CPTR_EL3, gem5::ArmISA::MISCREG_HCR_EL2, gem5::NoFault, and gem5::ThreadContext::readMiscReg().

Referenced by checkAdvSIMDOrFPEnabled32(), and checkFPAdvSIMDEnabled64().

◆ checkSETENDEnabled()

Fault gem5::ArmISA::ArmStaticInst::checkSETENDEnabled	(	ThreadContext *	tc,
		CPSR	cpsr
	)		const

protected

Check if SETEND instruction execution in aarch32 should be trapped.

See aarch32/exceptions/traps/AArch32.CheckSETENDEnabled in the ARM ARM pseudocode library.

Definition at line 928 of file static_inst.cc.

References gem5::ArmISA::currEL(), gem5::ArmISA::EL2, gem5::ArmISA::isSecure(), gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_SCTLR, gem5::NoFault, gem5::ThreadContext::readMiscRegNoEffect(), gem5::ArmISA::sed, gem5::ArmISA::snsBankedIndex(), and undefinedFault32().

◆ checkSveEnabled()

Fault gem5::ArmISA::ArmStaticInst::checkSveEnabled	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPACR	cpacr
	)		const

protected

Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

Definition at line 1016 of file static_inst.cc.

References advSIMDFPAccessTrap64(), gem5::ArmISA::el, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::EL3, gem5::ArmISA::ELIsInHost(), gem5::ArmSystem::haveSecurity(), gem5::ArmISA::HaveVirtHostExt(), gem5::ArmISA::MISCREG_CPTR_EL2, gem5::ArmISA::MISCREG_CPTR_EL3, gem5::ArmISA::MISCREG_HCR_EL2, gem5::NoFault, gem5::ThreadContext::readMiscReg(), and sveAccessTrap().

◆ cpsrWriteByInstr()

static uint32_t gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr	(	CPSR	cpsr,
		uint32_t	val,
		SCR	scr,
		NSACR	nsacr,
		uint8_t	byteMask,
		bool	affectState,
		bool	nmfi,
		ThreadContext *	tc
	)

inlinestaticprotected

Definition at line 226 of file static_inst.hh.

References activateBreakpoint(), gem5::ArmISA::badMode(), gem5::bits(), gem5::ArmSystem::haveVirtualization(), gem5::ArmISA::isSecure(), gem5::ArmISA::mask, gem5::ArmISA::MODE_FIQ, gem5::ArmISA::MODE_HYP, gem5::ArmISA::MODE_MON, gem5::ArmISA::MODE_USER, gem5::ArmISA::nmfi, gem5::X86ISA::val, and warn_once.

◆ cSwap() [1/2]

template<class T >

static T gem5::ArmISA::ArmStaticInst::cSwap	(	T	val,
		bool	big
	)

inlinestaticprotected

Definition at line 339 of file static_inst.hh.

References gem5::letobe(), and gem5::X86ISA::val.

◆ cSwap() [2/2]

template<class T , class E >

static T gem5::ArmISA::ArmStaticInst::cSwap	(	T	val,
		bool	big
	)

inlinestaticprotected

Definition at line 350 of file static_inst.hh.

References gem5::RefCounted::count, gem5::X86ISA::E, gem5::htole(), gem5::ArmISA::i, gem5::letobe(), gem5::letoh(), and gem5::X86ISA::val.

◆ disabledFault()

Fault gem5::ArmISA::ArmStaticInst::disabledFault ( ) const

inlineprotected

Definition at line 391 of file static_inst.hh.

References machInst, and gem5::StaticInst::mnemonic.

Referenced by checkAdvSIMDOrFPEnabled32().

◆ encoding()

MachInst gem5::ArmISA::ArmStaticInst::encoding ( ) const

inline

Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and contains some instruction metadata, which means it differs from the real opcode.

Definition at line 554 of file static_inst.hh.

References instSize(), machInst, and gem5::ArmISA::mask.

◆ extendReg64()

int64_t gem5::ArmISA::ArmStaticInst::extendReg64	(	uint64_t	base,
		ArmExtendType	type,
		uint64_t	shiftAmt,
		uint8_t	width
	)		const

protected

Definition at line 134 of file static_inst.cc.

References gem5::X86ISA::base, gem5::bits(), gem5::ArmISA::len, gem5::ArmISA::mask, gem5::ArmISA::SXTB, gem5::ArmISA::SXTH, gem5::ArmISA::SXTW, gem5::ArmISA::SXTX, gem5::X86ISA::type, gem5::ArmISA::UXTB, gem5::ArmISA::UXTH, gem5::ArmISA::UXTW, gem5::ArmISA::UXTX, and gem5::ArmISA::width.

◆ generalExceptionsToAArch64()

bool gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64	(	ThreadContext *	tc,
		ExceptionLevel	pstateEL
	)		const

protected

Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2 is using AArch64.

See aarch32/exceptions/exceptions/AArch32.GeneralExceptionsToAArch64 in the ARM ARM pseudocode library.

Definition at line 1206 of file static_inst.cc.

References gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::ELIs32(), gem5::ArmSystem::haveEL(), gem5::ArmISA::isSecure(), gem5::ArmISA::MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by undefinedFault32().

◆ generateDisassembly()

std::string gem5::ArmISA::ArmStaticInst::generateDisassembly	(	Addr	pc,
		const loader::SymbolTable *	symtab
	)		const

overrideprotectedvirtual

Internal function to generate disassembly string.

Implements gem5::StaticInst.

Definition at line 626 of file static_inst.cc.

References printMnemonic(), and gem5::ArmISA::ss.

◆ getCurSveVecLen()

template<typename T >

static unsigned gem5::ArmISA::ArmStaticInst::getCurSveVecLen ( ThreadContext * tc )

inlinestatic

Definition at line 575 of file static_inst.hh.

References getCurSveVecLenInBits().

◆ getCurSveVecLenInBits()

unsigned gem5::ArmISA::ArmStaticInst::getCurSveVecLenInBits ( ThreadContext * tc )

static

Definition at line 1219 of file static_inst.cc.

References gem5::ArmISA::ISA::getCurSveVecLenInBits(), and gem5::ThreadContext::getIsaPtr().

Referenced by getCurSveVecLen(), getCurSveVecLenInQWords(), gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updatePred(), and gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateVec().

◆ getCurSveVecLenInQWords()

static unsigned gem5::ArmISA::ArmStaticInst::getCurSveVecLenInQWords ( ThreadContext * tc )

inlinestatic

Definition at line 568 of file static_inst.hh.

References getCurSveVecLenInBits().

◆ getEMI()

uint64_t gem5::ArmISA::ArmStaticInst::getEMI ( ) const

inlineoverrideprotectedvirtual

Reimplemented from gem5::StaticInst.

Definition at line 205 of file static_inst.hh.

References machInst.

◆ getIntWidth()

uint8_t gem5::ArmISA::ArmStaticInst::getIntWidth ( ) const

inline

Definition at line 535 of file static_inst.hh.

References intWidth.

◆ getPSTATEFromPSR()

CPSR gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR	(	ThreadContext *	tc,
		CPSR	cpsr,
		CPSR	spsr
	)		const

protected

Get the new PSTATE from a SPSR register in preparation for an exception return.

See shared/functions/system/SetPSTATEFromPSR in the ARM ARM pseudocode library.

Definition at line 1148 of file static_inst.cc.

References gem5::ArmISA::currEL(), gem5::ArmISA::getRestoredITBits(), gem5::ArmISA::ISA::getSelfDebug(), gem5::ArmISA::illegalExceptionReturn(), gem5::ArmISA::sd, gem5::ArmISA::ss, and gem5::ArmISA::unknownMode32().

◆ instSize()

ssize_t gem5::ArmISA::ArmStaticInst::instSize ( ) const

inline

Returns the byte size of current instruction.

Definition at line 542 of file static_inst.hh.

References machInst.

Referenced by encoding().

◆ isWFxTrapping()

bool gem5::ArmISA::ArmStaticInst::isWFxTrapping	(	ThreadContext *	tc,
		ExceptionLevel	targetEL,
		bool	isWfe
	)		const

inlineprotected

Definition at line 803 of file static_inst.cc.

References gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR_EL1, and gem5::ThreadContext::readMiscReg().

Referenced by checkForWFxTrap32(), and checkForWFxTrap64().

◆ printCCReg()

void gem5::ArmISA::ArmStaticInst::printCCReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 364 of file static_inst.cc.

References gem5::ccprintf(), gem5::ArmISA::ccRegName, and gem5::X86ISA::os.

◆ printCondition()

void gem5::ArmISA::ArmStaticInst::printCondition	(	std::ostream &	os,
		unsigned	code,
		bool	noImplicit = `false`
	)		const

protected

◆ printDataInst() [1/2]

void gem5::ArmISA::ArmStaticInst::printDataInst	(	std::ostream &	os,
		bool	withImm
	)		const

protected

Referenced by gem5::ArmISA::DataXImmOp::generateDisassembly(), gem5::ArmISA::DataXSRegOp::generateDisassembly(), gem5::ArmISA::DataXERegOp::generateDisassembly(), gem5::ArmISA::PredImmOp::generateDisassembly(), gem5::ArmISA::PredIntOp::generateDisassembly(), gem5::ArmISA::DataImmOp::generateDisassembly(), gem5::ArmISA::DataRegOp::generateDisassembly(), and gem5::ArmISA::DataRegRegOp::generateDisassembly().

◆ printDataInst() [2/2]

void gem5::ArmISA::ArmStaticInst::printDataInst	(	std::ostream &	os,
		bool	withImm,
		bool	immShift,
		bool	s,
		IntRegIndex	rd,
		IntRegIndex	rn,
		IntRegIndex	rm,
		IntRegIndex	rs,
		uint32_t	shiftAmt,
		ArmShiftType	type,
		uint64_t	imm
	)		const

protected

Definition at line 594 of file static_inst.cc.

References gem5::ccprintf(), gem5::ArmISA::imm, gem5::X86ISA::os, printIntReg(), printMnemonic(), printShiftOperand(), gem5::ArmISA::rd, gem5::ArmISA::rm, gem5::ArmISA::rn, gem5::ArmISA::rs, gem5::ArmISA::s, and gem5::X86ISA::type.

◆ printExtendOperand()

void gem5::ArmISA::ArmStaticInst::printExtendOperand	(	bool	firstOperand,
		std::ostream &	os,
		IntRegIndex	rm,
		ArmExtendType	type,
		int64_t	shiftAmt
	)		const

protected

Definition at line 562 of file static_inst.cc.

References gem5::ccprintf(), gem5::X86ISA::os, printIntReg(), gem5::ArmISA::rm, gem5::ArmISA::SXTB, gem5::ArmISA::SXTH, gem5::ArmISA::SXTW, gem5::ArmISA::SXTX, gem5::X86ISA::type, gem5::ArmISA::UXTB, gem5::ArmISA::UXTH, gem5::ArmISA::UXTW, and gem5::ArmISA::UXTX.

Referenced by gem5::ArmISA::MemoryReg64::generateDisassembly(), and gem5::ArmISA::MicroIntRegXOp::generateDisassembly().

◆ printFloatReg()

void gem5::ArmISA::ArmStaticInst::printFloatReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 345 of file static_inst.cc.

References gem5::ccprintf(), and gem5::X86ISA::os.

◆ printIntReg()

void gem5::ArmISA::ArmStaticInst::printIntReg	(	std::ostream &	os,
		RegIndex	reg_idx,
		uint8_t	opWidth = `0`
	)		const

protected

Print a register name for disassembly given the unique dependence tag number (FP or int).

Definition at line 299 of file static_inst.cc.

References aarch64, gem5::ccprintf(), gem5::ArmISA::FramePointerReg, gem5::SparcISA::INTREG_UREG0, intWidth, gem5::X86ISA::os, gem5::ArmISA::PCReg, gem5::ArmISA::ReturnAddressReg, and gem5::ArmISA::StackPointerReg.

◆ printMemSymbol()

void gem5::ArmISA::ArmStaticInst::printMemSymbol	(	std::ostream &	os,
		const loader::SymbolTable *	symtab,
		const std::string &	prefix,
		const Addr	addr,
		const std::string &	suffix
	)		const

protected

Definition at line 480 of file static_inst.cc.

References gem5::X86ISA::addr, gem5::ccprintf(), gem5::loader::SymbolTable::end(), gem5::loader::SymbolTable::findNearest(), and gem5::X86ISA::os.

◆ printMiscReg()

void gem5::ArmISA::ArmStaticInst::printMiscReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 370 of file static_inst.cc.

References gem5::ccprintf(), gem5::ArmISA::miscRegName, gem5::ArmISA::NUM_MISCREGS, and gem5::X86ISA::os.

◆ printMnemonic()

void gem5::ArmISA::ArmStaticInst::printMnemonic	(	std::ostream &	os,
		const std::string &	suffix = `""`,
		bool	withPred = `true`,
		bool	withCond64 = `false`,
		ConditionCode	cond64 = `COND_UC`
	)		const

protected

Definition at line 377 of file static_inst.cc.

References aarch64, machInst, gem5::StaticInst::mnemonic, gem5::X86ISA::os, and printCondition().

◆ printPFflags()

void gem5::ArmISA::ArmStaticInst::printPFflags	(	std::ostream &	os,
		int	flag
	)		const

protected

Definition at line 334 of file static_inst.cc.

References gem5::ccprintf(), and gem5::X86ISA::os.

Referenced by gem5::ArmISA::Memory64::startDisassembly().

◆ printShiftOperand()

void gem5::ArmISA::ArmStaticInst::printShiftOperand	(	std::ostream &	os,
		IntRegIndex	rm,
		bool	immShift,
		uint32_t	shiftAmt,
		IntRegIndex	rs,
		ArmShiftType	type
	)		const

protected

Definition at line 498 of file static_inst.cc.

References gem5::X86ISA::os, panic, printIntReg(), gem5::ArmISA::rm, gem5::ArmISA::rs, and gem5::X86ISA::type.

Referenced by printDataInst().

◆ printTarget()

void gem5::ArmISA::ArmStaticInst::printTarget	(	std::ostream &	os,
		Addr	target,
		const loader::SymbolTable *	symtab
	)		const

protected

Definition at line 398 of file static_inst.cc.

References gem5::ccprintf(), gem5::loader::SymbolTable::end(), gem5::loader::SymbolTable::findNearest(), and gem5::X86ISA::os.

Referenced by gem5::ArmISA::BranchImm::generateDisassembly(), gem5::ArmISA::BranchImm64::generateDisassembly(), gem5::ArmISA::BranchImmCond64::generateDisassembly(), gem5::ArmISA::BranchImmReg64::generateDisassembly(), and gem5::ArmISA::BranchImmImmReg64::generateDisassembly().

◆ printVecPredReg()

void gem5::ArmISA::ArmStaticInst::printVecPredReg	(	std::ostream &	os,
		RegIndex	reg_idx
	)		const

protected

Definition at line 358 of file static_inst.cc.

References gem5::ccprintf(), and gem5::X86ISA::os.

◆ printVecReg()

void gem5::ArmISA::ArmStaticInst::printVecReg	(	std::ostream &	os,
		RegIndex	reg_idx,
		bool	isSveVecReg = `false`
	)		const

protected

Definition at line 351 of file static_inst.cc.

References gem5::ccprintf(), and gem5::X86ISA::os.

◆ readPC()

static Addr gem5::ArmISA::ArmStaticInst::readPC ( ExecContext * xc )

inlinestaticprotected

Definition at line 324 of file static_inst.hh.

References gem5::ExecContext::pcState().

Referenced by softwareBreakpoint32().

◆ satInt()

static bool gem5::ArmISA::ArmStaticInst::satInt	(	int32_t &	res,
		int64_t	op,
		int	width
	)

inlinestaticprotected

Definition at line 102 of file static_inst.hh.

References gem5::X86ISA::op, and gem5::ArmISA::width.

◆ saturateOp()

template<int width>

static bool gem5::ArmISA::ArmStaticInst::saturateOp	(	int32_t &	res,
		int64_t	op1,
		int64_t	op2,
		bool	sub = `false`
	)

inlinestaticprotected

Definition at line 86 of file static_inst.hh.

References gem5::bits(), and gem5::ArmISA::width.

◆ setAIWNextPC()

static void gem5::ArmISA::ArmStaticInst::setAIWNextPC	(	ExecContext *	xc,
		Addr	val
	)

inlinestaticprotected

Definition at line 383 of file static_inst.hh.

References gem5::MipsISA::pc, gem5::ExecContext::pcState(), and gem5::X86ISA::val.

◆ setIWNextPC()

static void gem5::ArmISA::ArmStaticInst::setIWNextPC	(	ExecContext *	xc,
		Addr	val
	)

inlinestaticprotected

Definition at line 373 of file static_inst.hh.

References gem5::MipsISA::pc, gem5::ExecContext::pcState(), and gem5::X86ISA::val.

◆ setNextPC()

static void gem5::ArmISA::ArmStaticInst::setNextPC	(	ExecContext *	xc,
		Addr	val
	)

inlinestaticprotected

Definition at line 330 of file static_inst.hh.

References gem5::MipsISA::pc, gem5::ExecContext::pcState(), and gem5::X86ISA::val.

◆ shift_carry_imm()

bool gem5::ArmISA::ArmStaticInst::shift_carry_imm	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 220 of file static_inst.cc.

References gem5::X86ISA::base, gem5::ccprintf(), gem5::X86ISA::exit, and gem5::X86ISA::type.

◆ shift_carry_rs()

bool gem5::ArmISA::ArmStaticInst::shift_carry_rs	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 260 of file static_inst.cc.

References gem5::X86ISA::base, gem5::ccprintf(), gem5::X86ISA::exit, and gem5::X86ISA::type.

◆ shift_rm_imm()

int32_t gem5::ArmISA::ArmStaticInst::shift_rm_imm	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 60 of file static_inst.cc.

References gem5::X86ISA::base, gem5::ccprintf(), gem5::X86ISA::exit, and gem5::X86ISA::type.

◆ shift_rm_rs()

int32_t gem5::ArmISA::ArmStaticInst::shift_rm_rs	(	uint32_t	base,
		uint32_t	shamt,
		uint32_t	type,
		uint32_t	cfval
	)		const

protected

Definition at line 180 of file static_inst.cc.

References gem5::X86ISA::base, gem5::ccprintf(), gem5::X86ISA::exit, and gem5::X86ISA::type.

◆ shiftReg64()

int64_t gem5::ArmISA::ArmStaticInst::shiftReg64	(	uint64_t	base,
		uint64_t	shiftAmt,
		ArmShiftType	type,
		uint8_t	width
	)		const

protected

Definition at line 95 of file static_inst.cc.

References gem5::X86ISA::base, gem5::bits(), gem5::ccprintf(), gem5::X86ISA::exit, intWidth, gem5::ArmISA::mask, gem5::X86ISA::type, and gem5::ArmISA::width.

◆ softwareBreakpoint32()

Fault gem5::ArmISA::ArmStaticInst::softwareBreakpoint32	(	ExecContext *	xc,
		uint16_t	imm
	)		const

protected

Trigger a Software Breakpoint.

See aarch32/exceptions/debug/AArch32.SoftwareBreakpoint in the ARM ARM psueodcode library.

Definition at line 635 of file static_inst.cc.

References gem5::ArmISA::ArmFault::BRKPOINT, gem5::ArmISA::ArmFault::DebugEvent, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::ELIs32(), gem5::ArmISA::imm, machInst, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_MDCR_EL2, gem5::ThreadContext::readMiscReg(), readPC(), gem5::ExecContext::tcBase(), and gem5::ArmISA::ArmFault::UnknownTran.

◆ spsrWriteByInstr()

static uint32_t gem5::ArmISA::ArmStaticInst::spsrWriteByInstr	(	uint32_t	spsr,
		uint32_t	val,
		uint8_t	byteMask,
		bool	affectState
	)

inlinestaticprotected

Definition at line 306 of file static_inst.hh.

References gem5::bits(), gem5::ArmISA::mask, and gem5::X86ISA::val.

◆ sveAccessTrap()

Fault gem5::ArmISA::ArmStaticInst::sveAccessTrap ( ExceptionLevel el ) const

protected

Trap an access to SVE registers due to access control bits.

Parameters

el	Target EL for the trap.

Definition at line 999 of file static_inst.cc.

References gem5::ArmISA::EC_TRAPPED_SVE, gem5::ArmISA::el, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, machInst, and panic.

Referenced by checkSveEnabled().

◆ trapWFx()

Fault gem5::ArmISA::ArmStaticInst::trapWFx	(	ThreadContext *	tc,
		CPSR	cpsr,
		SCR	scr,
		bool	isWfe
	)		const

protected

WFE/WFI trapping helper function.

Definition at line 902 of file static_inst.cc.

References checkForWFxTrap32(), gem5::ArmISA::currEL(), gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::EL3, gem5::ArmSystem::haveEL(), and gem5::NoFault.

◆ undefinedFault32()

Fault gem5::ArmISA::ArmStaticInst::undefinedFault32	(	ThreadContext *	tc,
		ExceptionLevel	el
	)		const

protected

UNDEFINED behaviour in AArch32.

See aarch32/exceptions/traps/AArch32.UndefinedFault in the ARM ARM pseudocode library.

Definition at line 960 of file static_inst.cc.

References gem5::ArmISA::EC_UNKNOWN, generalExceptionsToAArch64(), machInst, gem5::StaticInst::mnemonic, and undefinedFault64().

Referenced by checkSETENDEnabled().

◆ undefinedFault64()

Fault gem5::ArmISA::ArmStaticInst::undefinedFault64	(	ThreadContext *	tc,
		ExceptionLevel	el
	)		const

protected

UNDEFINED behaviour in AArch64.

See aarch64/exceptions/traps/AArch64.UndefinedFault in the ARM ARM pseudocode library.

Definition at line 979 of file static_inst.cc.

References gem5::ArmISA::EC_UNKNOWN, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, machInst, gem5::NoFault, and panic.

Referenced by undefinedFault32().

◆ uSatInt()

static bool gem5::ArmISA::ArmStaticInst::uSatInt	(	int32_t &	res,
		int64_t	op,
		int	width
	)

inlinestaticprotected

Definition at line 135 of file static_inst.hh.

References gem5::X86ISA::op, and gem5::ArmISA::width.

◆ uSaturateOp()

template<int width>

static bool gem5::ArmISA::ArmStaticInst::uSaturateOp	(	uint32_t &	res,
		int64_t	op1,
		int64_t	op2,
		bool	sub = `false`
	)

inlinestaticprotected

Definition at line 119 of file static_inst.hh.

References gem5::ArmISA::width.

Member Data Documentation

◆ aarch64

bool gem5::ArmISA::ArmStaticInst::aarch64

protected

Definition at line 66 of file static_inst.hh.

Referenced by ArmStaticInst(), printIntReg(), and printMnemonic().

◆ intWidth

uint8_t gem5::ArmISA::ArmStaticInst::intWidth

protected

Definition at line 67 of file static_inst.hh.

Referenced by ArmStaticInst(), getIntWidth(), printIntReg(), and shiftReg64().

◆ machInst

ExtMachInst gem5::ArmISA::ArmStaticInst::machInst

protected

Definition at line 149 of file static_inst.hh.

Referenced by advSIMDFPAccessTrap64(), ArmStaticInst(), asBytes(), gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp(), gem5::ArmISA::BigFpMemLitOp::BigFpMemLitOp(), gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp(), gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::ArmISA::BranchImmCond::BranchImmCond(), gem5::ArmISA::BranchRegCond::BranchRegCond(), checkAdvSIMDOrFPEnabled32(), checkForWFxTrap32(), checkForWFxTrap64(), disabledFault(), encoding(), gem5::DecoderFaultInst::execute(), gem5::FailUnimplemented::execute(), gem5::DebugStep::execute(), gem5::McrMrcMiscInst::execute(), gem5::McrMrcImplDefined::execute(), gem5::ArmISA::PredImmOp::generateDisassembly(), gem5::ArmISA::PredIntOp::generateDisassembly(), getEMI(), instSize(), gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::ArmISA::PredOp::PredOp(), printMnemonic(), softwareBreakpoint32(), sveAccessTrap(), gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS(), undefinedFault32(), undefinedFault64(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

The documentation for this class was generated from the following files:

arch/arm/insts/static_inst.hh
arch/arm/insts/static_inst.cc

Public Member Functions

Static Public Member Functions

Protected Member Functions

Static Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ArmStaticInst()

Member Function Documentation

◆ activateBreakpoint()

◆ advancePC()

◆ advSIMDFPAccessTrap64()

◆ annotateFault()

◆ asBytes()

◆ buildRetPC()

◆ checkAdvSIMDOrFPEnabled32()

◆ checkForWFxTrap32()

◆ checkForWFxTrap64()

◆ checkFPAdvSIMDEnabled64()

◆ checkFPAdvSIMDTrap64()

◆ checkSETENDEnabled()

◆ checkSveEnabled()

◆ cpsrWriteByInstr()

◆ cSwap() [1/2]

◆ cSwap() [2/2]

◆ disabledFault()

◆ encoding()

◆ extendReg64()

◆ generalExceptionsToAArch64()

◆ generateDisassembly()

◆ getCurSveVecLen()

◆ getCurSveVecLenInBits()

◆ getCurSveVecLenInQWords()

◆ getEMI()

◆ getIntWidth()

◆ getPSTATEFromPSR()

◆ instSize()

◆ isWFxTrapping()

◆ printCCReg()

◆ printCondition()

◆ printDataInst() [1/2]

◆ printDataInst() [2/2]

◆ printExtendOperand()

◆ printFloatReg()

◆ printIntReg()

◆ printMemSymbol()

◆ printMiscReg()

◆ printMnemonic()

◆ printPFflags()

◆ printShiftOperand()

◆ printTarget()

◆ printVecPredReg()

◆ printVecReg()

◆ readPC()

◆ satInt()

◆ saturateOp()

◆ setAIWNextPC()

◆ setIWNextPC()

◆ setNextPC()

◆ shift_carry_imm()

◆ shift_carry_rs()

◆ shift_rm_imm()

◆ shift_rm_rs()

◆ shiftReg64()

◆ softwareBreakpoint32()

◆ spsrWriteByInstr()

◆ sveAccessTrap()

◆ trapWFx()

◆ undefinedFault32()

◆ undefinedFault64()

◆ uSatInt()

◆ uSaturateOp()

Member Data Documentation

◆ aarch64

◆ intWidth

◆ machInst