gem5::ArmISA::TLB Class Reference

#include <tlb.hh>

Inheritance diagram for gem5::ArmISA::TLB:

Classes
struct	TlbStats

Public Types
enum	ArmFlags {   AlignmentMask = 0x7, AlignByte = 0x0, AlignHalfWord = 0x1, AlignWord = 0x2,   AlignDoubleWord = 0x3, AlignQuadWord = 0x4, AlignOctWord = 0x5, AllowUnaligned = 0x8,   UserMode = 0x10 }
enum	ArmTranslationType {   NormalTran = 0, S1CTran = 0x1, HypMode = 0x2, S1S2NsTran = 0x4,   S1E0Tran = 0x8, S1E1Tran = 0x10, S1E2Tran = 0x20, S1E3Tran = 0x40,   S12E0Tran = 0x80, S12E1Tran = 0x100 }
using	Params = ArmTLBParams
Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	TLB (const Params &p)
	TLB (const Params &p, int _size, TableWalker *_walker)
TlbEntry *	lookup (Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, BaseMMU::Mode mode)
	Lookup an entry in the TLB. More...
virtual	~TLB ()
void	takeOverFrom (BaseTLB *otlb) override
	Take over from an old tlb context. More...
void	setTestInterface (SimObject *ti)
void	setStage2Tlb (TLB *stage2_tlb)
void	setTableWalker (TableWalker *table_walker)
TableWalker *	getTableWalker ()
int	getsize () const
void	insert (Addr vaddr, TlbEntry &pte)
Fault	getTE (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType)
Fault	getResultTe (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, TlbEntry *mergeTe)
Fault	checkPermissions (TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode)
Fault	checkPermissions64 (TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode, ThreadContext *tc)
bool	checkPAN (ThreadContext *tc, uint8_t ap, const RequestPtr &req, BaseMMU::Mode mode, const bool is_priv)
void	flushAll () override
	Reset the entire TLB. More...
void	flush (const TLBIALL &tlbi_op)
	Reset the entire TLB. More...
void	flush (const TLBIALLEL &tlbi_op)
	Implementaton of AArch64 TLBI ALLE1(IS), ALLE2(IS), ALLE3(IS) instructions. More...
void	flush (const TLBIVMALL &tlbi_op)
	Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions. More...
void	flush (const TLBIALLN &tlbi_op)
	Remove all entries in the non secure world, depending on whether they were allocated in hyp mode or not. More...
void	flush (const TLBIMVA &tlbi_op)
	Remove any entries that match both a va and asn. More...
void	flush (const TLBIASID &tlbi_op)
	Remove any entries that match the asn. More...
void	flush (const TLBIMVAA &tlbi_op)
	Remove all entries that match the va regardless of asn. More...
Fault	trickBoxCheck (const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain)
Fault	walkTrickBoxCheck (Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level)
void	printTlb () const
void	demapPage (Addr vaddr, uint64_t asn) override
bool	translateFunctional (ThreadContext *tc, Addr vaddr, Addr &paddr)
	Do a functional lookup on the TLB (for debugging) and don't modify any internal state. More...
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType)
	Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state. More...
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
void	setAttr (uint64_t attr)
	Accessor functions for memory attributes for last accessed TLB entry. More...
uint64_t	getAttr () const
Fault	translateMmuOff (ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format)
Fault	translateMmuOn (ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod)
Fault	translateFs (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional=false)
Fault	translateSe (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing)
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType)
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
void	translateTiming (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType)
void	translateTiming (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
Fault	translateComplete (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType, bool callFromS2)
Fault	finalizePhysical (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
	Do post-translation physical address finalization. More...
void	drainResume () override
	Resume execution after a successful drain. More...
void	regProbePoints () override
	Register probe points for this object. More...
Port *	getTableWalkerPort () override
	Get the table walker port. More...
void	invalidateMiscReg ()
Fault	testTranslation (const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain)
Fault	testWalk (Addr pa, Addr size, Addr va, bool is_secure, BaseMMU::Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level)
Public Member Functions inherited from gem5::BaseTLB
void	memInvalidate ()
	Invalidate the contents of memory buffers. More...
Public Member Functions inherited from gem5::SimObject
const Params &	params () const
	SimObject (const Params &p)
virtual	~SimObject ()
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void	regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...
virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...
virtual void	startup ()
	startup() is the final initialization call before simulation. More...
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
void	setCurTick (Tick newVal)
	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...
virtual void	notifyFork ()
	Notify a child process of a fork. More...
Public Member Functions inherited from gem5::statistics::Group
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group. More...
virtual	~Group ()
virtual void	regStats ()
	Callback to set stat parameters. More...
virtual void	resetStats ()
	Callback to reset stats. More...
virtual void	preDumpStats ()
	Callback before stats are dumped. More...
void	addStat (statistics::Info *info)
	Register a stat with this group. More...
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block. More...
const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...
void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete
Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)
virtual	~Named ()=default
virtual std::string	name () const

Static Public Member Functions
static ExceptionLevel	tranTypeEL (CPSR cpsr, ArmTranslationType type)
	Determine the EL to use for the purpose of a translation given a specific translation type. More...
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...
static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Protected Member Functions
void	updateMiscReg (ThreadContext *tc, ArmTranslationType tranType=NormalTran)
vmid_t	getVMID (ThreadContext *tc) const
	Returns the current VMID (information stored in the VTTBR_EL2 register) More...
Protected Member Functions inherited from gem5::BaseTLB
	BaseTLB (const Params &p)
Protected Member Functions inherited from gem5::Drainable
	Drainable ()
virtual	~Drainable ()
void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
TlbEntry *	table
int	size
bool	isStage2
bool	stage2Req
bool	stage2DescReq
uint64_t	_attr
bool	directToStage2
TableWalker *	tableWalker
TLB *	stage2Tlb
TlbTestInterface *	test
gem5::ArmISA::TLB::TlbStats	stats
probing::PMUUPtr	ppRefills
	PMU probe for TLB refills. More...
int	rangeMRU
CPSR	cpsr
bool	aarch64
ExceptionLevel	aarch64EL
SCTLR	sctlr
SCR	scr
bool	isPriv
bool	isSecure
bool	isHyp
TTBCR	ttbcr
uint16_t	asid
vmid_t	vmid
PRRR	prrr
NMRR	nmrr
HCR	hcr
uint32_t	dacr
bool	miscRegValid
ContextID	miscRegContext
ArmTranslationType	curTranType
bool	haveLPAE
bool	haveVirtualization
bool	haveLargeAsid64
uint8_t	physAddrRange
AddrRange	m5opRange
Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...
Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Member Functions
void	_flushMva (Addr mva, uint64_t asn, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el, bool in_host)
	Remove any entries that match both a va and asn. More...

Detailed Description

Definition at line 109 of file tlb.hh.

Member Typedef Documentation

Params

using gem5::ArmISA::TLB::Params = ArmTLBParams

Definition at line 208 of file tlb.hh.

Member Enumeration Documentation

ArmFlags

enum gem5::ArmISA::TLB::ArmFlags

Enumerator
AlignmentMask
AlignByte
AlignHalfWord
AlignWord
AlignDoubleWord
AlignQuadWord
AlignOctWord
AllowUnaligned
UserMode

Definition at line 112 of file tlb.hh.

ArmTranslationType

enum gem5::ArmISA::TLB::ArmTranslationType

Enumerator
NormalTran
S1CTran
HypMode
S1S2NsTran
S1E0Tran
S1E1Tran
S1E2Tran
S1E3Tran
S12E0Tran
S12E1Tran

Definition at line 128 of file tlb.hh.

Constructor & Destructor Documentation

TLB() [1/2]

gem5::TLB::TLB

(

const Params &

p

)

Definition at line 79 of file tlb.cc.

References gem5::FullSystem, gem5::ArmSystem::haveLargeAsid64(), haveLargeAsid64, gem5::ArmSystem::haveLPAE(), haveLPAE, gem5::ArmSystem::haveVirtualization(), haveVirtualization, m5opRange, gem5::MipsISA::p, gem5::ArmSystem::physAddrRange(), and physAddrRange.

TLB() [2/2]

gem5::ArmISA::TLB::TLB	(	const Params &	p,
		int	_size,
		TableWalker *	_walker
	)

~TLB()

gem5::TLB::~TLB ( )

virtual

Definition at line 106 of file tlb.cc.

References table.

Member Function Documentation

_flushMva()

void gem5::TLB::_flushMva ( Addr  mva, uint64_t  asn, bool  secure_lookup, bool  ignore_asn, ExceptionLevel  target_el, bool  in_host  )

private

Remove any entries that match both a va and asn.

Parameters

mva	virtual address to flush
asn	contextid/asn to flush on match
secure_lookup	if the operation affects the secure world
ignore_asn	if the flush should ignore the asn
in_host	if hcr.e2h == 1 and hcr.tge == 1 for VHE.

Definition at line 435 of file tlb.cc.

References DPRINTF, gem5::ArmISA::EL2, gem5::ArmISA::TLB::TlbStats::flushedEntries, lookup(), gem5::BaseMMU::Read, stats, gem5::ArmISA::te, and vmid.

Referenced by flush().

checkPAN()

bool gem5::TLB::checkPAN	(	ThreadContext *	tc,
		uint8_t	ap,
		const RequestPtr &	req,
		BaseMMU::Mode	mode,
		const bool	is_priv
	)

Definition at line 1000 of file tlb.cc.

References gem5::Request::CACHE_BLOCK_ZERO, gem5::BaseMMU::Execute, gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::mode, and gem5::ThreadContext::readMiscReg().

checkPermissions()

Fault gem5::TLB::checkPermissions	(	TlbEntry *	te,
		const RequestPtr &	req,
		BaseMMU::Mode	mode
	)

Definition at line 581 of file tlb.cc.

References gem5::ArmISA::ArmFault::AlignmentFault, gem5::ArmISA::ArmFault::DomainLL, DPRINTF, gem5::BaseMMU::Execute, gem5::ArmISA::isSecure(), gem5::ArmISA::ArmFault::LpaeTran, gem5::X86ISA::mask, gem5::ArmISA::mode, gem5::NoFault, panic, gem5::ArmISA::ArmFault::PermissionLL, gem5::ArmISA::ArmFault::PrefetchUncacheable, gem5::X86ISA::TLB::stats, gem5::ArmISA::te, gem5::MipsISA::vaddr, gem5::ArmISA::ArmFault::VmsaTran, and gem5::BaseMMU::Write.

Referenced by gem5::ArmISA::Stage2LookUp::getTe().

checkPermissions64()

Fault gem5::TLB::checkPermissions64	(	TlbEntry *	te,
		const RequestPtr &	req,
		BaseMMU::Mode	mode,
		ThreadContext *	tc
	)

Definition at line 759 of file tlb.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::ArmFault::AlignmentFault, DPRINTF, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::BaseMMU::Execute, GEM5_FALLTHROUGH, gem5::ArmSystem::haveEL(), gem5::ArmSystem::haveVirtualization(), gem5::ArmISA::isSecure(), gem5::ArmISA::ArmFault::LpaeTran, gem5::X86ISA::mask, gem5::ArmISA::mode, gem5::NoFault, gem5::RiscvISA::perm, gem5::ArmISA::ArmFault::PermissionLL, gem5::ArmISA::ArmFault::PrefetchUncacheable, gem5::ArmISA::purifyTaggedAddr(), gem5::X86ISA::r, gem5::X86ISA::TLB::stats, gem5::ArmISA::te, gem5::MipsISA::vaddr, gem5::X86ISA::w, gem5::BaseMMU::Write, gem5::ArmISA::wxn, and gem5::X86ISA::x.

Referenced by gem5::ArmISA::Stage2LookUp::getTe().

demapPage()

void gem5::TLB::demapPage ( Addr  vaddr, uint64_t  asn  )

inlineoverridevirtual

Implements gem5::BaseTLB.

Definition at line 311 of file tlb.hh.

References panic.

drainResume()

void gem5::TLB::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 458 of file tlb.cc.

References miscRegValid.

finalizePhysical()

Fault gem5::TLB::finalizePhysical ( const RequestPtr &  req, ThreadContext *  tc, BaseMMU::Mode  mode  ) const

overridevirtual

Do post-translation physical address finalization.

This method is used by some architectures that need post-translation massaging of physical addresses. For example, X86 uses this to remap physical addresses in the APIC range to a range of physical memory not normally available to real x86 implementations.

Parameters

req	Request to updated in-place.
tc	Thread context that created the request.
mode	Request type (read/write/execute).

Returns

A fault on failure, NoFault otherwise.

Implements gem5::BaseTLB.

Definition at line 137 of file tlb.cc.

References gem5::AddrRange::contains(), gem5::pseudo_inst::decodeAddrOffset(), gem5::ArmISA::inAArch64(), m5opRange, gem5::ArmISA::mode, gem5::NoFault, gem5::BaseMMU::Read, gem5::Packet::setLE(), and gem5::AddrRange::start().

flush() [1/7]

void gem5::TLB::flush

(

const TLBIALL &

tlbi_op

)

Reset the entire TLB.

Definition at line 292 of file tlb.cc.

References DPRINTF, gem5::ArmISA::TLBIALL::el2Enabled, gem5::ArmISA::TLB::TlbStats::flushedEntries, gem5::ArmISA::TLB::TlbStats::flushTlb, gem5::ArmISA::TLBIALL::inHost, gem5::ArmISA::TLBIOp::secureLookup, size, stats, table, gem5::ArmISA::TLBIOp::targetEL, gem5::ArmISA::te, vmid, and gem5::RiscvISA::x.

Referenced by gem5::ArmISA::MMU::dflush(), gem5::ArmISA::MMU::flushStage2(), and gem5::ArmISA::MMU::iflush().

flush() [2/7]

void gem5::TLB::flush

(

const TLBIALLEL &

tlbi_op

)

Implementaton of AArch64 TLBI ALLE1(IS), ALLE2(IS), ALLE3(IS) instructions.

Definition at line 316 of file tlb.cc.

References DPRINTF, gem5::ArmISA::TLB::TlbStats::flushedEntries, gem5::ArmISA::TLB::TlbStats::flushTlb, gem5::ArmISA::TLBIALLEL::inHost, gem5::ArmISA::TLBIOp::secureLookup, size, stats, table, gem5::ArmISA::TLBIOp::targetEL, gem5::ArmISA::te, and gem5::RiscvISA::x.

flush() [3/7]

void gem5::TLB::flush

(

const TLBIALLN &

tlbi_op

)

Remove all entries in the non secure world, depending on whether they were allocated in hyp mode or not.

Definition at line 363 of file tlb.cc.

References DPRINTF, gem5::ArmISA::EL2, gem5::ArmISA::TLB::TlbStats::flushedEntries, gem5::ArmISA::TLB::TlbStats::flushTlb, size, stats, table, gem5::ArmISA::TLBIOp::targetEL, gem5::ArmISA::te, and gem5::RiscvISA::x.

flush() [4/7]

void gem5::TLB::flush

(

const TLBIASID &

tlbi_op

)

Remove any entries that match the asn.

Definition at line 399 of file tlb.cc.

References gem5::ArmISA::TLBIASID::asid, DPRINTF, gem5::ArmISA::TLBIASID::el2Enabled, gem5::ArmISA::TLB::TlbStats::flushedEntries, gem5::ArmISA::TLB::TlbStats::flushTlbAsid, gem5::ArmISA::TLBIASID::inHost, gem5::ArmISA::TLBIOp::secureLookup, size, stats, table, gem5::ArmISA::TLBIOp::targetEL, gem5::ArmISA::te, vmid, and gem5::RiscvISA::x.

flush() [5/7]

void gem5::TLB::flush

(

const TLBIMVA &

tlbi_op

)

Remove any entries that match both a va and asn.

Definition at line 388 of file tlb.cc.

References _flushMva(), gem5::ArmISA::TLBIMVA::addr, gem5::ArmISA::TLBIMVA::asid, DPRINTF, gem5::ArmISA::TLB::TlbStats::flushTlbMvaAsid, gem5::ArmISA::TLBIMVA::inHost, gem5::ArmISA::TLBIOp::secureLookup, stats, and gem5::ArmISA::TLBIOp::targetEL.

flush() [6/7]

void gem5::TLB::flush

(

const TLBIMVAA &

tlbi_op

)

Remove all entries that match the va regardless of asn.

Definition at line 424 of file tlb.cc.

References _flushMva(), gem5::ArmISA::TLBIMVAA::addr, DPRINTF, gem5::ArmISA::TLB::TlbStats::flushTlbMva, gem5::ArmISA::TLBIMVAA::inHost, gem5::ArmISA::TLBIOp::secureLookup, stats, and gem5::ArmISA::TLBIOp::targetEL.

flush() [7/7]

void gem5::TLB::flush

(

const TLBIVMALL &

tlbi_op

)

Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.

Definition at line 339 of file tlb.cc.

References DPRINTF, gem5::ArmISA::TLBIVMALL::el2Enabled, gem5::ArmISA::TLB::TlbStats::flushedEntries, gem5::ArmISA::TLB::TlbStats::flushTlb, gem5::ArmISA::TLBIVMALL::inHost, gem5::ArmISA::TLBIOp::secureLookup, size, stats, table, gem5::ArmISA::TLBIOp::targetEL, gem5::ArmISA::te, vmid, and gem5::RiscvISA::x.

flushAll()

void gem5::TLB::flushAll ( )

overridevirtual

Reset the entire TLB.

Used for CPU switching to prevent stale translations after multiple switches

Implements gem5::BaseTLB.

Definition at line 274 of file tlb.cc.

References DPRINTF, gem5::ArmISA::TLB::TlbStats::flushedEntries, gem5::ArmISA::TLB::TlbStats::flushTlb, size, stats, table, gem5::ArmISA::te, and gem5::RiscvISA::x.

Referenced by gem5::ArmISA::MMU::flushAll().

getAttr()

uint64_t gem5::ArmISA::TLB::getAttr ( ) const

inline

Definition at line 349 of file tlb.hh.

References _attr.

Referenced by gem5::ArmISA::MMU::getAttr().

getResultTe()

Fault gem5::TLB::getResultTe	(	TlbEntry **	te,
		const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		BaseMMU::Translation *	translation,
		bool	timing,
		bool	functional,
		TlbEntry *	mergeTe
	)

Definition at line 1640 of file tlb.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::ArmFault::annotate(), DPRINTF, gem5::ArmISA::Stage2LookUp::getTe(), gem5::ArmISA::Stage2LookUp::isComplete(), gem5::ArmISA::isSecure(), gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::ArmFault::OVA, gem5::ArmISA::ArmFault::S1PTW, gem5::ArmISA::Stage2LookUp::setSelfDelete(), and gem5::ArmISA::te.

getsize()

int gem5::ArmISA::TLB::getsize ( ) const

inline

Definition at line 242 of file tlb.hh.

References size.

getTableWalker()

TableWalker* gem5::ArmISA::TLB::getTableWalker ( )

inline

Definition at line 240 of file tlb.hh.

References tableWalker.

getTableWalkerPort()

Port * gem5::TLB::getTableWalkerPort ( )

overridevirtual

Get the table walker port.

This is used for migrating port connections during a CPU takeOverFrom() call. For architectures that do not have a table walker, NULL is returned, hence the use of a pointer rather than a reference. For ARM this method will always return a valid port pointer.

Returns

A pointer to the walker request port

Reimplemented from gem5::BaseTLB.

Definition at line 1346 of file tlb.cc.

getTE()

Fault gem5::TLB::getTE	(	TlbEntry **	te,
		const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		BaseMMU::Translation *	translation,
		bool	timing,
		bool	functional,
		bool	is_secure,
		TLB::ArmTranslationType	tranType
	)

Definition at line 1586 of file tlb.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::asid, DPRINTF, gem5::ArmISA::EL1, gem5::BaseMMU::Execute, gem5::X86ISA::TLB::lookup(), gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::ArmFault::PrefetchTLBMiss, gem5::ArmISA::purifyTaggedAddr(), gem5::X86ISA::TLB::stats, gem5::ArmISA::te, and gem5::MipsISA::vaddr.

Referenced by gem5::ArmISA::Stage2LookUp::finish(), and gem5::ArmISA::Stage2LookUp::getTe().

getVMID()

vmid_t gem5::TLB::getVMID ( ThreadContext *  tc ) const

protected

Returns the current VMID (information stored in the VTTBR_EL2 register)

Definition at line 1352 of file tlb.cc.

References gem5::bits(), gem5::ArmISA::EL2, gem5::ArmISA::ELIs64(), gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_VTCR_EL2, gem5::ArmISA::MISCREG_VTTBR_EL2, panic, and gem5::ThreadContext::readMiscReg().

insert()

void gem5::TLB::insert	(	Addr	vaddr,
		TlbEntry &	pte
	)

Definition at line 230 of file tlb.cc.

References gem5::ArmISA::TlbEntry::ap, gem5::ArmISA::TlbEntry::asid, asid, gem5::ArmISA::TlbEntry::domain, DPRINTF, gem5::ArmISA::el, gem5::ArmISA::TlbEntry::global, gem5::ArmISA::i, gem5::ArmISA::TLB::TlbStats::inserts, gem5::ArmISA::TlbEntry::isHyp, isHyp, gem5::ArmISA::TlbEntry::N, gem5::ArmISA::TlbEntry::nonCacheable, gem5::ArmISA::TlbEntry::ns, gem5::ArmISA::ns, gem5::ArmISA::TlbEntry::nstid, gem5::MipsISA::pfn, gem5::ArmISA::TlbEntry::pfn, ppRefills, gem5::ArmISA::TlbEntry::size, size, stats, table, gem5::ArmISA::TlbEntry::valid, gem5::ArmISA::TlbEntry::vmid, vmid, gem5::ArmISA::TlbEntry::vpn, and gem5::ArmISA::TlbEntry::xn.

Referenced by gem5::ArmISA::TableWalker::insertTableEntry().

invalidateMiscReg()

void gem5::ArmISA::TLB::invalidateMiscReg ( )

inline

Definition at line 453 of file tlb.hh.

References miscRegValid.

Referenced by gem5::ArmISA::MMU::invalidateMiscReg().

lookup()

TlbEntry * gem5::TLB::lookup	(	Addr	vpn,
		uint16_t	asn,
		vmid_t	vmid,
		bool	hyp,
		bool	secure,
		bool	functional,
		bool	ignore_asn,
		ExceptionLevel	target_el,
		bool	in_host,
		BaseMMU::Mode	mode
	)

Lookup an entry in the TLB.

Parameters

vpn	virtual address
asn	context id/address space id to use
vmid	The virtual machine ID used for stage 2 translation
secure	if the lookup is secure
hyp	if the lookup is done from hyp mode
functional	if the lookup should modify state
ignore_asn	if on lookup asn should be ignored
target_el	selecting the translation regime
in_host	if we are in host (EL2&0 regime)
mode	to differentiate between read/writes/fetches.

Returns

pointer to TLB entry if it exists

Definition at line 166 of file tlb.cc.

References gem5::ArmISA::TlbEntry::ap, gem5::ArmISA::TlbEntry::asid, DPRINTF, gem5::ArmISA::TlbEntry::el, gem5::BaseMMU::Execute, gem5::ArmISA::TlbEntry::global, gem5::ArmISA::i, gem5::ArmISA::TLB::TlbStats::instHits, gem5::ArmISA::TLB::TlbStats::instMisses, gem5::ArmISA::mode, gem5::ArmISA::TlbEntry::ns, gem5::ArmISA::TlbEntry::nstid, gem5::ArmISA::TlbEntry::pAddr(), gem5::ArmISA::TlbEntry::pfn, rangeMRU, gem5::ArmISA::TLB::TlbStats::readHits, gem5::ArmISA::TLB::TlbStats::readMisses, gem5::ArmISA::TlbEntry::size, size, stats, table, gem5::ArmISA::va, vmid, gem5::BaseMMU::Write, gem5::ArmISA::TLB::TlbStats::writeHits, gem5::ArmISA::TLB::TlbStats::writeMisses, and gem5::RiscvISA::x.

Referenced by _flushMva(), gem5::ArmISA::TableWalker::processWalkWrapper(), and translateFunctional().

printTlb()

void gem5::TLB::printTlb

(

)

const

Definition at line 260 of file tlb.cc.

References DPRINTF, size, table, gem5::ArmISA::te, and gem5::RiscvISA::x.

regProbePoints()

void gem5::TLB::regProbePoints ( )

overridevirtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented from gem5::SimObject.

Definition at line 535 of file tlb.cc.

References gem5::SimObject::getProbeManager().

setAttr()

void gem5::ArmISA::TLB::setAttr ( uint64_t  attr )

inline

Accessor functions for memory attributes for last accessed TLB entry.

Definition at line 343 of file tlb.hh.

References _attr, and gem5::ArmISA::attr.

setStage2Tlb()

void gem5::ArmISA::TLB::setStage2Tlb ( TLB *  stage2_tlb )

inline

Definition at line 236 of file tlb.hh.

References stage2Tlb.

Referenced by gem5::ArmISA::MMU::init().

setTableWalker()

void gem5::TLB::setTableWalker

(

TableWalker *

table_walker

)

Definition at line 112 of file tlb.cc.

References gem5::ArmISA::TableWalker::setTlb(), and tableWalker.

Referenced by gem5::ArmISA::MMU::init().

setTestInterface()

void gem5::TLB::setTestInterface

(

SimObject *

ti

)

Definition at line 1713 of file tlb.cc.

References fatal_if, gem5::Named::name(), and gem5::X86ISA::ti.

takeOverFrom()

void gem5::TLB::takeOverFrom ( BaseTLB *  otlb )

overridevirtual

Take over from an old tlb context.

Implements gem5::BaseTLB.

Definition at line 466 of file tlb.cc.

References _attr, directToStage2, isStage2, panic, stage2DescReq, stage2Req, stage2Tlb, and takeOverFrom().

Referenced by takeOverFrom().

testTranslation()

Fault gem5::TLB::testTranslation	(	const RequestPtr &	req,
		BaseMMU::Mode	mode,
		TlbEntry::DomainType	domain
	)

Definition at line 1725 of file tlb.cc.

References gem5::ArmISA::domain, gem5::ArmISA::mode, and gem5::NoFault.

testWalk()

Fault gem5::TLB::testWalk	(	Addr	pa,
		Addr	size,
		Addr	va,
		bool	is_secure,
		BaseMMU::Mode	mode,
		TlbEntry::DomainType	domain,
		LookupLevel	lookup_level
	)

Definition at line 1737 of file tlb.cc.

References gem5::ArmISA::domain, gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::pa, gem5::X86ISA::TLB::size, and gem5::ArmISA::va.

Referenced by gem5::ArmISA::TableWalker::testWalk().

translateAtomic() [1/2]

Fault gem5::TLB::translateAtomic ( const RequestPtr &  req, ThreadContext *  tc, BaseMMU::Mode  mode  )

inlineoverridevirtual

Implements gem5::BaseTLB.

Definition at line 374 of file tlb.hh.

References gem5::ArmISA::mode, NormalTran, and translateAtomic().

translateAtomic() [2/2]

Fault gem5::TLB::translateAtomic	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		TLB::ArmTranslationType	tranType
	)

Definition at line 1256 of file tlb.cc.

References gem5::FullSystem, and gem5::ArmISA::mode.

Referenced by gem5::ArmISA::MMU::translateAtomic(), and translateAtomic().

translateComplete()

Fault gem5::TLB::translateComplete	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Translation *	translation,
		BaseMMU::Mode	mode,
		TLB::ArmTranslationType	tranType,
		bool	callFromS2
	)

Definition at line 1316 of file tlb.cc.

References DPRINTF, gem5::BaseMMU::Translation::finish(), gem5::FullSystem, gem5::BaseMMU::Translation::markDelayed(), gem5::ArmISA::mode, and gem5::NoFault.

Referenced by gem5::ArmISA::Stage2LookUp::finish().

translateFs()

Fault gem5::TLB::translateFs	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		BaseMMU::Translation *	translation,
		bool &	delay,
		bool	timing,
		TLB::ArmTranslationType	tranType,
		bool	functional = false
	)

Definition at line 1174 of file tlb.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::ArmFault::AlignmentFault, gem5::ArmISA::asid, DPRINTF, gem5::BaseMMU::Execute, gem5::ArmISA::ISA::getSelfDebug(), gem5::ArmISA::HaveVirtHostExt(), gem5::ArmISA::isSecure(), gem5::ArmISA::longDescFormatInUse(), gem5::ArmISA::ArmFault::LpaeTran, gem5::X86ISA::mask, gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::purifyTaggedAddr(), gem5::ArmISA::sd, gem5::X86ISA::TLB::stats, gem5::Request::STRICT_ORDER, gem5::Request::UNCACHEABLE, gem5::MipsISA::vaddr, gem5::X86ISA::vm, gem5::ArmISA::ArmFault::VmsaTran, and gem5::BaseMMU::Write.

translateFunctional() [1/3]

Fault gem5::TLB::translateFunctional ( const RequestPtr &  req, ThreadContext *  tc, BaseMMU::Mode  mode  )

inlineoverridevirtual

Reimplemented from gem5::BaseTLB.

Definition at line 334 of file tlb.hh.

References gem5::ArmISA::mode, NormalTran, and translateFunctional().

translateFunctional() [2/3]

Fault gem5::TLB::translateFunctional	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		TLB::ArmTranslationType	tranType
	)

Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state.

Definition at line 1277 of file tlb.cc.

References gem5::FullSystem, and gem5::ArmISA::mode.

translateFunctional() [3/3]

bool gem5::TLB::translateFunctional	(	ThreadContext *	tc,
		Addr	vaddr,
		Addr &	paddr
	)

Do a functional lookup on the TLB (for debugging) and don't modify any internal state.

Parameters

tc	thread context to get the context id from
vaddr	virtual address to translate
pa	returned physical address

Returns

if the translation was successful

Definition at line 119 of file tlb.cc.

References aarch64, aarch64EL, asid, directToStage2, gem5::ArmISA::e, gem5::ArmISA::EL1, isHyp, isSecure, lookup(), gem5::ArmISA::pa, gem5::BaseMMU::Read, stage2Tlb, translateFunctional(), updateMiscReg(), gem5::ArmISA::va, and vmid.

Referenced by gem5::ArmISA::MMU::translateFunctional(), and translateFunctional().

translateMmuOff()

Fault gem5::TLB::translateMmuOff	(	ThreadContext *	tc,
		const RequestPtr &	req,
		BaseMMU::Mode	mode,
		TLB::ArmTranslationType	tranType,
		Addr	vaddr,
		bool	long_desc_format
	)

Definition at line 1028 of file tlb.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::ArmFault::AddressSizeLL, gem5::ArmISA::TlbEntry::attributes, gem5::bits(), gem5::ArmISA::computeAddrTop(), gem5::ArmISA::currEL(), gem5::ArmISA::dc, DPRINTF, gem5::BaseMMU::Execute, gem5::ArmISA::f, gem5::ArmISA::HaveVirtHostExt(), gem5::ArmISA::TlbEntry::innerAttrs, gem5::ArmISA::isSecure(), gem5::ArmISA::ArmFault::LpaeTran, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::mode, gem5::ArmISA::TlbEntry::mtype, gem5::ArmISA::TlbEntry::ns, gem5::ArmISA::TlbEntry::outerAttrs, gem5::ArmISA::TlbEntry::outerShareable, gem5::ThreadContext::readMiscReg(), gem5::Request::SECURE, gem5::ArmISA::TlbEntry::setAttributes(), gem5::ArmISA::TlbEntry::shareable, gem5::Request::STRICT_ORDER, gem5::Request::UNCACHEABLE, gem5::MipsISA::vaddr, and gem5::BaseMMU::Write.

translateMmuOn()

Fault gem5::TLB::translateMmuOn	(	ThreadContext *	tc,
		const RequestPtr &	req,
		BaseMMU::Mode	mode,
		BaseMMU::Translation *	translation,
		bool &	delay,
		bool	timing,
		bool	functional,
		Addr	vaddr,
		ArmFault::TranMethod	tranMethod
	)

Definition at line 1101 of file tlb.cc.

References gem5::ArmISA::ArmFault::AlignmentFault, DPRINTF, gem5::BaseMMU::Execute, gem5::X86ISA::TLB::finalizePhysical(), gem5::ArmISA::isSecure(), gem5::X86ISA::mask, gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::pa, gem5::Request::SECURE, gem5::X86ISA::TLB::stats, gem5::Request::STRICT_ORDER, gem5::ArmISA::te, gem5::Request::UNCACHEABLE, gem5::MipsISA::vaddr, and gem5::BaseMMU::Write.

translateSe()

Fault gem5::TLB::translateSe	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		BaseMMU::Translation *	translation,
		bool &	delay,
		bool	timing
	)

Definition at line 541 of file tlb.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::ArmFault::AlignmentFault, gem5::BaseMMU::Execute, gem5::X86ISA::TLB::finalizePhysical(), gem5::ThreadContext::getProcessPtr(), gem5::X86ISA::mask, gem5::ArmISA::mode, gem5::X86ISA::p, gem5::ArmISA::purifyTaggedAddr(), gem5::MipsISA::vaddr, gem5::ArmISA::ArmFault::VmsaTran, and gem5::BaseMMU::Write.

translateTiming() [1/2]

void gem5::TLB::translateTiming ( const RequestPtr &  req, ThreadContext *  tc, BaseMMU::Translation *  translation, BaseMMU::Mode  mode  )

inlineoverridevirtual

Implements gem5::BaseTLB.

Definition at line 384 of file tlb.hh.

References gem5::ArmISA::mode, NormalTran, and translateTiming().

translateTiming() [2/2]

void gem5::TLB::translateTiming	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Translation *	translation,
		BaseMMU::Mode	mode,
		TLB::ArmTranslationType	tranType
	)

Definition at line 1298 of file tlb.cc.

References gem5::ArmISA::mode.

Referenced by gem5::ArmISA::TableWalker::doL1DescriptorWrapper(), gem5::ArmISA::TableWalker::doL2DescriptorWrapper(), gem5::ArmISA::TableWalker::doLongDescriptorWrapper(), gem5::ArmISA::TableWalker::processWalkWrapper(), gem5::ArmISA::MMU::translateTiming(), and translateTiming().

tranTypeEL()

ExceptionLevel gem5::TLB::tranTypeEL ( CPSR  cpsr, ArmTranslationType  type  )

static

Determine the EL to use for the purpose of a translation given a specific translation type.

If the translation type doesn't specify an EL, we use the current EL.

Definition at line 1557 of file tlb.cc.

References gem5::ArmISA::currEL(), gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, panic, and gem5::X86ISA::type.

Referenced by gem5::ArmISA::TableWalker::walk().

trickBoxCheck()

Fault gem5::ArmISA::TLB::trickBoxCheck	(	const RequestPtr &	req,
		BaseMMU::Mode	mode,
		TlbEntry::DomainType	domain
	)

updateMiscReg()

void gem5::TLB::updateMiscReg ( ThreadContext *  tc, ArmTranslationType  tranType = NormalTran  )

protected

Definition at line 1381 of file tlb.cc.

References gem5::ArmISA::aarch64, gem5::ArmISA::asid, gem5::bits(), gem5::ThreadContext::contextId(), DPRINTF, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::ELIs64(), gem5::ArmISA::HaveVirtHostExt(), gem5::ArmISA::isSecure(), gem5::ArmISA::IsSecureEL2Enabled(), gem5::ArmISA::longDescFormatInUse(), gem5::ArmISA::MISCREG_CONTEXTIDR, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_DACR, gem5::ArmISA::MISCREG_HCR, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_NMRR, gem5::ArmISA::MISCREG_PRRR, gem5::ArmISA::MISCREG_SCR, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR, gem5::ArmISA::MISCREG_SCTLR_EL1, gem5::ArmISA::MISCREG_SCTLR_EL2, gem5::ArmISA::MISCREG_SCTLR_EL3, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::MISCREG_TCR_EL2, gem5::ArmISA::MISCREG_TCR_EL3, gem5::ArmISA::MISCREG_TTBCR, gem5::ArmISA::MISCREG_TTBR0, gem5::ArmISA::MISCREG_TTBR0_EL1, gem5::ArmISA::MISCREG_TTBR0_EL2, gem5::ArmISA::MISCREG_TTBR1, gem5::ArmISA::MISCREG_TTBR1_EL1, gem5::ArmISA::MISCREG_TTBR1_EL2, gem5::ArmISA::MISCREG_VTTBR, gem5::ArmISA::MODE_HYP, gem5::ArmISA::MODE_USER, gem5::ThreadContext::readMiscReg(), gem5::ArmISA::snsBankedIndex(), and gem5::X86ISA::vm.

Referenced by translateFunctional().

walkTrickBoxCheck()

Fault gem5::ArmISA::TLB::walkTrickBoxCheck	(	Addr	pa,
		bool	is_secure,
		Addr	va,
		Addr	sz,
		bool	is_exec,
		bool	is_write,
		TlbEntry::DomainType	domain,
		LookupLevel	lookup_level
	)

Member Data Documentation

_attr

uint64_t gem5::ArmISA::TLB::_attr

protected

Definition at line 164 of file tlb.hh.

Referenced by getAttr(), setAttr(), and takeOverFrom().

aarch64

bool gem5::ArmISA::TLB::aarch64

protected

Definition at line 419 of file tlb.hh.

Referenced by translateFunctional().

aarch64EL

ExceptionLevel gem5::ArmISA::TLB::aarch64EL

protected

Definition at line 420 of file tlb.hh.

Referenced by translateFunctional().

asid

uint16_t gem5::ArmISA::TLB::asid

protected

Definition at line 427 of file tlb.hh.

Referenced by insert(), and translateFunctional().

cpsr

CPSR gem5::ArmISA::TLB::cpsr

protected

Definition at line 418 of file tlb.hh.

curTranType

ArmTranslationType gem5::ArmISA::TLB::curTranType

protected

Definition at line 435 of file tlb.hh.

dacr

uint32_t gem5::ArmISA::TLB::dacr

protected

Definition at line 432 of file tlb.hh.

directToStage2

bool gem5::ArmISA::TLB::directToStage2

protected

Definition at line 165 of file tlb.hh.

Referenced by takeOverFrom(), and translateFunctional().

haveLargeAsid64

bool gem5::ArmISA::TLB::haveLargeAsid64

protected

Definition at line 440 of file tlb.hh.

Referenced by TLB().

haveLPAE

bool gem5::ArmISA::TLB::haveLPAE

protected

Definition at line 438 of file tlb.hh.

Referenced by TLB().

haveVirtualization

bool gem5::ArmISA::TLB::haveVirtualization

protected

Definition at line 439 of file tlb.hh.

Referenced by TLB().

hcr

HCR gem5::ArmISA::TLB::hcr

protected

Definition at line 431 of file tlb.hh.

isHyp

bool gem5::ArmISA::TLB::isHyp

protected

Definition at line 425 of file tlb.hh.

Referenced by insert(), and translateFunctional().

isPriv

bool gem5::ArmISA::TLB::isPriv

protected

Definition at line 423 of file tlb.hh.

isSecure

bool gem5::ArmISA::TLB::isSecure

protected

Definition at line 424 of file tlb.hh.

Referenced by translateFunctional().

isStage2

bool gem5::ArmISA::TLB::isStage2

protected

Definition at line 158 of file tlb.hh.

Referenced by takeOverFrom().

m5opRange

AddrRange gem5::ArmISA::TLB::m5opRange

protected

Definition at line 443 of file tlb.hh.

Referenced by finalizePhysical(), and TLB().

miscRegContext

ContextID gem5::ArmISA::TLB::miscRegContext

protected

Definition at line 434 of file tlb.hh.

miscRegValid

bool gem5::ArmISA::TLB::miscRegValid

protected

Definition at line 433 of file tlb.hh.

Referenced by drainResume(), and invalidateMiscReg().

nmrr

NMRR gem5::ArmISA::TLB::nmrr

protected

Definition at line 430 of file tlb.hh.

physAddrRange

uint8_t gem5::ArmISA::TLB::physAddrRange

protected

Definition at line 441 of file tlb.hh.

Referenced by TLB().

ppRefills

probing::PMUUPtr gem5::ArmISA::TLB::ppRefills

protected

PMU probe for TLB refills.

Definition at line 203 of file tlb.hh.

Referenced by insert().

prrr

PRRR gem5::ArmISA::TLB::prrr

protected

Definition at line 429 of file tlb.hh.

rangeMRU

int gem5::ArmISA::TLB::rangeMRU

protected

Definition at line 205 of file tlb.hh.

Referenced by lookup().

scr

SCR gem5::ArmISA::TLB::scr

protected

Definition at line 422 of file tlb.hh.

sctlr

SCTLR gem5::ArmISA::TLB::sctlr

protected

Definition at line 421 of file tlb.hh.

size

int gem5::ArmISA::TLB::size

protected

Definition at line 157 of file tlb.hh.

Referenced by flush(), flushAll(), getsize(), insert(), lookup(), and printTlb().

stage2DescReq

bool gem5::ArmISA::TLB::stage2DescReq

protected

Definition at line 163 of file tlb.hh.

Referenced by takeOverFrom().

stage2Req

bool gem5::ArmISA::TLB::stage2Req

protected

Definition at line 159 of file tlb.hh.

Referenced by takeOverFrom().

stage2Tlb

TLB* gem5::ArmISA::TLB::stage2Tlb

protected

Definition at line 169 of file tlb.hh.

Referenced by setStage2Tlb(), takeOverFrom(), and translateFunctional().

stats

gem5::ArmISA::TLB::TlbStats gem5::ArmISA::TLB::stats

protected

Referenced by _flushMva(), flush(), flushAll(), insert(), and lookup().

table

TlbEntry* gem5::ArmISA::TLB::table

protected

Definition at line 156 of file tlb.hh.

Referenced by flush(), flushAll(), insert(), gem5::PowerISA::TLB::lookup(), lookup(), printTlb(), and ~TLB().

tableWalker

TableWalker* gem5::ArmISA::TLB::tableWalker

protected

Definition at line 168 of file tlb.hh.

Referenced by getTableWalker(), and setTableWalker().

test

TlbTestInterface* gem5::ArmISA::TLB::test

protected

Definition at line 171 of file tlb.hh.

ttbcr

TTBCR gem5::ArmISA::TLB::ttbcr

protected

Definition at line 426 of file tlb.hh.

vmid

vmid_t gem5::ArmISA::TLB::vmid

protected

Definition at line 428 of file tlb.hh.

Referenced by _flushMva(), flush(), insert(), lookup(), and translateFunctional().

---

The documentation for this class was generated from the following files:

• arch/arm/tlb.hh
• arch/arm/tlb.cc