#include <thread_context.hh>

Inheritance diagram for gem5::Iris::ThreadContext:

Classes
struct	BpInfo

Public Types
typedef std::map< std::string, iris::ResourceInfo >	ResourceMap

typedef std::vector< iris::ResourceId >	ResourceIds

typedef std::map< int, std::string >	IdxNameMap

Public Types inherited from gem5::ThreadContext
enum	Status { Active, Suspended, Halting, Halted }

Public Member Functions
	ThreadContext (gem5::BaseCPU cpu, int id, System system, gem5::BaseMMU mmu, gem5::BaseISA isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)

virtual	~ThreadContext ()

virtual bool	translateAddress (Addr &paddr, Addr vaddr)=0

bool	schedule (PCEvent *e) override

bool	remove (PCEvent *e) override

void	scheduleInstCountEvent (Event *event, Tick count) override

void	descheduleInstCountEvent (Event *event) override

Tick	getCurrentInstCount () override

gem5::BaseCPU *	getCpuPtr () override

int	cpuId () const override

uint32_t	socketId () const override

int	threadId () const override

void	setThreadId (int id) override

int	contextId () const override

void	setContextId (int id) override

BaseMMU *	getMMUPtr () override

CheckerCPU *	getCheckerCpuPtr () override

ArmISA::Decoder *	getDecoderPtr () override

System *	getSystemPtr () override

BaseISA *	getIsaPtr () override

PortProxy &	getVirtProxy () override

void	initMemProxies (gem5::ThreadContext *tc) override
	Initialise the physical and virtual port proxies and tie them to the data port of the CPU. More...

void	sendFunctional (PacketPtr pkt) override

Process *	getProcessPtr () override

void	setProcessPtr (Process *p) override

Status	status () const override

void	setStatus (Status new_status) override

void	activate () override
	Set the status to Active. More...

void	suspend () override
	Set the status to Suspended. More...

void	halt () override
	Set the status to Halted. More...

void	takeOverFrom (gem5::ThreadContext *old_context) override

void	regStats (const std::string &name) override

Tick	readLastActivate () override

Tick	readLastSuspend () override

void	copyArchRegs (gem5::ThreadContext *tc) override

void	clearArchRegs () override

RegVal	readIntReg (RegIndex reg_idx) const override

RegVal	readFloatReg (RegIndex reg_idx) const override

const ArmISA::VecRegContainer &	readVecReg (const RegId &reg) const override

ArmISA::VecRegContainer &	getWritableVecReg (const RegId &reg) override

const ArmISA::VecElem &	readVecElem (const RegId &reg) const override

const ArmISA::VecPredRegContainer &	readVecPredReg (const RegId &reg) const override

ArmISA::VecPredRegContainer &	getWritableVecPredReg (const RegId &reg) override

RegVal	readCCReg (RegIndex reg_idx) const override

void	setIntReg (RegIndex reg_idx, RegVal val) override

void	setFloatReg (RegIndex reg_idx, RegVal val) override

void	setVecReg (const RegId &reg, const ArmISA::VecRegContainer &val) override

void	setVecElem (const RegId &reg, const ArmISA::VecElem &val) override

void	setVecPredReg (const RegId &reg, const ArmISA::VecPredRegContainer &val) override

void	setCCReg (RegIndex reg_idx, RegVal val) override

void	pcStateNoRecord (const ArmISA::PCState &val) override

MicroPC	microPC () const override

ArmISA::PCState	pcState () const override

void	pcState (const ArmISA::PCState &val) override

Addr	instAddr () const override

Addr	nextInstAddr () const override

RegVal	readMiscRegNoEffect (RegIndex misc_reg) const override

RegVal	readMiscReg (RegIndex misc_reg) override

void	setMiscRegNoEffect (RegIndex misc_reg, const RegVal val) override

void	setMiscReg (RegIndex misc_reg, const RegVal val) override

RegId	flattenRegId (const RegId &regId) const override

unsigned	readStCondFailures () const override

void	setStCondFailures (unsigned sc_failures) override

void	htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override

BaseHTMCheckpointPtr &	getHtmCheckpointPtr () override

void	setHtmCheckpointPtr (BaseHTMCheckpointPtr cpt) override


RegVal	readIntRegFlat (RegIndex idx) const override
	Flat register interfaces. More...

void	setIntRegFlat (RegIndex idx, uint64_t val) override

RegVal	readFloatRegFlat (RegIndex idx) const override

void	setFloatRegFlat (RegIndex idx, RegVal val) override

const ArmISA::VecRegContainer &	readVecRegFlat (RegIndex idx) const override

ArmISA::VecRegContainer &	getWritableVecRegFlat (RegIndex idx) override

void	setVecRegFlat (RegIndex idx, const ArmISA::VecRegContainer &val) override

const ArmISA::VecElem &	readVecElemFlat (RegIndex idx, const ElemIndex &elemIdx) const override

void	setVecElemFlat (RegIndex idx, const ElemIndex &elemIdx, const ArmISA::VecElem &val) override

const ArmISA::VecPredRegContainer &	readVecPredRegFlat (RegIndex idx) const override

ArmISA::VecPredRegContainer &	getWritableVecPredRegFlat (RegIndex idx) override

void	setVecPredRegFlat (RegIndex idx, const ArmISA::VecPredRegContainer &val) override

RegVal	readCCRegFlat (RegIndex idx) const override

void	setCCRegFlat (RegIndex idx, RegVal val) override

Public Member Functions inherited from gem5::ThreadContext
bool	getUseForClone ()

void	setUseForClone (bool new_val)

void	quiesce ()
	Quiesce thread context. More...

void	quiesceTick (Tick resume)
	Quiesce, suspend, and schedule activate at resume. More...

virtual void	setVecPredReg (const RegId &reg, const TheISA::VecPredRegContainer &val)=0

void	setNPC (Addr val)

virtual int	exit ()

virtual void	setVecPredRegFlat (RegIndex idx, const TheISA::VecPredRegContainer &val)=0

Protected Types
using	BpId = uint64_t

using	BpInfoPtr = std::unique_ptr< BpInfo >

using	BpInfoMap = std::map< Addr, BpInfoPtr >

using	BpInfoIt = BpInfoMap::iterator

Protected Member Functions
virtual void	initFromIrisInstance (const ResourceMap &resources)

iris::ResourceId	extractResourceId (const ResourceMap &resources, const std::string &name)

void	extractResourceMap (ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)

void	maintainStepping ()

BpInfoIt	getOrAllocBp (Addr pc)

void	installBp (BpInfoIt it)

void	uninstallBp (BpInfoIt it)

void	delBp (BpInfoIt it)

virtual const std::vector< iris::MemorySpaceId > &	getBpSpaceIds () const =0

iris::IrisErrorCode	instanceRegistryChanged (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	phaseInitLeave (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	simulationTimeEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	breakpointHit (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	semihostingEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisCppAdapter &	call () const

iris::IrisCppAdapter &	noThrow () const

bool	translateAddress (Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)

Protected Attributes
gem5::BaseCPU *	_cpu

int	_threadId

ContextID	_contextId

System *	_system

gem5::BaseMMU *	_mmu

gem5::BaseISA *	_isa

std::string	_irisPath

iris::InstanceId	_instId = iris::IRIS_UINT64_MAX

std::vector< ArmISA::VecRegContainer >	vecRegs

std::vector< ArmISA::VecPredRegContainer >	vecPredRegs

Status	_status = Active

Event *	enableAfterPseudoEvent

ResourceIds	miscRegIds

ResourceIds	intReg32Ids

ResourceIds	intReg64Ids

ResourceIds	flattenedIntIds

ResourceIds	ccRegIds

iris::ResourceId	pcRscId = iris::IRIS_UINT64_MAX

iris::ResourceId	icountRscId

ResourceIds	vecRegIds

ResourceIds	vecPredRegIds

std::vector< iris::MemorySpaceInfo >	memorySpaces

std::vector< iris::MemorySupportedAddressTranslationResult >	translations

std::unique_ptr< PortProxy >	virtProxy = nullptr

EventQueue	comInstEventQueue

BpInfoMap	bps

iris::EventStreamId	regEventStreamId

iris::EventStreamId	initEventStreamId

iris::EventStreamId	timeEventStreamId

iris::EventStreamId	breakpointEventStreamId

iris::EventStreamId	semihostingEventStreamId

iris::IrisInstance	client

Protected Attributes inherited from gem5::ThreadContext
bool	useForClone = false

Additional Inherited Members
Static Public Member Functions inherited from gem5::ThreadContext
static void	compare (ThreadContext one, ThreadContext two)
	function to compare two thread contexts (for debugging) More...

Public Attributes inherited from gem5::ThreadContext
int	intResult = DefaultIntResult

double	floatResult = DefaultFloatResult

int	intOffset = 0

Static Public Attributes inherited from gem5::ThreadContext
static const int	ints []

static const double	floats []

static const int	DefaultIntResult = 0

static const double	DefaultFloatResult = 0.0

Detailed Description

Definition at line 51 of file thread_context.hh.

Member Typedef Documentation

◆ BpId

using gem5::Iris::ThreadContext::BpId = uint64_t

protected

Definition at line 112 of file thread_context.hh.

◆ BpInfoIt

using gem5::Iris::ThreadContext::BpInfoIt = BpInfoMap::iterator

protected

Definition at line 129 of file thread_context.hh.

◆ BpInfoMap

using gem5::Iris::ThreadContext::BpInfoMap = std::map<Addr, BpInfoPtr>

protected

Definition at line 128 of file thread_context.hh.

◆ BpInfoPtr

using gem5::Iris::ThreadContext::BpInfoPtr = std::unique_ptr<BpInfo>

protected

Definition at line 127 of file thread_context.hh.

◆ IdxNameMap

typedef std::map<int, std::string> gem5::Iris::ThreadContext::IdxNameMap

Definition at line 57 of file thread_context.hh.

◆ ResourceIds

typedef std::vector<iris::ResourceId> gem5::Iris::ThreadContext::ResourceIds

Definition at line 56 of file thread_context.hh.

◆ ResourceMap

typedef std::map<std::string, iris::ResourceInfo> gem5::Iris::ThreadContext::ResourceMap

Definition at line 54 of file thread_context.hh.

Constructor & Destructor Documentation

◆ ThreadContext()

gem5::Iris::ThreadContext::ThreadContext	(	gem5::BaseCPU *	cpu,
		int	id,
		System *	system,
		gem5::BaseMMU *	mmu,
		gem5::BaseISA *	isa,
		iris::IrisConnectionInterface *	iris_if,
		const std::string &	iris_path
	)

Definition at line 310 of file thread_context.cc.

References _instId, breakpointEventStreamId, call(), client, enableAfterPseudoEvent, initEventStreamId, noThrow(), regEventStreamId, semihostingEventStreamId, gem5::EventBase::Sim_Exit_Pri, and timeEventStreamId.

◆ ~ThreadContext()

gem5::Iris::ThreadContext::~ThreadContext ( )

virtual

Reimplemented from gem5::ThreadContext.

Definition at line 377 of file thread_context.cc.

References call(), client, gem5::EventManager::deschedule(), enableAfterPseudoEvent, getCpuPtr(), initEventStreamId, regEventStreamId, gem5::Event::scheduled(), and timeEventStreamId.

Member Function Documentation

◆ activate()

void gem5::Iris::ThreadContext::activate ( )

inlineoverridevirtual

Set the status to Active.

Implements gem5::ThreadContext.

Definition at line 236 of file thread_context.hh.

References gem5::ThreadContext::Active, and setStatus().

◆ breakpointHit()

iris::IrisErrorCode gem5::Iris::ThreadContext::breakpointHit	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 268 of file thread_context.cc.

References gem5::ArmISA::e, getOrAllocBp(), and gem5::MipsISA::pc.

◆ call()

iris::IrisCppAdapter& gem5::Iris::ThreadContext::call ( ) const

inlineprotected

◆ clearArchRegs()

void gem5::Iris::ThreadContext::clearArchRegs ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 267 of file thread_context.hh.

References warn.

◆ contextId()

int gem5::Iris::ThreadContext::contextId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 194 of file thread_context.hh.

References _contextId.

◆ copyArchRegs()

void gem5::Iris::ThreadContext::copyArchRegs ( gem5::ThreadContext * tc )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 261 of file thread_context.hh.

References panic.

◆ cpuId()

int gem5::Iris::ThreadContext::cpuId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 188 of file thread_context.hh.

References _cpu, and gem5::BaseCPU::cpuId().

◆ delBp()

void gem5::Iris::ThreadContext::delBp ( BpInfoIt it )

protected

Definition at line 182 of file thread_context.cc.

References bps, panic_if, and uninstallBp().

Referenced by remove().

◆ descheduleInstCountEvent()

void gem5::Iris::ThreadContext::descheduleInstCountEvent ( Event * event )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 465 of file thread_context.cc.

References comInstEventQueue, gem5::EventQueue::deschedule(), gem5::MipsISA::event, and maintainStepping().

◆ extractResourceId()

iris::ResourceId gem5::Iris::ThreadContext::extractResourceId	(	const ResourceMap &	resources,
		const std::string &	name
	)

protected

Definition at line 97 of file thread_context.cc.

References name().

Referenced by extractResourceMap(), gem5::fastmodel::CortexR52TC::initFromIrisInstance(), and gem5::fastmodel::CortexA76TC::initFromIrisInstance().

◆ extractResourceMap()

void gem5::Iris::ThreadContext::extractResourceMap	(	ResourceIds &	ids,
		const ResourceMap &	resources,
		const IdxNameMap &	idx_names
	)

protected

Definition at line 104 of file thread_context.cc.

References extractResourceId(), gem5::ArmISA::ids, and name().

Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), and gem5::fastmodel::CortexA76TC::initFromIrisInstance().

◆ flattenRegId()

RegId gem5::Iris::ThreadContext::flattenRegId ( const RegId & regId ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 366 of file thread_context.hh.

References panic.

◆ getBpSpaceIds()

virtual const std::vector<iris::MemorySpaceId>& gem5::Iris::ThreadContext::getBpSpaceIds ( ) const

protectedpure virtual

Implemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Referenced by installBp().

◆ getCheckerCpuPtr()

CheckerCPU* gem5::Iris::ThreadContext::getCheckerCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 203 of file thread_context.hh.

◆ getCpuPtr()

gem5::BaseCPU* gem5::Iris::ThreadContext::getCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 187 of file thread_context.hh.

References _cpu.

Referenced by semihostingEvent(), sendFunctional(), setStatus(), and ~ThreadContext().

◆ getCurrentInstCount()

Tick gem5::Iris::ThreadContext::getCurrentInstCount ( )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 472 of file thread_context.cc.

References _instId, call(), gem5::X86ISA::count, and panic_if.

Referenced by maintainStepping(), and scheduleInstCountEvent().

◆ getDecoderPtr()

ArmISA::Decoder* gem5::Iris::ThreadContext::getDecoderPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 205 of file thread_context.hh.

References panic.

◆ getHtmCheckpointPtr()

BaseHTMCheckpointPtr& gem5::Iris::ThreadContext::getHtmCheckpointPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 461 of file thread_context.hh.

References panic.

◆ getIsaPtr()

BaseISA* gem5::Iris::ThreadContext::getIsaPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 213 of file thread_context.hh.

References _isa.

◆ getMMUPtr()

BaseMMU* gem5::Iris::ThreadContext::getMMUPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 198 of file thread_context.hh.

References _mmu.

◆ getOrAllocBp()

ThreadContext::BpInfoIt gem5::Iris::ThreadContext::getOrAllocBp ( Addr pc )

protected

Definition at line 149 of file thread_context.cc.

References bps, panic_if, and gem5::MipsISA::pc.

Referenced by breakpointHit(), remove(), and schedule().

◆ getProcessPtr()

Process* gem5::Iris::ThreadContext::getProcessPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 224 of file thread_context.hh.

References panic.

◆ getSystemPtr()

System* gem5::Iris::ThreadContext::getSystemPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 210 of file thread_context.hh.

References _cpu, and gem5::BaseCPU::system.

◆ getVirtProxy()

PortProxy& gem5::Iris::ThreadContext::getVirtProxy ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 218 of file thread_context.hh.

References virtProxy.

◆ getWritableVecPredReg()

ArmISA::VecPredRegContainer& gem5::Iris::ThreadContext::getWritableVecPredReg ( const RegId & reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 299 of file thread_context.hh.

References panic.

◆ getWritableVecPredRegFlat()

ArmISA::VecPredRegContainer& gem5::Iris::ThreadContext::getWritableVecPredRegFlat ( RegIndex idx )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 438 of file thread_context.hh.

References panic.

◆ getWritableVecReg()

ArmISA::VecRegContainer& gem5::Iris::ThreadContext::getWritableVecReg ( const RegId & reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 285 of file thread_context.hh.

References panic.

◆ getWritableVecRegFlat()

ArmISA::VecRegContainer& gem5::Iris::ThreadContext::getWritableVecRegFlat ( RegIndex idx )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 413 of file thread_context.hh.

References panic.

◆ halt()

void gem5::Iris::ThreadContext::halt ( )

inlineoverridevirtual

Set the status to Halted.

Implements gem5::ThreadContext.

Definition at line 238 of file thread_context.hh.

References gem5::ThreadContext::Halted, and setStatus().

◆ htmAbortTransaction()

void gem5::Iris::ThreadContext::htmAbortTransaction	(	uint64_t	htm_uid,
		HtmFailureFaultCause	cause
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 455 of file thread_context.hh.

References panic.

◆ initFromIrisInstance()

void gem5::Iris::ThreadContext::initFromIrisInstance ( const ResourceMap & resources )

protectedvirtual

Reimplemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Definition at line 60 of file thread_context.cc.

References _instId, _status, gem5::ThreadContext::Active, bps, breakpointEventStreamId, call(), client, gem5::statistics::enabled(), installBp(), memorySpaces, semihostingEventStreamId, suspend(), gem5::ThreadContext::Suspended, and translations.

Referenced by phaseInitLeave().

◆ initMemProxies()

void gem5::Iris::ThreadContext::initMemProxies ( gem5::ThreadContext * tc )

overridevirtual

Initialise the physical and virtual port proxies and tie them to the data port of the CPU.

tc ThreadContext for the virtual-to-physical translation

Implements gem5::ThreadContext.

Definition at line 481 of file thread_context.cc.

References gem5::FullSystem, gem5::SETranslatingPortProxy::NextPage, and virtProxy.

◆ instAddr()

Addr gem5::Iris::ThreadContext::instAddr ( ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 560 of file thread_context.cc.

References pcState().

◆ installBp()

void gem5::Iris::ThreadContext::installBp ( BpInfoIt it )

protected

Definition at line 162 of file thread_context.cc.

References _instId, call(), getBpSpaceIds(), gem5::ArmISA::id, and gem5::MipsISA::pc.

Referenced by initFromIrisInstance(), and schedule().

◆ instanceRegistryChanged()

iris::IrisErrorCode gem5::Iris::ThreadContext::instanceRegistryChanged	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 194 of file thread_context.cc.

References _instId, _irisPath, gem5::MipsISA::event, gem5::ArmISA::id, name(), and panic.

◆ maintainStepping()

void gem5::Iris::ThreadContext::maintainStepping ( )

protected

Definition at line 120 of file thread_context.cc.

References _instId, call(), comInstEventQueue, gem5::EventQueue::empty(), getCurrentInstCount(), gem5::EventQueue::nextTick(), and gem5::EventQueue::serviceEvents().

Referenced by descheduleInstCountEvent(), scheduleInstCountEvent(), and simulationTimeEvent().

◆ microPC()

MicroPC gem5::Iris::ThreadContext::microPC ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 344 of file thread_context.hh.

◆ nextInstAddr()

Addr gem5::Iris::ThreadContext::nextInstAddr ( ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 566 of file thread_context.cc.

References pcState().

◆ noThrow()

iris::IrisCppAdapter& gem5::Iris::ThreadContext::noThrow ( ) const

inlineprotected

Definition at line 166 of file thread_context.hh.

References client.

Referenced by ThreadContext(), and translateAddress().

◆ pcState() [1/2]

ArmISA::PCState gem5::Iris::ThreadContext::pcState ( ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 522 of file thread_context.cc.

References _instId, gem5::X86ISA::addr, call(), gem5::ArmISA::itState(), gem5::ArmISA::MISCREG_CPSR, gem5::MipsISA::pc, pcRscId, and readMiscRegNoEffect().

Referenced by instAddr(), nextInstAddr(), and pcStateNoRecord().

◆ pcState() [2/2]

void gem5::Iris::ThreadContext::pcState ( const ArmISA::PCState & val )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 547 of file thread_context.cc.

References _instId, call(), gem5::ArmISA::MISCREG_CPSR, gem5::MipsISA::pc, pcRscId, readMiscRegNoEffect(), and gem5::X86ISA::val.

◆ pcStateNoRecord()

void gem5::Iris::ThreadContext::pcStateNoRecord ( const ArmISA::PCState & val )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 343 of file thread_context.hh.

References pcState(), and gem5::X86ISA::val.

◆ phaseInitLeave()

iris::IrisErrorCode gem5::Iris::ThreadContext::phaseInitLeave	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 216 of file thread_context.cc.

References _instId, call(), initFromIrisInstance(), and name().

◆ readCCReg()

RegVal gem5::Iris::ThreadContext::readCCReg ( RegIndex reg_idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 305 of file thread_context.hh.

References readCCRegFlat().

◆ readCCRegFlat()

RegVal gem5::Iris::ThreadContext::readCCRegFlat ( RegIndex idx ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 641 of file thread_context.cc.

References _instId, call(), and ccRegIds.

Referenced by readCCReg(), gem5::fastmodel::CortexA76TC::readCCRegFlat(), and gem5::fastmodel::CortexR52TC::readCCRegFlat().

◆ readFloatReg()

RegVal gem5::Iris::ThreadContext::readFloatReg ( RegIndex reg_idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 278 of file thread_context.hh.

References panic.

◆ readFloatRegFlat()

RegVal gem5::Iris::ThreadContext::readFloatRegFlat ( RegIndex idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 401 of file thread_context.hh.

References panic.

◆ readIntReg()

RegVal gem5::Iris::ThreadContext::readIntReg ( RegIndex reg_idx ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 587 of file thread_context.cc.

References _instId, call(), intReg32Ids, intReg64Ids, gem5::ArmISA::MISCREG_CPSR, and readMiscRegNoEffect().

Referenced by semihostingEvent().

◆ readIntRegFlat()

RegVal gem5::Iris::ThreadContext::readIntRegFlat ( RegIndex idx ) const

overridevirtual

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Implements gem5::ThreadContext.

Definition at line 616 of file thread_context.cc.

References _instId, call(), and flattenedIntIds.

◆ readLastActivate()

Tick gem5::Iris::ThreadContext::readLastActivate ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 251 of file thread_context.hh.

References panic.

◆ readLastSuspend()

Tick gem5::Iris::ThreadContext::readLastSuspend ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 255 of file thread_context.hh.

References panic.

◆ readMiscReg()

RegVal gem5::Iris::ThreadContext::readMiscReg ( RegIndex misc_reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 353 of file thread_context.hh.

References readMiscRegNoEffect().

◆ readMiscRegNoEffect()

RegVal gem5::Iris::ThreadContext::readMiscRegNoEffect ( RegIndex misc_reg ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 572 of file thread_context.cc.

References _instId, call(), and miscRegIds.

Referenced by pcState(), readIntReg(), gem5::fastmodel::CortexA76TC::readIntRegFlat(), readMiscReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), setIntReg(), and gem5::fastmodel::CortexA76TC::setIntRegFlat().

◆ readStCondFailures()

unsigned gem5::Iris::ThreadContext::readStCondFailures ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 374 of file thread_context.hh.

References panic.

◆ readVecElem()

const ArmISA::VecElem& gem5::Iris::ThreadContext::readVecElem ( const RegId & reg ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 291 of file thread_context.hh.

References panic.

◆ readVecElemFlat()

const ArmISA::VecElem& gem5::Iris::ThreadContext::readVecElemFlat	(	RegIndex	idx,
		const ElemIndex &	elemIdx
	)		const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 424 of file thread_context.hh.

References panic.

◆ readVecPredReg()

const ArmISA::VecPredRegContainer & gem5::Iris::ThreadContext::readVecPredReg ( const RegId & reg ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 688 of file thread_context.cc.

References _instId, call(), gem5::RegId::index(), gem5::ArmISA::offset, gem5::X86ISA::reg, vecPredRegIds, and vecPredRegs.

Referenced by readVecPredRegFlat().

◆ readVecPredRegFlat()

const ArmISA::VecPredRegContainer & gem5::Iris::ThreadContext::readVecPredRegFlat ( RegIndex idx ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 717 of file thread_context.cc.

References readVecPredReg(), and gem5::VecPredRegClass.

◆ readVecReg()

const ArmISA::VecRegContainer & gem5::Iris::ThreadContext::readVecReg ( const RegId & reg ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 660 of file thread_context.cc.

References _instId, call(), gem5::RegId::index(), gem5::X86ISA::reg, vecRegIds, and vecRegs.

Referenced by readVecRegFlat().

◆ readVecRegFlat()

const ArmISA::VecRegContainer & gem5::Iris::ThreadContext::readVecRegFlat ( RegIndex idx ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 682 of file thread_context.cc.

References readVecReg(), and gem5::VecRegClass.

◆ regStats()

void gem5::Iris::ThreadContext::regStats ( const std::string & name )

inlineoverridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 246 of file thread_context.hh.

◆ remove()

bool gem5::Iris::ThreadContext::remove ( PCEvent * e )

overridevirtual

Implements gem5::PCEventScope.

Definition at line 412 of file thread_context.cc.

References delBp(), gem5::ArmISA::e, and getOrAllocBp().

◆ schedule()

bool gem5::Iris::ThreadContext::schedule ( PCEvent * e )

overridevirtual

Implements gem5::PCEventScope.

Definition at line 400 of file thread_context.cc.

References _instId, gem5::ArmISA::e, getOrAllocBp(), and installBp().

◆ scheduleInstCountEvent()

void gem5::Iris::ThreadContext::scheduleInstCountEvent	(	Event *	event,
		Tick	count
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 454 of file thread_context.cc.

References call(), comInstEventQueue, gem5::X86ISA::count, gem5::MipsISA::event, getCurrentInstCount(), maintainStepping(), and gem5::EventQueue::schedule().

◆ semihostingEvent()

iris::IrisErrorCode gem5::Iris::ThreadContext::semihostingEvent	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 289 of file thread_context.cc.

References _instId, call(), gem5::ArmSystem::callSemihosting(), gem5::curTick(), enableAfterPseudoEvent, getCpuPtr(), readIntReg(), gem5::EventManager::schedule(), and gem5::Event::scheduled().

◆ sendFunctional()

void gem5::Iris::ThreadContext::sendFunctional ( PacketPtr pkt )

overridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 493 of file thread_context.cc.

References getCpuPtr().

◆ setCCReg()

void gem5::Iris::ThreadContext::setCCReg	(	RegIndex	reg_idx,
		RegVal	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 338 of file thread_context.hh.

References setCCRegFlat(), and gem5::X86ISA::val.

◆ setCCRegFlat()

void gem5::Iris::ThreadContext::setCCRegFlat	(	RegIndex	idx,
		RegVal	val
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 651 of file thread_context.cc.

References _instId, call(), ccRegIds, panic_if, and gem5::X86ISA::val.

Referenced by setCCReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), and gem5::fastmodel::CortexR52TC::setCCRegFlat().

◆ setContextId()

void gem5::Iris::ThreadContext::setContextId ( int id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 195 of file thread_context.hh.

References _contextId, and gem5::ArmISA::id.

◆ setFloatReg()

void gem5::Iris::ThreadContext::setFloatReg	(	RegIndex	reg_idx,
		RegVal	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 313 of file thread_context.hh.

References panic.

◆ setFloatRegFlat()

void gem5::Iris::ThreadContext::setFloatRegFlat	(	RegIndex	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 406 of file thread_context.hh.

References panic.

◆ setHtmCheckpointPtr()

void gem5::Iris::ThreadContext::setHtmCheckpointPtr ( BaseHTMCheckpointPtr cpt )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 467 of file thread_context.hh.

References panic.

◆ setIntReg()

void gem5::Iris::ThreadContext::setIntReg	(	RegIndex	reg_idx,
		RegVal	val
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 600 of file thread_context.cc.

References _instId, call(), intReg32Ids, intReg64Ids, gem5::ArmISA::MISCREG_CPSR, readMiscRegNoEffect(), and gem5::X86ISA::val.

◆ setIntRegFlat()

void gem5::Iris::ThreadContext::setIntRegFlat	(	RegIndex	idx,
		uint64_t	val
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 629 of file thread_context.cc.

References _instId, call(), flattenedIntIds, panic_if, and gem5::X86ISA::val.

◆ setMiscReg()

void gem5::Iris::ThreadContext::setMiscReg	(	RegIndex	misc_reg,
		const RegVal	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 360 of file thread_context.hh.

References setMiscRegNoEffect(), and gem5::X86ISA::val.

Referenced by gem5::fastmodel::CortexA76TC::setIntRegFlat().

◆ setMiscRegNoEffect()

void gem5::Iris::ThreadContext::setMiscRegNoEffect	(	RegIndex	misc_reg,
		const RegVal	val
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 580 of file thread_context.cc.

References _instId, call(), miscRegIds, and gem5::X86ISA::val.

Referenced by setMiscReg().

◆ setProcessPtr()

void gem5::Iris::ThreadContext::setProcessPtr ( Process * p )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 229 of file thread_context.hh.

References panic.

◆ setStatus()

void gem5::Iris::ThreadContext::setStatus ( Status new_status )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 507 of file thread_context.cc.

References _instId, _status, gem5::ThreadContext::Active, call(), gem5::EventManager::deschedule(), enableAfterPseudoEvent, getCpuPtr(), and gem5::Event::scheduled().

Referenced by activate(), halt(), and suspend().

◆ setStCondFailures()

void gem5::Iris::ThreadContext::setStCondFailures ( unsigned sc_failures )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 380 of file thread_context.hh.

References panic.

◆ setThreadId()

void gem5::Iris::ThreadContext::setThreadId ( int id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 192 of file thread_context.hh.

References _threadId, and gem5::ArmISA::id.

◆ setVecElem()

void gem5::Iris::ThreadContext::setVecElem	(	const RegId &	reg,
		const ArmISA::VecElem &	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 325 of file thread_context.hh.

References panic.

◆ setVecElemFlat()

void gem5::Iris::ThreadContext::setVecElemFlat	(	RegIndex	idx,
		const ElemIndex &	elemIdx,
		const ArmISA::VecElem &	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 429 of file thread_context.hh.

References panic.

◆ setVecPredReg()

void gem5::Iris::ThreadContext::setVecPredReg	(	const RegId &	reg,
		const ArmISA::VecPredRegContainer &	val
	)

inlineoverride

Definition at line 331 of file thread_context.hh.

References panic.

◆ setVecPredRegFlat()

void gem5::Iris::ThreadContext::setVecPredRegFlat	(	RegIndex	idx,
		const ArmISA::VecPredRegContainer &	val
	)

inlineoverride

Definition at line 443 of file thread_context.hh.

References panic.

◆ setVecReg()

void gem5::Iris::ThreadContext::setVecReg	(	const RegId &	reg,
		const ArmISA::VecRegContainer &	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 319 of file thread_context.hh.

References panic.

◆ setVecRegFlat()

void gem5::Iris::ThreadContext::setVecRegFlat	(	RegIndex	idx,
		const ArmISA::VecRegContainer &	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 418 of file thread_context.hh.

References panic.

◆ simulationTimeEvent()

iris::IrisErrorCode gem5::Iris::ThreadContext::simulationTimeEvent	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 246 of file thread_context.cc.

References call(), and maintainStepping().

◆ socketId()

uint32_t gem5::Iris::ThreadContext::socketId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 189 of file thread_context.hh.

References _cpu, and gem5::BaseCPU::socketId().

◆ status()

ThreadContext::Status gem5::Iris::ThreadContext::status ( ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 501 of file thread_context.cc.

References _status.

◆ suspend()

void gem5::Iris::ThreadContext::suspend ( )

inlineoverridevirtual

Set the status to Suspended.

Implements gem5::ThreadContext.

Definition at line 237 of file thread_context.hh.

References setStatus(), and gem5::ThreadContext::Suspended.

Referenced by initFromIrisInstance().

◆ takeOverFrom()

void gem5::Iris::ThreadContext::takeOverFrom ( gem5::ThreadContext * old_context )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 241 of file thread_context.hh.

References panic.

◆ threadId()

int gem5::Iris::ThreadContext::threadId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 191 of file thread_context.hh.

References _threadId.

◆ translateAddress() [1/2]

virtual bool gem5::Iris::ThreadContext::translateAddress	(	Addr &	paddr,
		Addr	vaddr
	)

pure virtual

Implemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

◆ translateAddress() [2/2]

bool gem5::Iris::ThreadContext::translateAddress	(	Addr &	paddr,
		iris::MemorySpaceId	p_space,
		Addr	vaddr,
		iris::MemorySpaceId	v_space
	)

protected

Definition at line 424 of file thread_context.cc.

References _instId, noThrow(), panic, translations, gem5::MipsISA::vaddr, and warn.

◆ uninstallBp()

void gem5::Iris::ThreadContext::uninstallBp ( BpInfoIt it )

protected

Definition at line 174 of file thread_context.cc.

References _instId, and call().

Referenced by delBp().

Member Data Documentation

◆ _contextId

ContextID gem5::Iris::ThreadContext::_contextId

protected

Definition at line 62 of file thread_context.hh.

Referenced by contextId(), and setContextId().

◆ _cpu

gem5::BaseCPU* gem5::Iris::ThreadContext::_cpu

protected

Definition at line 60 of file thread_context.hh.

Referenced by cpuId(), getCpuPtr(), getSystemPtr(), and socketId().

◆ _instId

iris::InstanceId gem5::Iris::ThreadContext::_instId = iris::IRIS_UINT64_MAX

protected

◆ _irisPath

std::string gem5::Iris::ThreadContext::_irisPath

protected

Definition at line 67 of file thread_context.hh.

Referenced by instanceRegistryChanged().

◆ _isa

gem5::BaseISA* gem5::Iris::ThreadContext::_isa

protected

Definition at line 65 of file thread_context.hh.

Referenced by getIsaPtr().

◆ _mmu

gem5::BaseMMU* gem5::Iris::ThreadContext::_mmu

protected

Definition at line 64 of file thread_context.hh.

Referenced by getMMUPtr().

◆ _status

Status gem5::Iris::ThreadContext::_status = Active

protected

Definition at line 75 of file thread_context.hh.

Referenced by initFromIrisInstance(), setStatus(), and status().

◆ _system

System* gem5::Iris::ThreadContext::_system

protected

Definition at line 63 of file thread_context.hh.

◆ _threadId

int gem5::Iris::ThreadContext::_threadId

protected

Definition at line 61 of file thread_context.hh.

Referenced by setThreadId(), and threadId().

◆ bps

BpInfoMap gem5::Iris::ThreadContext::bps

protected

Definition at line 131 of file thread_context.hh.

Referenced by delBp(), getOrAllocBp(), and initFromIrisInstance().

◆ breakpointEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::breakpointEventStreamId

protected

Definition at line 161 of file thread_context.hh.

Referenced by initFromIrisInstance(), and ThreadContext().

◆ ccRegIds

ResourceIds gem5::Iris::ThreadContext::ccRegIds

protected

Definition at line 90 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readCCRegFlat(), and setCCRegFlat().

◆ client

iris::IrisInstance gem5::Iris::ThreadContext::client

mutableprotected

Definition at line 164 of file thread_context.hh.

Referenced by call(), initFromIrisInstance(), noThrow(), ThreadContext(), and ~ThreadContext().

◆ comInstEventQueue

EventQueue gem5::Iris::ThreadContext::comInstEventQueue

protected

Definition at line 105 of file thread_context.hh.

Referenced by descheduleInstCountEvent(), maintainStepping(), and scheduleInstCountEvent().

◆ enableAfterPseudoEvent

Event* gem5::Iris::ThreadContext::enableAfterPseudoEvent

protected

Definition at line 76 of file thread_context.hh.

Referenced by semihostingEvent(), setStatus(), ThreadContext(), and ~ThreadContext().

◆ flattenedIntIds

ResourceIds gem5::Iris::ThreadContext::flattenedIntIds

protected

Definition at line 89 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readIntRegFlat(), and setIntRegFlat().

◆ icountRscId

iris::ResourceId gem5::Iris::ThreadContext::icountRscId

protected

Definition at line 93 of file thread_context.hh.

◆ initEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::initEventStreamId

protected

Definition at line 159 of file thread_context.hh.

Referenced by ThreadContext(), and ~ThreadContext().

◆ intReg32Ids

ResourceIds gem5::Iris::ThreadContext::intReg32Ids

protected

Definition at line 87 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), gem5::fastmodel::CortexR52TC::readIntReg(), readIntReg(), gem5::fastmodel::CortexR52TC::setIntReg(), and setIntReg().

◆ intReg64Ids

ResourceIds gem5::Iris::ThreadContext::intReg64Ids

protected

Definition at line 88 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readIntReg(), and setIntReg().

◆ memorySpaces

std::vector<iris::MemorySpaceInfo> gem5::Iris::ThreadContext::memorySpaces

protected

Definition at line 98 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexA76TC::getBpSpaceIds(), gem5::fastmodel::CortexR52TC::getBpSpaceIds(), initFromIrisInstance(), gem5::fastmodel::CortexR52TC::translateAddress(), and gem5::fastmodel::CortexA76TC::translateAddress().

◆ miscRegIds

ResourceIds gem5::Iris::ThreadContext::miscRegIds

protected

Definition at line 86 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readMiscRegNoEffect(), and setMiscRegNoEffect().

◆ pcRscId

iris::ResourceId gem5::Iris::ThreadContext::pcRscId = iris::IRIS_UINT64_MAX

protected

Definition at line 92 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and pcState().

◆ regEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::regEventStreamId

protected

Definition at line 158 of file thread_context.hh.

Referenced by ThreadContext(), and ~ThreadContext().

◆ semihostingEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::semihostingEventStreamId

protected

Definition at line 162 of file thread_context.hh.

Referenced by initFromIrisInstance(), and ThreadContext().

◆ timeEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::timeEventStreamId

protected

Definition at line 160 of file thread_context.hh.

Referenced by ThreadContext(), and ~ThreadContext().

◆ translations

std::vector<iris::MemorySupportedAddressTranslationResult> gem5::Iris::ThreadContext::translations

protected

Definition at line 99 of file thread_context.hh.

Referenced by initFromIrisInstance(), and translateAddress().

◆ vecPredRegIds

ResourceIds gem5::Iris::ThreadContext::vecPredRegIds

protected

Definition at line 96 of file thread_context.hh.

Referenced by readVecPredReg().

◆ vecPredRegs

std::vector<ArmISA::VecPredRegContainer> gem5::Iris::ThreadContext::vecPredRegs

mutableprotected

Definition at line 73 of file thread_context.hh.

Referenced by readVecPredReg().

◆ vecRegIds

ResourceIds gem5::Iris::ThreadContext::vecRegIds

protected

Definition at line 95 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and readVecReg().

◆ vecRegs

std::vector<ArmISA::VecRegContainer> gem5::Iris::ThreadContext::vecRegs

mutableprotected

Definition at line 72 of file thread_context.hh.

Referenced by readVecReg().

◆ virtProxy

std::unique_ptr<PortProxy> gem5::Iris::ThreadContext::virtProxy = nullptr

protected

Definition at line 101 of file thread_context.hh.

Referenced by getVirtProxy(), and initMemProxies().

The documentation for this class was generated from the following files:

arch/arm/fastmodel/iris/thread_context.hh
arch/arm/fastmodel/iris/thread_context.cc

Classes

Public Types

Public Member Functions

Protected Types

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ BpId

◆ BpInfoIt

◆ BpInfoMap

◆ BpInfoPtr

◆ IdxNameMap

◆ ResourceIds

◆ ResourceMap

Constructor & Destructor Documentation

◆ ThreadContext()

◆ ~ThreadContext()

Member Function Documentation

◆ activate()

◆ breakpointHit()

◆ call()

◆ clearArchRegs()

◆ contextId()

◆ copyArchRegs()

◆ cpuId()

◆ delBp()

◆ descheduleInstCountEvent()

◆ extractResourceId()

◆ extractResourceMap()

◆ flattenRegId()

◆ getBpSpaceIds()

◆ getCheckerCpuPtr()

◆ getCpuPtr()

◆ getCurrentInstCount()

◆ getDecoderPtr()

◆ getHtmCheckpointPtr()

◆ getIsaPtr()

◆ getMMUPtr()

◆ getOrAllocBp()

◆ getProcessPtr()

◆ getSystemPtr()

◆ getVirtProxy()

◆ getWritableVecPredReg()

◆ getWritableVecPredRegFlat()

◆ getWritableVecReg()

◆ getWritableVecRegFlat()

◆ halt()

◆ htmAbortTransaction()

◆ initFromIrisInstance()

◆ initMemProxies()

◆ instAddr()

◆ installBp()

◆ instanceRegistryChanged()

◆ maintainStepping()

◆ microPC()

◆ nextInstAddr()

◆ noThrow()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ pcStateNoRecord()

◆ phaseInitLeave()

◆ readCCReg()

◆ readCCRegFlat()

◆ readFloatReg()

◆ readFloatRegFlat()

◆ readIntReg()

◆ readIntRegFlat()

◆ readLastActivate()

◆ readLastSuspend()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readStCondFailures()

◆ readVecElem()

◆ readVecElemFlat()

◆ readVecPredReg()

◆ readVecPredRegFlat()

◆ readVecReg()

◆ readVecRegFlat()