Static instruction class for unknown (illegal) instructions. More...
#include <unknown.hh>
Inheritance diagram for gem5::RiscvISA::Unknown:
Public Member Functions | |
| Unknown (MachInst _machInst) | |
| Fault | execute (ExecContext *, Trace::InstRecord *) const override |
| std::string | generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override |
| Internal function to generate disassembly string. More... | |
 Public Member Functions inherited from gem5::RiscvISA::RiscvStaticInst | |
| void | advancePC (PCState &pc) const override |
| PCState | buildRetPC (const PCState &curPC, const PCState &callPC) const override |
| size_t | asBytes (void *buf, size_t size) override |
| Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More... | |
| Public Member Functions inherited from gem5::StaticInst | |
| int8_t | numSrcRegs () const |
| Number of source registers. More... | |
| int8_t | numDestRegs () const |
| Number of destination registers. More... | |
| int8_t | numFPDestRegs () const |
| Number of floating-point destination regs. More... | |
| int8_t | numIntDestRegs () const |
| Number of integer destination regs. More... | |
| int8_t | numVecDestRegs () const |
| Number of vector destination regs. More... | |
| int8_t | numVecElemDestRegs () const |
| Number of vector element destination regs. More... | |
| int8_t | numVecPredDestRegs () const |
| Number of predicate destination regs. More... | |
| int8_t | numCCDestRegs () const |
| Number of coprocesor destination regs. More... | |
| bool | isNop () const |
| bool | isMemRef () const |
| bool | isLoad () const |
| bool | isStore () const |
| bool | isAtomic () const |
| bool | isStoreConditional () const |
| bool | isInstPrefetch () const |
| bool | isDataPrefetch () const |
| bool | isPrefetch () const |
| bool | isInteger () const |
| bool | isFloating () const |
| bool | isVector () const |
| bool | isControl () const |
| bool | isCall () const |
| bool | isReturn () const |
| bool | isDirectCtrl () const |
| bool | isIndirectCtrl () const |
| bool | isCondCtrl () const |
| bool | isUncondCtrl () const |
| bool | isSerializing () const |
| bool | isSerializeBefore () const |
| bool | isSerializeAfter () const |
| bool | isSquashAfter () const |
| bool | isFullMemBarrier () const |
| bool | isReadBarrier () const |
| bool | isWriteBarrier () const |
| bool | isNonSpeculative () const |
| bool | isQuiesce () const |
| bool | isUnverifiable () const |
| bool | isSyscall () const |
| bool | isMacroop () const |
| bool | isMicroop () const |
| bool | isDelayedCommit () const |
| bool | isLastMicroop () const |
| bool | isFirstMicroop () const |
| bool | isHtmStart () const |
| bool | isHtmStop () const |
| bool | isHtmCancel () const |
| bool | isHtmCmd () const |
| void | setFirstMicroop () |
| void | setLastMicroop () |
| void | setDelayedCommit () |
| void | setFlag (Flags f) |
| OpClass | opClass () const |
| Operation class. Used to select appropriate function unit in issue. More... | |
| const RegId & | destRegIdx (int i) const |
| Return logical index (architectural reg num) of i'th destination reg. More... | |
| void | setDestRegIdx (int i, const RegId &val) |
| const RegId & | srcRegIdx (int i) const |
| Return logical index (architectural reg num) of i'th source reg. More... | |
| void | setSrcRegIdx (int i, const RegId &val) |
| virtual uint64_t | getEMI () const |
| virtual | ~StaticInst () |
| virtual Fault | initiateAcc (ExecContext *xc, Trace::InstRecord *traceData) const |
| virtual Fault | completeAcc (Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const |
| virtual void | advancePC (TheISA::PCState &pc_state) const =0 |
| virtual TheISA::PCState | buildRetPC (const TheISA::PCState &cur_pc, const TheISA::PCState &call_pc) const |
| virtual StaticInstPtr | fetchMicroop (MicroPC upc) const |
| Return the microop that goes with a particular micropc. More... | |
| virtual TheISA::PCState | branchTarget (const TheISA::PCState &pc) const |
| Return the target address for a PC-relative branch. More... | |
| virtual TheISA::PCState | branchTarget (ThreadContext *tc) const |
| Return the target address for an indirect branch (jump). More... | |
| bool | hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const |
| Return true if the instruction is a control transfer, and if so, return the target address as well. More... | |
| virtual const std::string & | disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const |
| Return string representation of disassembled instruction. More... | |
| void | printFlags (std::ostream &outs, const std::string &separator) const |
| Print a separator separated list of this instruction's set flag names on the given stream. More... | |
| std::string | getName () |
| Return name of machine instruction. More... | |
| Public Member Functions inherited from gem5::RefCounted | |
| RefCounted () | |
| We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More... | |
| virtual | ~RefCounted () |
| We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More... | |
| void | incref () const |
| Increment the reference count. More... | |
| void | decref () const |
| Decrement the reference count and destroy the object if all references are gone. More... | |
Additional Inherited Members | |
| Public Types inherited from gem5::StaticInst | |
| using | RegIdArrayPtr = RegId(StaticInst::*)[] |
| Public Attributes inherited from gem5::RiscvISA::RiscvStaticInst | |
| ExtMachInst | machInst |
| Static Public Attributes inherited from gem5::StaticInst | |
| static StaticInstPtr | nullStaticInstPtr |
| Pointer to a statically allocated "null" instruction object. More... | |
| Protected Member Functions inherited from gem5::RiscvISA::RiscvStaticInst | |
| RiscvStaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) | |
| Protected Member Functions inherited from gem5::StaticInst | |
| void | setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest) |
| Set the pointers which point to the arrays of source and destination register indices. More... | |
| StaticInst (const char *_mnemonic, OpClass op_class) | |
| Constructor. More... | |
| template<typename T > | |
| size_t | simpleAsBytes (void *buf, size_t max_size, const T &t) |
| Protected Attributes inherited from gem5::StaticInst | |
| std::bitset< Num_Flags > | flags |
| Flag values for this instruction. More... | |
| OpClass | _opClass |
| See opClass(). More... | |
| int8_t | _numSrcRegs = 0 |
| See numSrcRegs(). More... | |
| int8_t | _numDestRegs = 0 |
| See numDestRegs(). More... | |
| int8_t | _numFPDestRegs = 0 |
| The following are used to track physical register usage for machines with separate int & FP reg files. More... | |
| int8_t | _numIntDestRegs = 0 |
| int8_t | _numCCDestRegs = 0 |
| int8_t | _numVecDestRegs = 0 |
| To use in architectures with vector register file. More... | |
| int8_t | _numVecElemDestRegs = 0 |
| int8_t | _numVecPredDestRegs = 0 |
| const char * | mnemonic |
| Base mnemonic (e.g., "add"). More... | |
| std::unique_ptr< std::string > | cachedDisassembly |
| String representation of disassembly (lazily evaluated via disassemble()). More... | |
Detailed Description
Static instruction class for unknown (illegal) instructions.
These cause simulator termination if they are executed in a non-speculative mode. This is a leaf class.
Definition at line 53 of file unknown.hh.
Constructor & Destructor Documentation
◆ Unknown()
|
inline |
Definition at line 56 of file unknown.hh.
Member Function Documentation
◆ execute()
|
inlineoverridevirtual |
Implements gem5::StaticInst.
Definition at line 61 of file unknown.hh.
References gem5::RiscvISA::RiscvStaticInst::machInst.
◆ generateDisassembly()
|
inlineoverridevirtual |
Internal function to generate disassembly string.
Implements gem5::StaticInst.
Definition at line 67 of file unknown.hh.
References gem5::csprintf(), and OPCODE.
The documentation for this class was generated from the following file:
- arch/riscv/insts/unknown.hh