#include <op_encodings.hh>

Inheritance diagram for gem5::VegaISA::Inst_SMEM:

Public Member Functions
	Inst_SMEM (InFmt_SMEM *, const std::string &opcode)

	~Inst_SMEM ()

int	instSize () const override

void	generateDisassembly () override

void	initOperandInfo () override

Public Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
	VEGAGPUStaticInst (const std::string &opcode)

	~VEGAGPUStaticInst ()

bool	isFlatScratchRegister (int opIdx) override

int	getOperandSize (int opIdx) override

int	coalescerTokenCount () const override
	Return the number of tokens needed by the coalescer. More...

ScalarRegU32	srcLiteral () const override

Public Member Functions inherited from gem5::GPUStaticInst
	GPUStaticInst (const std::string &opcode)

virtual	~GPUStaticInst ()

void	instAddr (int inst_addr)

int	instAddr () const

int	nextInstAddr () const

void	instNum (int num)

int	instNum ()

void	ipdInstNum (int num)

int	ipdInstNum () const

void	initDynOperandInfo (Wavefront wf, ComputeUnit cu)

virtual void	execute (GPUDynInstPtr gpuDynInst)=0

const std::string &	disassemble ()

virtual int	getNumOperands ()=0

virtual bool	isExecMaskRegister (int opIdx)=0

virtual int	numDstRegOperands ()=0

virtual int	numSrcRegOperands ()=0

int	numSrcVecOperands ()

int	numDstVecOperands ()

int	numSrcVecDWords ()

int	numDstVecDWords ()

int	numSrcScalarOperands ()

int	numDstScalarOperands ()

int	numSrcScalarDWords ()

int	numDstScalarDWords ()

int	maxOperandSize ()

bool	isALU () const

bool	isBranch () const

bool	isCondBranch () const

bool	isNop () const

bool	isReturn () const

bool	isEndOfKernel () const

bool	isKernelLaunch () const

bool	isSDWAInst () const

bool	isDPPInst () const

bool	isUnconditionalJump () const

bool	isSpecialOp () const

bool	isWaitcnt () const

bool	isSleep () const

bool	isBarrier () const

bool	isMemSync () const

bool	isMemRef () const

bool	isFlat () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isAtomicNoRet () const

bool	isAtomicRet () const

bool	isScalar () const

bool	readsSCC () const

bool	writesSCC () const

bool	readsVCC () const

bool	writesVCC () const

bool	readsEXEC () const

bool	writesEXEC () const

bool	readsMode () const

bool	writesMode () const

bool	ignoreExec () const

bool	isAtomicAnd () const

bool	isAtomicOr () const

bool	isAtomicXor () const

bool	isAtomicCAS () const

bool	isAtomicExch () const

bool	isAtomicAdd () const

bool	isAtomicSub () const

bool	isAtomicInc () const

bool	isAtomicDec () const

bool	isAtomicMax () const

bool	isAtomicMin () const

bool	isArgLoad () const

bool	isGlobalMem () const

bool	isLocalMem () const

bool	isArgSeg () const

bool	isGlobalSeg () const

bool	isGroupSeg () const

bool	isKernArgSeg () const

bool	isPrivateSeg () const

bool	isReadOnlySeg () const

bool	isSpillSeg () const

bool	isGloballyCoherent () const
	Coherence domain of a memory instruction. More...

bool	isSystemCoherent () const

bool	isF16 () const

bool	isF32 () const

bool	isF64 () const

bool	isFMA () const

bool	isMAC () const

bool	isMAD () const

virtual void	initiateAcc (GPUDynInstPtr gpuDynInst)

virtual void	completeAcc (GPUDynInstPtr gpuDynInst)

virtual uint32_t	getTargetPc ()

void	setFlag (Flags flag)

const std::string &	opcode () const

const std::vector< OperandInfo > &	srcOperands () const

const std::vector< OperandInfo > &	dstOperands () const

const std::vector< OperandInfo > &	srcVecRegOperands () const

const std::vector< OperandInfo > &	dstVecRegOperands () const

const std::vector< OperandInfo > &	srcScalarRegOperands () const

const std::vector< OperandInfo > &	dstScalarRegOperands () const

Protected Member Functions
template<int N>
void	initMemRead (GPUDynInstPtr gpuDynInst)
	initiate a memory read access for N dwords More...

template<int N>
void	initMemWrite (GPUDynInstPtr gpuDynInst)
	initiate a memory write access for N dwords More...

void	calcAddr (GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU64 &addr, ScalarRegU32 offset)
	For normal s_load_dword/s_store_dword instruction addresses. More...

void	calcAddr (GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU128 &s_rsrc_desc, ScalarRegU32 offset)
	For s_buffer_load_dword/s_buffer_store_dword instruction addresses. More...

Protected Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
void	panicUnimplemented () const

Protected Attributes
InFmt_SMEM	instData

InFmt_SMEM_1	extData

Protected Attributes inherited from gem5::VegaISA::VEGAGPUStaticInst
ScalarRegU32	_srcLiteral
	if the instruction has a src literal - an immediate value that is part of the instruction stream - we store that here More...

Protected Attributes inherited from gem5::GPUStaticInst
const std::string	_opcode

std::string	disassembly

int	_instNum

int	_instAddr

std::vector< OperandInfo >	srcOps

std::vector< OperandInfo >	dstOps

Additional Inherited Members
Public Types inherited from gem5::GPUStaticInst
enum	OpType { SRC_VEC, SRC_SCALAR, DST_VEC, DST_SCALAR }

typedef int(RegisterManager::*	MapRegFn) (Wavefront *, int)

Public Attributes inherited from gem5::GPUStaticInst
enums::StorageClassType	executed_as

Static Public Attributes inherited from gem5::GPUStaticInst
static uint64_t	dynamic_id_count

Detailed Description

Definition at line 178 of file op_encodings.hh.

Constructor & Destructor Documentation

◆ Inst_SMEM()

gem5::VegaISA::Inst_SMEM::Inst_SMEM	(	InFmt_SMEM *	iFmt,
		const std::string &	opcode
	)

Definition at line 481 of file op_encodings.cc.

References gem5::VegaISA::VEGAGPUStaticInst::_srcLiteral, extData, gem5::VegaISA::InFmt_SMEM::GLC, instData, and gem5::GPUStaticInst::setFlag().

◆ ~Inst_SMEM()

gem5::VegaISA::Inst_SMEM::~Inst_SMEM ( )

Definition at line 497 of file op_encodings.cc.

Member Function Documentation

◆ calcAddr() [1/2]

void gem5::VegaISA::Inst_SMEM::calcAddr	(	GPUDynInstPtr	gpu_dyn_inst,
		ConstScalarOperandU128 &	s_rsrc_desc,
		ScalarRegU32	offset
	)

inlineprotected

For s_buffer_load_dword/s_buffer_store_dword instruction addresses.

The s_buffer instructions use the same buffer resource descriptor as the MUBUF instructions.

The address is clamped if: Stride is zero: clamp if offset >= num_records Stride is non-zero: clamp if offset > (stride * num_records)

Definition at line 229 of file op_encodings.hh.

References gem5::ArmISA::offset, gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::rawDataPtr(), and gem5::MipsISA::vaddr.

◆ calcAddr() [2/2]

void gem5::VegaISA::Inst_SMEM::calcAddr	(	GPUDynInstPtr	gpu_dyn_inst,
		ConstScalarOperandU64 &	addr,
		ScalarRegU32	offset
	)

inlineprotected

For normal s_load_dword/s_store_dword instruction addresses.

Definition at line 216 of file op_encodings.hh.

References gem5::X86ISA::addr, gem5::ArmISA::offset, and gem5::MipsISA::vaddr.

◆ generateDisassembly()

void gem5::VegaISA::Inst_SMEM::generateDisassembly ( )

overridevirtual

Reimplemented from gem5::VegaISA::VEGAGPUStaticInst.

Definition at line 554 of file op_encodings.cc.

References gem5::GPUStaticInst::_opcode, gem5::GPUStaticInst::disassembly, extData, gem5::GPUStaticInst::getNumOperands(), gem5::VegaISA::VEGAGPUStaticInst::getOperandSize(), gem5::VegaISA::InFmt_SMEM::IMM, instData, gem5::GPUStaticInst::numDstRegOperands(), gem5::VegaISA::InFmt_SMEM_1::OFFSET, gem5::VegaISA::InFmt_SMEM::SBASE, and gem5::VegaISA::InFmt_SMEM::SDATA.

◆ initMemRead()

template<int N>

void gem5::VegaISA::Inst_SMEM::initMemRead ( GPUDynInstPtr gpuDynInst )

inlineprotected

initiate a memory read access for N dwords

Definition at line 195 of file op_encodings.hh.

References gem5::MemCmd::ReadReq.

◆ initMemWrite()

template<int N>

void gem5::VegaISA::Inst_SMEM::initMemWrite ( GPUDynInstPtr gpuDynInst )

inlineprotected

initiate a memory write access for N dwords

Definition at line 206 of file op_encodings.hh.

References gem5::MemCmd::WriteReq.

◆ initOperandInfo()

void gem5::VegaISA::Inst_SMEM::initOperandInfo ( )

overridevirtual

Reimplemented from gem5::VegaISA::VEGAGPUStaticInst.

Definition at line 502 of file op_encodings.cc.

References gem5::GPUStaticInst::dstOps, extData, gem5::GPUStaticInst::getNumOperands(), gem5::VegaISA::VEGAGPUStaticInst::getOperandSize(), gem5::VegaISA::InFmt_SMEM::IMM, instData, gem5::VegaISA::isScalarReg(), gem5::GPUStaticInst::numDstRegOperands(), gem5::GPUStaticInst::numSrcRegOperands(), gem5::VegaISA::InFmt_SMEM_1::OFFSET, gem5::X86ISA::reg, gem5::VegaISA::InFmt_SMEM::SBASE, gem5::VegaISA::InFmt_SMEM::SDATA, and gem5::GPUStaticInst::srcOps.

◆ instSize()

int gem5::VegaISA::Inst_SMEM::instSize ( ) const

overridevirtual

Implements gem5::GPUStaticInst.

Definition at line 548 of file op_encodings.cc.

Member Data Documentation

◆ extData

InFmt_SMEM_1 gem5::VegaISA::Inst_SMEM::extData

protected

Definition at line 256 of file op_encodings.hh.

◆ instData

InFmt_SMEM gem5::VegaISA::Inst_SMEM::instData

protected

Definition at line 254 of file op_encodings.hh.

The documentation for this class was generated from the following files:

arch/amdgpu/vega/insts/op_encodings.hh
arch/amdgpu/vega/insts/op_encodings.cc

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ Inst_SMEM()

◆ ~Inst_SMEM()

Member Function Documentation

◆ calcAddr() [1/2]

◆ calcAddr() [2/2]

◆ generateDisassembly()

◆ initMemRead()

◆ initMemWrite()

◆ initOperandInfo()

◆ instSize()

Member Data Documentation

◆ extData

◆ instData