#include <faults.hh>
Public Member Functions | |
| InitInterrupt (uint8_t _vector) | |
| void | invoke (ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override |
 Public Member Functions inherited from gem5::X86ISA::X86FaultBase | |
| virtual uint8_t | getVector () const |
| Get the vector of an interrupt. More... | |
| Public Member Functions inherited from gem5::FaultBase | |
| virtual | ~FaultBase () |
Additional Inherited Members | |
| Protected Member Functions inherited from gem5::X86ISA::X86Interrupt | |
| X86FaultBase (const char *_faultName, const char *_mnem, const uint8_t _vector, uint64_t _errorCode=(uint64_t) -1) | |
| Protected Member Functions inherited from gem5::X86ISA::X86FaultBase | |
| X86FaultBase (const char *_faultName, const char *_mnem, const uint8_t _vector, uint64_t _errorCode=(uint64_t) -1) | |
| const char * | name () const override |
| virtual bool | isBenign () |
| virtual const char * | mnemonic () const |
| virtual bool | isSoft () |
| virtual std::string | describe () const |
| Protected Attributes inherited from gem5::X86ISA::X86FaultBase | |
| const char * | faultName |
| const char * | mnem |
| uint8_t | vector |
| uint64_t | errorCode |
Detailed Description
Constructor & Destructor Documentation
◆ InitInterrupt()
|
inline |
Member Function Documentation
◆ invoke()
|
overridevirtual |
Reimplemented from gem5::X86ISA::X86FaultBase.
Definition at line 187 of file faults.cc.
References DPRINTF, gem5::X86ISA::index, gem5::X86ISA::MISCREG_CR0, gem5::X86ISA::MISCREG_CR2, gem5::X86ISA::MISCREG_CR3, gem5::X86ISA::MISCREG_CR4, gem5::X86ISA::MISCREG_CS, gem5::X86ISA::MISCREG_CS_ATTR, gem5::X86ISA::MISCREG_CS_BASE, gem5::X86ISA::MISCREG_CS_EFF_BASE, gem5::X86ISA::MISCREG_CS_LIMIT, gem5::X86ISA::MISCREG_DR0, gem5::X86ISA::MISCREG_DR1, gem5::X86ISA::MISCREG_DR2, gem5::X86ISA::MISCREG_DR3, gem5::X86ISA::MISCREG_DR6, gem5::X86ISA::MISCREG_DR7, gem5::X86ISA::MISCREG_EFER, gem5::X86ISA::MISCREG_FTW, gem5::X86ISA::MISCREG_IDTR_BASE, gem5::X86ISA::MISCREG_IDTR_LIMIT, gem5::X86ISA::MISCREG_M5_REG, gem5::X86ISA::MISCREG_MXCSR, gem5::X86ISA::MISCREG_RFLAGS, gem5::X86ISA::MISCREG_SEG_ATTR(), gem5::X86ISA::MISCREG_SEG_BASE(), gem5::X86ISA::MISCREG_SEG_EFF_BASE(), gem5::X86ISA::MISCREG_SEG_LIMIT(), gem5::X86ISA::MISCREG_SEG_SEL(), gem5::X86ISA::MISCREG_TR, gem5::X86ISA::MISCREG_TR_ATTR, gem5::X86ISA::MISCREG_TR_BASE, gem5::X86ISA::MISCREG_TR_LIMIT, gem5::X86ISA::MISCREG_TSG_BASE, gem5::X86ISA::MISCREG_TSG_LIMIT, gem5::X86ISA::MISCREG_TSL, gem5::X86ISA::MISCREG_TSL_ATTR, gem5::X86ISA::MISCREG_TSL_BASE, gem5::X86ISA::MISCREG_TSL_LIMIT, gem5::X86ISA::NUM_SEGMENTREGS, gem5::X86ISA::pc, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscReg(), gem5::romMicroPC(), gem5::X86ISA::seg, gem5::ThreadContext::setIntReg(), and gem5::ThreadContext::setMiscReg().
Referenced by gem5::X86ISA::FsWorkload::initState().
The documentation for this class was generated from the following files: