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gem5
v21.1.0.2
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#include <lsq.hh>
Public Member Functions | |
| SplitDataRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr) | |
| virtual | ~SplitDataRequest () |
| virtual void | finish (const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode) |
| virtual bool | recvTimingResp (PacketPtr pkt) |
| virtual void | initiateTranslation () |
| virtual void | sendPacketToCache () |
| virtual void | buildPackets () |
| virtual Cycles | handleLocalAccess (gem5::ThreadContext *thread, PacketPtr pkt) |
| Memory mapped IPR accesses. More... | |
| virtual bool | isCacheBlockHit (Addr blockAddr, Addr cacheBlockMask) |
| Caches may probe into the load-store queue to enforce memory ordering guarantees. More... | |
| virtual RequestPtr | mainRequest () |
| virtual PacketPtr | mainPacket () |
| virtual std::string | name () const |
Public Member Functions inherited from gem5::o3::LSQ::LSQRequest | |
| void | packetSent () |
| Update the status to reflect that a packet was sent. More... | |
| void | packetNotSent () |
| Update the status to reflect that a packet was not sent. More... | |
| void | sendFragmentToTranslation (int i) |
| bool | isComplete () |
| bool | isInTranslation () |
| bool | isTranslationComplete () |
| bool | isTranslationBlocked () |
| bool | isSent () |
| bool | isPartialFault () |
| bool | isMemAccessRequired () |
| void | setStateToFault () |
| void | freeLSQEntry () |
| The LSQ entry is cleared. More... | |
| void | discard () |
| The request is discarded (e.g. More... | |
| void | packetReplied () |
| void | writebackScheduled () |
| void | writebackDone () |
| void | squashTranslation () |
| void | complete () |
| void | setContext (const ContextID &context_id) |
| Convenience getters/setters. More... | |
| const DynInstPtr & | instruction () |
| void | setVirt (Addr vaddr, unsigned size, Request::Flags flags_, RequestorID requestor_id, Addr pc) |
| Set up virtual request. More... | |
| void | taskId (const uint32_t &v) |
| uint32_t | taskId () const |
| RequestPtr | request (int idx=0) |
| const RequestPtr | request (int idx=0) const |
| Addr | getVaddr (int idx=0) const |
| PacketPtr | packet (int idx=0) |
| void | senderState (LSQSenderState *st) |
| const LSQSenderState * | senderState () const |
| void | discardSenderState () |
| Mark senderState as discarded. More... | |
| bool | isAnyOutstandingRequest () |
| Test if there is any in-flight translation or mem access request. More... | |
| bool | isSplit () const |
Public Member Functions inherited from gem5::BaseMMU::Translation | |
| virtual | ~Translation () |
Protected Types | |
| using | Flag = LSQRequest::Flag |
| using | State = LSQRequest::State |
Protected Types inherited from gem5::o3::LSQ::LSQRequest | |
| enum | Flag : FlagsStorage { IsLoad = 0x00000001, WbStore = 0x00000002, Delayed = 0x00000004, IsSplit = 0x00000008, TranslationStarted = 0x00000010, TranslationFinished = 0x00000020, Sent = 0x00000040, Retry = 0x00000080, Complete = 0x00000100, TranslationSquashed = 0x00000200, Discarded = 0x00000400, LSQEntryFreed = 0x00000800, WritebackScheduled = 0x00001000, WritebackDone = 0x00002000, IsAtomic = 0x00004000 } |
| enum | State { State::NotIssued, State::Translation, State::Request, State::Fault, State::PartialFault } |
| typedef uint32_t | FlagsStorage |
| typedef Flags< FlagsStorage > | FlagsType |
Protected Member Functions | |
| bool | isLoad () const |
| bool | isTranslationComplete () |
| LSQUnit * | lsqUnit () |
| RequestPtr | request (int idx=0) |
| const RequestPtr | request (int idx=0) const |
| void | sendFragmentToTranslation (int i) |
| void | setState (const State &newState) |
Protected Member Functions inherited from gem5::o3::LSQ::LSQRequest | |
| void | setState (const State &newState) |
| void | markDelayed () override |
| Signal that the translation has been delayed due to a hw page table walk. More... | |
| bool | isDelayed () |
| LSQUnit * | lsqUnit () |
| LSQRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad) | |
| LSQRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr) | |
| bool | isLoad () const |
| bool | isAtomic () const |
| void | install () |
| Install the request in the LQ/SQ. More... | |
| bool | squashed () const override |
| This function is used by the page table walker to determine if it should translate the a pending request or if the underlying request has been squashed. More... | |
| bool | isReleased () |
| Test if the LSQRequest has been released, i.e. More... | |
| void | release (Flag reason) |
| Release the LSQRequest. More... | |
| void | addRequest (Addr addr, unsigned size, const std::vector< bool > &byte_enable) |
Helper function used to add a (sub)request, given its address addr, size size and byte-enable mask byteEnable. More... | |
| virtual | ~LSQRequest () |
| Destructor. More... | |
Protected Attributes | |
| uint32_t | numFragments |
| uint32_t | numReceivedPackets |
| RequestPtr | mainReq |
| PacketPtr | _mainPacket |
| const Addr | _addr |
| PacketDataPtr | _data |
| std::vector< Fault > | _fault |
| const Request::Flags | _flags |
| const DynInstPtr | _inst |
| std::vector< PacketPtr > | _packets |
| LSQUnit & | _port |
| std::vector< RequestPtr > | _requests |
| uint64_t * | _res |
| std::vector< bool > | _byteEnable |
| LSQSenderState * | _senderState |
| const uint32_t | _size |
| State | _state |
| uint32_t | _taskId |
| FlagsType | flags |
| uint32_t | numInTranslationFragments |
| uint32_t | numTranslatedFragments |
| uint32_t | _numOutstandingPackets |
Protected Attributes inherited from gem5::o3::LSQ::LSQRequest | |
| FlagsType | flags |
| State | _state |
| LSQSenderState * | _senderState |
| uint32_t | numTranslatedFragments |
| uint32_t | numInTranslationFragments |
| uint32_t | _entryIdx |
| LQ/SQ entry idx. More... | |
Additional Inherited Members | |
Public Attributes inherited from gem5::o3::LSQ::LSQRequest | |
| LSQUnit & | _port |
| const DynInstPtr | _inst |
| uint32_t | _taskId |
| PacketDataPtr | _data |
| std::vector< PacketPtr > | _packets |
| std::vector< RequestPtr > | _requests |
| std::vector< Fault > | _fault |
| uint64_t * | _res |
| const Addr | _addr |
| const uint32_t | _size |
| const Request::Flags | _flags |
| std::vector< bool > | _byteEnable |
| uint32_t | _numOutstandingPackets |
| AtomicOpFunctorPtr | _amo_op |
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Definition at line 747 of file lsq.hh.
References gem5::o3::LSQ::LSQRequest::flags, and gem5::Flags< T >::set().
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Definition at line 760 of file lsq.hh.
References _mainPacket, and mainReq.
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Implements gem5::o3::LSQ::LSQRequest.
Definition at line 1196 of file lsq.cc.
References gem5::Packet::createRead(), gem5::Packet::createWrite(), gem5::Packet::dataDynamic(), gem5::Packet::dataStatic(), DPRINTF, gem5::ArmISA::i, gem5::NoFault, gem5::ArmISA::offset, gem5::MipsISA::r, and gem5::Packet::senderState.
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Implements gem5::BaseMMU::Translation.
Definition at line 893 of file lsq.cc.
References gem5::ArmISA::i, and gem5::NoFault.
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Memory mapped IPR accesses.
Implements gem5::o3::LSQ::LSQRequest.
Definition at line 1287 of file lsq.cc.
References gem5::ArmISA::d, gem5::Packet::dataStatic(), gem5::Packet::getPtr(), gem5::ArmISA::offset, gem5::MipsISA::r, gem5::MemCmd::ReadReq, gem5::o3::LSQ::thread, and gem5::MemCmd::WriteReq.
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Implements gem5::o3::LSQ::LSQRequest.
Definition at line 974 of file lsq.cc.
References gem5::addrBlockAlign(), gem5::ArmISA::i, and gem5::MipsISA::r.
Caches may probe into the load-store queue to enforce memory ordering guarantees.
This method supports probes by providing a mechanism to compare snoop messages with requests tracked by the load-store queue.
Consistency models must enforce ordering constraints. TSO, for instance, must prevent memory reorderings except stores which are reordered after loads. The reordering restrictions negatively impact performance by cutting down on memory level parallelism. However, the core can regain performance by generating speculative loads. Speculative loads may issue without affecting correctness if precautions are taken to handle invalid memory orders. The load queue must squash under memory model violations. Memory model violations may occur when block ownership is granted to another core or the block cannot be accurately monitored by the load queue.
The load-store queue handles partial faults which complicates this method. Physical addresses must be compared between requests and snoops. Some requests will not have a valid physical address, since partial faults may have outstanding translations. Therefore, the existence of a valid request address must be checked before comparing block hits. We assume no pipeline squash is needed if a valid request address does not exist.
Implements gem5::o3::LSQ::LSQRequest.
Definition at line 1328 of file lsq.cc.
References gem5::MipsISA::r.
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Reimplemented from gem5::o3::LSQ::LSQRequest.
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Reimplemented from gem5::o3::LSQ::LSQRequest.
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Reimplemented from gem5::o3::LSQ::LSQRequest.
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Implements gem5::o3::LSQ::LSQRequest.
Definition at line 1136 of file lsq.cc.
References gem5::Complete, gem5::Packet::createRead(), gem5::Packet::createWrite(), gem5::Packet::dataStatic(), and gem5::Packet::senderState.
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Implements gem5::o3::LSQ::LSQRequest.
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Definition at line 744 of file lsq.hh.
Referenced by ~SplitDataRequest().
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Definition at line 743 of file lsq.hh.
Referenced by ~SplitDataRequest().
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