vecregs.hh

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/*
 * Copyright (c) 2009 The University of Edinburgh
 * Copyright (c) 2021 IBM Corporation
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_POWER_VECREGS_HH__
#define __ARCH_POWER_VECREGS_HH__
 
#include <cstdint>
 
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
 
namespace gem5
{
 
namespace PowerISA
{
 
// Not applicable to Power
using VecElem = ::gem5::DummyVecElem;
using VecRegContainer = ::gem5::DummyVecRegContainer;
constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
 
// Not applicable to Power
using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
} // namespace PowerISA
} // namespace gem5
 
#endif // __ARCH_POWER_VECREGS_HH__