register_manager_policy.hh

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/*
 * Copyright (c) 2016 Advanced Micro Devices, Inc.
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 * For use for simulation and test purposes only
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#ifndef __REGISTER_MANAGER_POLICY_HH__
#define __REGISTER_MANAGER_POLICY_HH__
 
#include <cstdint>
 
namespace gem5
{
 
class ComputeUnit;
class HSAQueueEntry;
class Wavefront;
 
class RegisterManagerPolicy
{
  public:
    virtual void setParent(ComputeUnit *_cu) { cu = _cu; }
 
    // Execute: called by RenameStage::execute()
    virtual void exec() = 0;
 
    // provide virtual to physical register mapping
    virtual int mapVgpr(Wavefront* w, int vgprIndex) = 0;
    virtual int mapSgpr(Wavefront* w, int sgprIndex) = 0;
 
    // check if requested number of vector registers can be allocated
    virtual bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf) = 0;
    // check if requested number of scalar registers can be allocated
    // machine ISA only
    virtual bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf) = 0;
 
    // allocate vector registers and reserve from register pool
    virtual void allocateRegisters(Wavefront *w, int vectorDemand,
        int scalarDemand) = 0;
 
    // free all remaining registers held by specified WF
    virtual void freeRegisters(Wavefront *w) = 0;
 
  protected:
    ComputeUnit *cu;
};
 
} // namespace gem5
 
#endif // __REGISTER_MANAGER_POLICY_HH__