#include <gpu_registers.hh>
Definition at line 183 of file gpu_registers.hh.
◆ StatusReg() [1/2]
| gem5::Gcn3ISA::StatusReg::StatusReg |
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inline |
◆ StatusReg() [2/2]
| gem5::Gcn3ISA::StatusReg::StatusReg |
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inline |
◆ ALLOW_REPLAY
| uint32_t gem5::Gcn3ISA::StatusReg::ALLOW_REPLAY |
◆ COND_DBG_SYS
| uint32_t gem5::Gcn3ISA::StatusReg::COND_DBG_SYS |
◆ COND_DBG_USER
| uint32_t gem5::Gcn3ISA::StatusReg::COND_DBG_USER |
◆ ECC_ERR
| uint32_t gem5::Gcn3ISA::StatusReg::ECC_ERR |
◆ EXECZ
| uint32_t gem5::Gcn3ISA::StatusReg::EXECZ |
◆ EXPORT_RDY
| uint32_t gem5::Gcn3ISA::StatusReg::EXPORT_RDY |
◆ HALT
| uint32_t gem5::Gcn3ISA::StatusReg::HALT |
◆ IN_BARRIER
| uint32_t gem5::Gcn3ISA::StatusReg::IN_BARRIER |
◆ IN_TG
| uint32_t gem5::Gcn3ISA::StatusReg::IN_TG |
◆ INSTRUCTION_ATC
| uint32_t gem5::Gcn3ISA::StatusReg::INSTRUCTION_ATC |
◆ MUST_EXPORT
| uint32_t gem5::Gcn3ISA::StatusReg::MUST_EXPORT |
◆ PERF_EN
| uint32_t gem5::Gcn3ISA::StatusReg::PERF_EN |
◆ PRIV
| uint32_t gem5::Gcn3ISA::StatusReg::PRIV |
◆ RESERVED
| uint32_t gem5::Gcn3ISA::StatusReg::RESERVED |
◆ RESERVED_1
| uint32_t gem5::Gcn3ISA::StatusReg::RESERVED_1 |
◆ SCC
| uint32_t gem5::Gcn3ISA::StatusReg::SCC |
◆ SKIP_EXPORT
| uint32_t gem5::Gcn3ISA::StatusReg::SKIP_EXPORT |
◆ SPI_PRIO
| uint32_t gem5::Gcn3ISA::StatusReg::SPI_PRIO |
◆ TRAP
| uint32_t gem5::Gcn3ISA::StatusReg::TRAP |
◆ TRAP_EN
| uint32_t gem5::Gcn3ISA::StatusReg::TRAP_EN |
◆ TTRACE_CU_EN
| uint32_t gem5::Gcn3ISA::StatusReg::TTRACE_CU_EN |
◆ TTRACE_EN
| uint32_t gem5::Gcn3ISA::StatusReg::TTRACE_EN |
◆ USER_PRIO
| uint32_t gem5::Gcn3ISA::StatusReg::USER_PRIO |
◆ VALID
| uint32_t gem5::Gcn3ISA::StatusReg::VALID |
◆ VCCZ
| uint32_t gem5::Gcn3ISA::StatusReg::VCCZ |
The documentation for this struct was generated from the following files: