gem5::VegaISA::InFmt_SOPK Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SIMM16: 16
unsigned int	SDST: 7
unsigned int	OP: 5
unsigned int	ENCODING: 4

Detailed Description

Definition at line 1765 of file gpu_decoder.hh.

Member Data Documentation

ENCODING

unsigned int gem5::VegaISA::InFmt_SOPK::ENCODING

Definition at line 1769 of file gpu_decoder.hh.

OP

unsigned int gem5::VegaISA::InFmt_SOPK::OP

Definition at line 1768 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOPK::generateDisassembly(), and gem5::VegaISA::Inst_SOPK::hasSecondDword().

SDST

unsigned int gem5::VegaISA::InFmt_SOPK::SDST

Definition at line 1767 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOPK__S_MOVK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMOVK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LG_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GT_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GE_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LT_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LE_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LG_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GT_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GE_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LT_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LE_U32::execute(), gem5::VegaISA::Inst_SOPK__S_ADDK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_MULK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_B32::execute(), gem5::VegaISA::Inst_SOPK::generateDisassembly(), and gem5::VegaISA::Inst_SOPK::initOperandInfo().

SIMM16

unsigned int gem5::VegaISA::InFmt_SOPK::SIMM16

Definition at line 1766 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOPK__S_MOVK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMOVK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LG_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GT_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GE_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LT_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LE_I32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LG_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GT_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_GE_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LT_U32::execute(), gem5::VegaISA::Inst_SOPK__S_CMPK_LE_U32::execute(), gem5::VegaISA::Inst_SOPK__S_ADDK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_MULK_I32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_B32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32::execute(), gem5::VegaISA::Inst_SOPK::generateDisassembly(), and gem5::VegaISA::Inst_SOPK::initOperandInfo().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh