static_inst.cc

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/*
 * Copyright (c) 2009 The University of Edinburgh
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#include "arch/power/insts/static_inst.hh"
 
#include "cpu/reg_class.hh"
 
namespace gem5
{
 
using namespace PowerISA;
 
void
PowerStaticInst::printReg(std::ostream &os, RegId reg) const
{
    switch (reg.classValue()) {
      case IntRegClass:
        ccprintf(os, "r%d", reg.index());
        break;
      case FloatRegClass:
        ccprintf(os, "f%d", reg.index());
        break;
      case MiscRegClass:
        switch (reg.index()) {
          case 0: ccprintf(os, "cr"); break;
          case 1: ccprintf(os, "xer"); break;
          case 2: ccprintf(os, "lr"); break;
          case 3: ccprintf(os, "ctr"); break;
          default: ccprintf(os, "unknown_reg");
            break;
        }
        break;
      default:
        panic("printReg: Unrecognized register class.");
    }
}
 
std::string
PowerStaticInst::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
 
    ccprintf(ss, "%-10s ", mnemonic);
 
    return ss.str();
}
 
} // namespace gem5