thread_context.hh

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 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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#ifndef __CPU_O3_THREAD_CONTEXT_HH__
#define __CPU_O3_THREAD_CONTEXT_HH__
 
#include "config/the_isa.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/thread_context.hh"
 
namespace gem5
{
 
namespace o3
{
 
class ThreadContext : public gem5::ThreadContext
{
  public:
    CPU *cpu;
 
    bool
    schedule(PCEvent *e) override
    {
        return thread->pcEventQueue.schedule(e);
    }
    bool
    remove(PCEvent *e) override
    {
        return thread->pcEventQueue.remove(e);
    }
 
    void
    scheduleInstCountEvent(Event *event, Tick count) override
    {
        thread->comInstEventQueue.schedule(event, count);
    }
    void
    descheduleInstCountEvent(Event *event) override
    {
        thread->comInstEventQueue.deschedule(event);
    }
    Tick
    getCurrentInstCount() override
    {
        return thread->comInstEventQueue.getCurTick();
    }
 
    ThreadState *thread;
 
    BaseMMU *getMMUPtr() override { return cpu->mmu; }
 
    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
 
    BaseISA *
    getIsaPtr() override
    {
        return cpu->isa[thread->threadId()];
    }
 
    InstDecoder *
    getDecoderPtr() override
    {
        return cpu->fetch.decoder[thread->threadId()];
    }
 
    BaseCPU *getCpuPtr() override { return cpu; }
 
    int cpuId() const override { return cpu->cpuId(); }
 
    uint32_t socketId() const override { return cpu->socketId(); }
 
    ContextID contextId() const override { return thread->contextId(); }
 
    void setContextId(ContextID id) override { thread->setContextId(id); }
 
    int threadId() const override { return thread->threadId(); }
    void setThreadId(int id) override { return thread->setThreadId(id); }
 
    System *getSystemPtr() override { return cpu->system; }
 
    Process *getProcessPtr() override { return thread->getProcessPtr(); }
 
    void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
 
    Status status() const override { return thread->status(); }
 
    void
    setStatus(Status new_status) override
    {
        thread->setStatus(new_status);
    }
 
    void activate() override;
 
    void suspend() override;
 
    void halt() override;
 
    void takeOverFrom(gem5::ThreadContext *old_context) override;
 
    Tick readLastActivate() override;
    Tick readLastSuspend() override;
 
    void copyArchRegs(gem5::ThreadContext *tc) override;
 
    void clearArchRegs() override;
 
    RegVal
    readReg(RegIndex reg_idx)
    {
        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                 reg_idx)).index());
    }
    RegVal
    readIntReg(RegIndex reg_idx) const override
    {
        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                 reg_idx)).index());
    }
 
    RegVal
    readFloatReg(RegIndex reg_idx) const override
    {
        return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                             reg_idx)).index());
    }
 
    const TheISA::VecRegContainer &
    readVecReg(const RegId& id) const override
    {
        return readVecRegFlat(flattenRegId(id).index());
    }
 
    TheISA::VecRegContainer &
    getWritableVecReg(const RegId& id) override
    {
        return getWritableVecRegFlat(flattenRegId(id).index());
    }
 
    RegVal
    readVecElem(const RegId& reg) const override
    {
        return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
    }
 
    const TheISA::VecPredRegContainer &
    readVecPredReg(const RegId& id) const override
    {
        return readVecPredRegFlat(flattenRegId(id).index());
    }
 
    TheISA::VecPredRegContainer&
    getWritableVecPredReg(const RegId& id) override
    {
        return getWritableVecPredRegFlat(flattenRegId(id).index());
    }
 
    RegVal
    readCCReg(RegIndex reg_idx) const override
    {
        return readCCRegFlat(flattenRegId(RegId(CCRegClass,
                                                 reg_idx)).index());
    }
 
    void
    setIntReg(RegIndex reg_idx, RegVal val) override
    {
        setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
    }
 
    void
    setFloatReg(RegIndex reg_idx, RegVal val) override
    {
        setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
                                           reg_idx)).index(), val);
    }
 
    void
    setVecReg(const RegId& reg, const TheISA::VecRegContainer& val) override
    {
        setVecRegFlat(flattenRegId(reg).index(), val);
    }
 
    void
    setVecElem(const RegId& reg, RegVal val) override
    {
        setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
    }
 
    void
    setVecPredReg(const RegId& reg,
                  const TheISA::VecPredRegContainer& val) override
    {
        setVecPredRegFlat(flattenRegId(reg).index(), val);
    }
 
    void
    setCCReg(RegIndex reg_idx, RegVal val) override
    {
        setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
    }
 
    const PCStateBase &
    pcState() const override
    {
        return cpu->pcState(thread->threadId());
    }
 
    void pcState(const PCStateBase &val) override;
 
    void pcStateNoRecord(const PCStateBase &val) override;
 
    RegVal
    readMiscRegNoEffect(RegIndex misc_reg) const override
    {
        return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
    }
 
    RegVal
    readMiscReg(RegIndex misc_reg) override
    {
        return cpu->readMiscReg(misc_reg, thread->threadId());
    }
 
    void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
 
    void setMiscReg(RegIndex misc_reg, RegVal val) override;
 
    RegId flattenRegId(const RegId& regId) const override;
 
    // @todo: Figure out where these store cond failures should go.
    unsigned
    readStCondFailures() const override
    {
        return thread->storeCondFailures;
    }
 
    void
    setStCondFailures(unsigned sc_failures) override
    {
        thread->storeCondFailures = sc_failures;
    }
 
    void
    conditionalSquash()
    {
        if (!thread->trapPending && !thread->noSquashFromTC)
            cpu->squashFromTC(thread->threadId());
    }
 
    RegVal readIntRegFlat(RegIndex idx) const override;
    void setIntRegFlat(RegIndex idx, RegVal val) override;
 
    RegVal readFloatRegFlat(RegIndex idx) const override;
    void setFloatRegFlat(RegIndex idx, RegVal val) override;
 
    const TheISA::VecRegContainer& readVecRegFlat(RegIndex idx) const override;
    TheISA::VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
    void setVecRegFlat(RegIndex idx,
            const TheISA::VecRegContainer& val) override;
 
    RegVal readVecElemFlat(RegIndex idx,
            const ElemIndex& elemIndex) const override;
    void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
                        RegVal val) override;
 
    const TheISA::VecPredRegContainer&
        readVecPredRegFlat(RegIndex idx) const override;
    TheISA::VecPredRegContainer&
        getWritableVecPredRegFlat(RegIndex idx) override;
    void setVecPredRegFlat(RegIndex idx,
                           const TheISA::VecPredRegContainer& val) override;
 
    RegVal readCCRegFlat(RegIndex idx) const override;
    void setCCRegFlat(RegIndex idx, RegVal val) override;
 
    // hardware transactional memory
    void htmAbortTransaction(uint64_t htm_uid,
                             HtmFailureFaultCause cause) override;
    BaseHTMCheckpointPtr& getHtmCheckpointPtr() override;
    void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
};
 
} // namespace o3
} // namespace gem5
 
#endif