gem5::X86ISA::GpuTLB::TranslationState Struct Reference

TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back. More...

#include <tlb.hh>

Inheritance diagram for gem5::X86ISA::GpuTLB::TranslationState:

Public Member Functions
	TranslationState (Mode tlb_mode, ThreadContext *_tc, bool is_prefetch=false, Packet::SenderState *_saved=nullptr)
Public Member Functions inherited from gem5::Packet::SenderState
	SenderState ()
virtual	~SenderState ()

Public Attributes
Mode	tlbMode
ThreadContext *	tc
TlbEntry *	tlbEntry
bool	isPrefetch
uint64_t	issueTime
std::vector< ResponsePort * >	ports
std::vector< int >	reqCnt
int	hitLevel
Packet::SenderState *	saved
Public Attributes inherited from gem5::Packet::SenderState
SenderState *	predecessor

Detailed Description

TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back.

However, since there is state that we want to pass to the TLBs using the send/recv Timing/Functional/etc. APIs, which don't allow for new arguments, we need a common TLB senderState to pass between TLBs, both "forwards" and "backwards."

So, basically, the rule is that any packet received by a TLB port (cpuside OR memside) must be safely castable to a TranslationState.

Definition at line 283 of file tlb.hh.

Constructor & Destructor Documentation

TranslationState()

gem5::X86ISA::GpuTLB::TranslationState::TranslationState ( Mode  tlb_mode, ThreadContext *  _tc, bool  is_prefetch = false, Packet::SenderState *  _saved = nullptr  )

inline

Definition at line 310 of file tlb.hh.

Member Data Documentation

hitLevel

int gem5::X86ISA::GpuTLB::TranslationState::hitLevel

Definition at line 307 of file tlb.hh.

Referenced by gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::sendRequest(), and gem5::TLBCoalescer::updatePhysAddresses().

isPrefetch

bool gem5::X86ISA::GpuTLB::TranslationState::isPrefetch

Definition at line 297 of file tlb.hh.

Referenced by gem5::TLBCoalescer::canCoalesce(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::TLBCoalescer::CpuSidePort::recvFunctional(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::X86ISA::GpuTLB::translationReturn(), and gem5::TLBCoalescer::updatePhysAddresses().

issueTime

uint64_t gem5::X86ISA::GpuTLB::TranslationState::issueTime

Definition at line 299 of file tlb.hh.

Referenced by gem5::TLBCoalescer::CpuSidePort::recvTimingReq().

ports

std::vector<ResponsePort*> gem5::X86ISA::GpuTLB::TranslationState::ports

Definition at line 301 of file tlb.hh.

Referenced by gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), gem5::ComputeUnit::ITLBPort::recvTimingResp(), and gem5::TLBCoalescer::updatePhysAddresses().

reqCnt

std::vector<int> gem5::X86ISA::GpuTLB::TranslationState::reqCnt

Definition at line 305 of file tlb.hh.

Referenced by gem5::TLBCoalescer::canCoalesce(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::X86ISA::GpuTLB::translationReturn(), and gem5::TLBCoalescer::updatePhysAddresses().

saved

Packet::SenderState* gem5::X86ISA::GpuTLB::TranslationState::saved

Definition at line 308 of file tlb.hh.

Referenced by gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), gem5::ComputeUnit::ITLBPort::recvTimingResp(), and gem5::ComputeUnit::sendRequest().

tc

ThreadContext* gem5::X86ISA::GpuTLB::TranslationState::tc

Definition at line 288 of file tlb.hh.

Referenced by gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::X86ISA::GpuTLB::translationReturn(), and gem5::TLBCoalescer::updatePhysAddresses().

tlbEntry

TlbEntry* gem5::X86ISA::GpuTLB::TranslationState::tlbEntry

Definition at line 295 of file tlb.hh.

Referenced by gem5::Shader::functionalTLBAccess(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::FetchUnit::initiateFetch(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), gem5::ComputeUnit::ITLBPort::recvTimingResp(), gem5::ComputeUnit::sendRequest(), gem5::X86ISA::GpuTLB::translationReturn(), and gem5::TLBCoalescer::updatePhysAddresses().

tlbMode

Mode gem5::X86ISA::GpuTLB::TranslationState::tlbMode

Definition at line 286 of file tlb.hh.

Referenced by gem5::TLBCoalescer::canCoalesce(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), and gem5::X86ISA::GpuTLB::translationReturn().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/common/tlb.hh