gem5  v22.0.0.2
decoder.cc
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1 /*
2  * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <vector>
33 
37 
38 namespace gem5
39 {
40 
41 namespace VegaISA
42 {
44  {
45  } // Decoder
46 
48  {
49  } // ~Decoder
50 
51  /*
52  * These will probably have to be updated according to the Vega ISA manual:
53  * https://developer.amd.com/wp-content/resources/
54  * Vega_Shader_ISA_28July2017.pdf
55  */
569  };
570 
1340  };
1341 
1599  };
1600 
1730  };
1731 
1861  };
1862 
1992  };
1993 
2011  };
2012 
2142  };
2143 
2273  };
2274 
2532  };
2533 
2791  };
2792 
2922  };
2923 
3053  };
3054 
3060  };
3061 
3319  };
3320 
3578  };
3579 
3709  };
3710 
3711  GPUStaticInst*
3713  {
3714  InFmt_SOP1 *enc = &mach_inst->iFmt_SOP1;
3716  return (this->*method)(mach_inst);
3717  } // decode
3718 
3719  GPUStaticInst*
3721  {
3722  InFmt_VOPC *enc = &iFmt->iFmt_VOPC;
3723  IsaDecodeMethod method = tableSubDecode_OP_VOPC[enc->OP];
3724  return (this->*method)(iFmt);
3725  } // subDecode_OP_VOPC
3726 
3727  GPUStaticInst*
3729  {
3730  InFmt_VOP3P *enc = &iFmt->iFmt_VOP3P;
3732  return (this->*method)(iFmt);
3733  } // subDecode_OP_VOP3P
3734 
3735  GPUStaticInst*
3737  {
3738  InFmt_VOP1 *enc = &iFmt->iFmt_VOP1;
3739  IsaDecodeMethod method = tableSubDecode_OP_VOP1[enc->OP];
3740  return (this->*method)(iFmt);
3741  } // subDecode_OP_VOP1
3742 
3743  GPUStaticInst*
3745  {
3746  InFmt_SOP1 *enc = &iFmt->iFmt_SOP1;
3747  IsaDecodeMethod method = tableSubDecode_OP_SOP1[enc->OP];
3748  return (this->*method)(iFmt);
3749  } // subDecode_OP_SOP1
3750 
3751  GPUStaticInst*
3753  {
3754  InFmt_SOPC *enc = &iFmt->iFmt_SOPC;
3755  IsaDecodeMethod method = tableSubDecode_OP_SOPC[enc->OP];
3756  return (this->*method)(iFmt);
3757  } // subDecode_OP_SOPC
3758 
3759  GPUStaticInst*
3761  {
3762  InFmt_SOPP *enc = &iFmt->iFmt_SOPP;
3763  IsaDecodeMethod method = tableSubDecode_OP_SOPP[enc->OP];
3764  return (this->*method)(iFmt);
3765  } // subDecode_OP_SOPP
3766 
3767  GPUStaticInst*
3769  {
3770  InFmt_SMEM *enc = &iFmt->iFmt_SMEM;
3771  IsaDecodeMethod method = tableSubDecode_OP_SMEM[enc->OP];
3772  return (this->*method)(iFmt);
3773  } // subDecode_OP_SMEM
3774 
3775  GPUStaticInst*
3777  {
3778  InFmt_VOP3A *enc = &iFmt->iFmt_VOP3A;
3780  return (this->*method)(iFmt);
3781  } // subDecode_OPU_VOP3
3782 
3783  GPUStaticInst*
3785  {
3786  InFmt_VINTRP *enc = &iFmt->iFmt_VINTRP;
3788  return (this->*method)(iFmt);
3789  } // subDecode_OP_VINTRP
3790 
3791  GPUStaticInst*
3793  {
3794  InFmt_DS *enc = &iFmt->iFmt_DS;
3795  IsaDecodeMethod method = tableSubDecode_OP_DS[enc->OP];
3796  return (this->*method)(iFmt);
3797  } // subDecode_OP_DS
3798 
3799  GPUStaticInst*
3801  {
3802  InFmt_FLAT *enc = &iFmt->iFmt_FLAT;
3803  IsaDecodeMethod method;
3804  switch (enc->SEG) {
3805  case 0:
3806  method = tableSubDecode_OP_FLAT[enc->OP];
3807  break;
3808  case 1:
3809  method = tableSubDecode_OP_SCRATCH[enc->OP];
3810  break;
3811  case 2:
3812  method = tableSubDecode_OP_GLOBAL[enc->OP];
3813  break;
3814  default:
3815  fatal("Invalid SEG for FLAT encoding: %d\n", enc->SEG);
3816  }
3817  return (this->*method)(iFmt);
3818  } // subDecode_OP_FLAT
3819 
3820  GPUStaticInst*
3822  {
3823  InFmt_MUBUF *enc = &iFmt->iFmt_MUBUF;
3825  return (this->*method)(iFmt);
3826  } // subDecode_OP_MUBUF
3827 
3828  GPUStaticInst*
3830  {
3831  InFmt_MTBUF *enc = &iFmt->iFmt_MTBUF;
3833  return (this->*method)(iFmt);
3834  } // subDecode_OP_MTBUF
3835 
3836  GPUStaticInst*
3838  {
3839  InFmt_MIMG *enc = &iFmt->iFmt_MIMG;
3840  IsaDecodeMethod method = tableSubDecode_OP_MIMG[enc->OP];
3841  return (this->*method)(iFmt);
3842  } // subDecode_OP_MIMG
3843 
3844  GPUStaticInst*
3846  {
3847  return new Inst_VOP2__V_CNDMASK_B32(&iFmt->iFmt_VOP2);
3848  } // decode_OP_VOP2__V_CNDMASK_B32
3849 
3850  GPUStaticInst*
3852  {
3853  return new Inst_VOP2__V_ADD_F32(&iFmt->iFmt_VOP2);
3854  } // decode_OP_VOP2__V_ADD_F32
3855 
3856  GPUStaticInst*
3858  {
3859  return new Inst_VOP2__V_SUB_F32(&iFmt->iFmt_VOP2);
3860  } // decode_OP_VOP2__V_SUB_F32
3861 
3862  GPUStaticInst*
3864  {
3865  return new Inst_VOP2__V_SUBREV_F32(&iFmt->iFmt_VOP2);
3866  } // decode_OP_VOP2__V_SUBREV_F32
3867 
3868  GPUStaticInst*
3870  {
3871  return new Inst_VOP2__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP2);
3872  } // decode_OP_VOP2__V_MUL_LEGACY_F32
3873 
3874  GPUStaticInst*
3876  {
3877  return new Inst_VOP2__V_MUL_F32(&iFmt->iFmt_VOP2);
3878  } // decode_OP_VOP2__V_MUL_F32
3879 
3880  GPUStaticInst*
3882  {
3883  return new Inst_VOP2__V_MUL_I32_I24(&iFmt->iFmt_VOP2);
3884  } // decode_OP_VOP2__V_MUL_I32_I24
3885 
3886  GPUStaticInst*
3888  {
3889  return new Inst_VOP2__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP2);
3890  } // decode_OP_VOP2__V_MUL_HI_I32_I24
3891 
3892  GPUStaticInst*
3894  {
3895  return new Inst_VOP2__V_MUL_U32_U24(&iFmt->iFmt_VOP2);
3896  } // decode_OP_VOP2__V_MUL_U32_U24
3897 
3898  GPUStaticInst*
3900  {
3901  return new Inst_VOP2__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP2);
3902  } // decode_OP_VOP2__V_MUL_HI_U32_U24
3903 
3904  GPUStaticInst*
3906  {
3907  return new Inst_VOP2__V_MIN_F32(&iFmt->iFmt_VOP2);
3908  } // decode_OP_VOP2__V_MIN_F32
3909 
3910  GPUStaticInst*
3912  {
3913  return new Inst_VOP2__V_MAX_F32(&iFmt->iFmt_VOP2);
3914  } // decode_OP_VOP2__V_MAX_F32
3915 
3916  GPUStaticInst*
3918  {
3919  return new Inst_VOP2__V_MIN_I32(&iFmt->iFmt_VOP2);
3920  } // decode_OP_VOP2__V_MIN_I32
3921 
3922  GPUStaticInst*
3924  {
3925  return new Inst_VOP2__V_MAX_I32(&iFmt->iFmt_VOP2);
3926  } // decode_OP_VOP2__V_MAX_I32
3927 
3928  GPUStaticInst*
3930  {
3931  return new Inst_VOP2__V_MIN_U32(&iFmt->iFmt_VOP2);
3932  } // decode_OP_VOP2__V_MIN_U32
3933 
3934  GPUStaticInst*
3936  {
3937  return new Inst_VOP2__V_MAX_U32(&iFmt->iFmt_VOP2);
3938  } // decode_OP_VOP2__V_MAX_U32
3939 
3940  GPUStaticInst*
3942  {
3943  return new Inst_VOP2__V_LSHRREV_B32(&iFmt->iFmt_VOP2);
3944  } // decode_OP_VOP2__V_LSHRREV_B32
3945 
3946  GPUStaticInst*
3948  {
3949  return new Inst_VOP2__V_ASHRREV_I32(&iFmt->iFmt_VOP2);
3950  } // decode_OP_VOP2__V_ASHRREV_I32
3951 
3952  GPUStaticInst*
3954  {
3955  return new Inst_VOP2__V_LSHLREV_B32(&iFmt->iFmt_VOP2);
3956  } // decode_OP_VOP2__V_LSHLREV_B32
3957 
3958  GPUStaticInst*
3960  {
3961  return new Inst_VOP2__V_AND_B32(&iFmt->iFmt_VOP2);
3962  } // decode_OP_VOP2__V_AND_B32
3963 
3964  GPUStaticInst*
3966  {
3967  return new Inst_VOP2__V_OR_B32(&iFmt->iFmt_VOP2);
3968  } // decode_OP_VOP2__V_OR_B32
3969 
3970  GPUStaticInst*
3972  {
3973  return new Inst_VOP2__V_XOR_B32(&iFmt->iFmt_VOP2);
3974  } // decode_OP_VOP2__V_XOR_B32
3975 
3976  GPUStaticInst*
3978  {
3979  return new Inst_VOP2__V_MAC_F32(&iFmt->iFmt_VOP2);
3980  } // decode_OP_VOP2__V_MAC_F32
3981 
3982  GPUStaticInst*
3984  {
3985  return new Inst_VOP2__V_MADMK_F32(&iFmt->iFmt_VOP2);
3986  } // decode_OP_VOP2__V_MADMK_F32
3987 
3988  GPUStaticInst*
3990  {
3991  return new Inst_VOP2__V_MADAK_F32(&iFmt->iFmt_VOP2);
3992  } // decode_OP_VOP2__V_MADAK_F32
3993 
3994  GPUStaticInst*
3996  {
3997  return new Inst_VOP2__V_ADD_CO_U32(&iFmt->iFmt_VOP2);
3998  } // decode_OP_VOP2__V_ADD_CO_U32
3999 
4000  GPUStaticInst*
4002  {
4003  return new Inst_VOP2__V_SUB_CO_U32(&iFmt->iFmt_VOP2);
4004  } // decode_OP_VOP2__V_SUB_CO_U32
4005 
4006  GPUStaticInst*
4008  {
4009  return new Inst_VOP2__V_SUBREV_CO_U32(&iFmt->iFmt_VOP2);
4010  } // decode_OP_VOP2__V_SUBREV_CO_U32
4011 
4012  GPUStaticInst*
4014  {
4015  return new Inst_VOP2__V_ADDC_CO_U32(&iFmt->iFmt_VOP2);
4016  } // decode_OP_VOP2__V_ADDC_CO_U32
4017 
4018  GPUStaticInst*
4020  {
4021  return new Inst_VOP2__V_SUBB_CO_U32(&iFmt->iFmt_VOP2);
4022  } // decode_OP_VOP2__V_SUBB_CO_U32
4023 
4024  GPUStaticInst*
4026  {
4027  return new Inst_VOP2__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP2);
4028  } // decode_OP_VOP2__V_SUBBREV_CO_U32
4029 
4030  GPUStaticInst*
4032  {
4033  return new Inst_VOP2__V_ADD_F16(&iFmt->iFmt_VOP2);
4034  } // decode_OP_VOP2__V_ADD_F16
4035 
4036  GPUStaticInst*
4038  {
4039  return new Inst_VOP2__V_SUB_F16(&iFmt->iFmt_VOP2);
4040  } // decode_OP_VOP2__V_SUB_F16
4041 
4042  GPUStaticInst*
4044  {
4045  return new Inst_VOP2__V_SUBREV_F16(&iFmt->iFmt_VOP2);
4046  } // decode_OP_VOP2__V_SUBREV_F16
4047 
4048  GPUStaticInst*
4050  {
4051  return new Inst_VOP2__V_MUL_F16(&iFmt->iFmt_VOP2);
4052  } // decode_OP_VOP2__V_MUL_F16
4053 
4054  GPUStaticInst*
4056  {
4057  return new Inst_VOP2__V_MAC_F16(&iFmt->iFmt_VOP2);
4058  } // decode_OP_VOP2__V_MAC_F16
4059 
4060  GPUStaticInst*
4062  {
4063  return new Inst_VOP2__V_MADMK_F16(&iFmt->iFmt_VOP2);
4064  } // decode_OP_VOP2__V_MADMK_F16
4065 
4066  GPUStaticInst*
4068  {
4069  return new Inst_VOP2__V_MADAK_F16(&iFmt->iFmt_VOP2);
4070  } // decode_OP_VOP2__V_MADAK_F16
4071 
4072  GPUStaticInst*
4074  {
4075  return new Inst_VOP2__V_ADD_U16(&iFmt->iFmt_VOP2);
4076  } // decode_OP_VOP2__V_ADD_U16
4077 
4078  GPUStaticInst*
4080  {
4081  return new Inst_VOP2__V_SUB_U16(&iFmt->iFmt_VOP2);
4082  } // decode_OP_VOP2__V_SUB_U16
4083 
4084  GPUStaticInst*
4086  {
4087  return new Inst_VOP2__V_SUBREV_U16(&iFmt->iFmt_VOP2);
4088  } // decode_OP_VOP2__V_SUBREV_U16
4089 
4090  GPUStaticInst*
4092  {
4093  return new Inst_VOP2__V_MUL_LO_U16(&iFmt->iFmt_VOP2);
4094  } // decode_OP_VOP2__V_MUL_LO_U16
4095 
4096  GPUStaticInst*
4098  {
4099  return new Inst_VOP2__V_LSHLREV_B16(&iFmt->iFmt_VOP2);
4100  } // decode_OP_VOP2__V_LSHLREV_B16
4101 
4102  GPUStaticInst*
4104  {
4105  return new Inst_VOP2__V_LSHRREV_B16(&iFmt->iFmt_VOP2);
4106  } // decode_OP_VOP2__V_LSHRREV_B16
4107 
4108  GPUStaticInst*
4110  {
4111  return new Inst_VOP2__V_ASHRREV_I16(&iFmt->iFmt_VOP2);
4112  } // decode_OP_VOP2__V_ASHRREV_I16
4113 
4114  GPUStaticInst*
4116  {
4117  return new Inst_VOP2__V_MAX_F16(&iFmt->iFmt_VOP2);
4118  } // decode_OP_VOP2__V_MAX_F16
4119 
4120  GPUStaticInst*
4122  {
4123  return new Inst_VOP2__V_MIN_F16(&iFmt->iFmt_VOP2);
4124  } // decode_OP_VOP2__V_MIN_F16
4125 
4126  GPUStaticInst*
4128  {
4129  return new Inst_VOP2__V_MAX_U16(&iFmt->iFmt_VOP2);
4130  } // decode_OP_VOP2__V_MAX_U16
4131 
4132  GPUStaticInst*
4134  {
4135  return new Inst_VOP2__V_MAX_I16(&iFmt->iFmt_VOP2);
4136  } // decode_OP_VOP2__V_MAX_I16
4137 
4138  GPUStaticInst*
4140  {
4141  return new Inst_VOP2__V_MIN_U16(&iFmt->iFmt_VOP2);
4142  } // decode_OP_VOP2__V_MIN_U16
4143 
4144  GPUStaticInst*
4146  {
4147  return new Inst_VOP2__V_MIN_I16(&iFmt->iFmt_VOP2);
4148  } // decode_OP_VOP2__V_MIN_I16
4149 
4150  GPUStaticInst*
4152  {
4153  return new Inst_VOP2__V_LDEXP_F16(&iFmt->iFmt_VOP2);
4154  } // decode_OP_VOP2__V_LDEXP_F16
4155 
4156  GPUStaticInst*
4158  {
4159  return new Inst_VOP2__V_ADD_U32(&iFmt->iFmt_VOP2);
4160  }
4161 
4162  GPUStaticInst*
4164  {
4165  return new Inst_VOP2__V_SUB_U32(&iFmt->iFmt_VOP2);
4166  }
4167 
4168  GPUStaticInst*
4170  {
4171  return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
4172  }
4173 
4174  GPUStaticInst*
4176  {
4177  return new Inst_SOP2__S_ADD_U32(&iFmt->iFmt_SOP2);
4178  } // decode_OP_SOP2__S_ADD_U32
4179 
4180  GPUStaticInst*
4182  {
4183  return new Inst_SOP2__S_SUB_U32(&iFmt->iFmt_SOP2);
4184  } // decode_OP_SOP2__S_SUB_U32
4185 
4186  GPUStaticInst*
4188  {
4189  return new Inst_SOP2__S_ADD_I32(&iFmt->iFmt_SOP2);
4190  } // decode_OP_SOP2__S_ADD_I32
4191 
4192  GPUStaticInst*
4194  {
4195  return new Inst_SOP2__S_SUB_I32(&iFmt->iFmt_SOP2);
4196  } // decode_OP_SOP2__S_SUB_I32
4197 
4198  GPUStaticInst*
4200  {
4201  return new Inst_SOP2__S_ADDC_U32(&iFmt->iFmt_SOP2);
4202  } // decode_OP_SOP2__S_ADDC_U32
4203 
4204  GPUStaticInst*
4206  {
4207  return new Inst_SOP2__S_SUBB_U32(&iFmt->iFmt_SOP2);
4208  } // decode_OP_SOP2__S_SUBB_U32
4209 
4210  GPUStaticInst*
4212  {
4213  return new Inst_SOP2__S_MIN_I32(&iFmt->iFmt_SOP2);
4214  } // decode_OP_SOP2__S_MIN_I32
4215 
4216  GPUStaticInst*
4218  {
4219  return new Inst_SOP2__S_MIN_U32(&iFmt->iFmt_SOP2);
4220  } // decode_OP_SOP2__S_MIN_U32
4221 
4222  GPUStaticInst*
4224  {
4225  return new Inst_SOP2__S_MAX_I32(&iFmt->iFmt_SOP2);
4226  } // decode_OP_SOP2__S_MAX_I32
4227 
4228  GPUStaticInst*
4230  {
4231  return new Inst_SOP2__S_MAX_U32(&iFmt->iFmt_SOP2);
4232  } // decode_OP_SOP2__S_MAX_U32
4233 
4234  GPUStaticInst*
4236  {
4237  return new Inst_SOP2__S_CSELECT_B32(&iFmt->iFmt_SOP2);
4238  } // decode_OP_SOP2__S_CSELECT_B32
4239 
4240  GPUStaticInst*
4242  {
4243  return new Inst_SOP2__S_CSELECT_B64(&iFmt->iFmt_SOP2);
4244  } // decode_OP_SOP2__S_CSELECT_B64
4245 
4246  GPUStaticInst*
4248  {
4249  return new Inst_SOP2__S_AND_B32(&iFmt->iFmt_SOP2);
4250  } // decode_OP_SOP2__S_AND_B32
4251 
4252  GPUStaticInst*
4254  {
4255  return new Inst_SOP2__S_AND_B64(&iFmt->iFmt_SOP2);
4256  } // decode_OP_SOP2__S_AND_B64
4257 
4258  GPUStaticInst*
4260  {
4261  return new Inst_SOP2__S_OR_B32(&iFmt->iFmt_SOP2);
4262  } // decode_OP_SOP2__S_OR_B32
4263 
4264  GPUStaticInst*
4266  {
4267  return new Inst_SOP2__S_OR_B64(&iFmt->iFmt_SOP2);
4268  } // decode_OP_SOP2__S_OR_B64
4269 
4270  GPUStaticInst*
4272  {
4273  return new Inst_SOP2__S_XOR_B32(&iFmt->iFmt_SOP2);
4274  } // decode_OP_SOP2__S_XOR_B32
4275 
4276  GPUStaticInst*
4278  {
4279  return new Inst_SOP2__S_XOR_B64(&iFmt->iFmt_SOP2);
4280  } // decode_OP_SOP2__S_XOR_B64
4281 
4282  GPUStaticInst*
4284  {
4285  return new Inst_SOP2__S_ANDN2_B32(&iFmt->iFmt_SOP2);
4286  } // decode_OP_SOP2__S_ANDN2_B32
4287 
4288  GPUStaticInst*
4290  {
4291  return new Inst_SOP2__S_ANDN2_B64(&iFmt->iFmt_SOP2);
4292  } // decode_OP_SOP2__S_ANDN2_B64
4293 
4294  GPUStaticInst*
4296  {
4297  return new Inst_SOP2__S_ORN2_B32(&iFmt->iFmt_SOP2);
4298  } // decode_OP_SOP2__S_ORN2_B32
4299 
4300  GPUStaticInst*
4302  {
4303  return new Inst_SOP2__S_ORN2_B64(&iFmt->iFmt_SOP2);
4304  } // decode_OP_SOP2__S_ORN2_B64
4305 
4306  GPUStaticInst*
4308  {
4309  return new Inst_SOP2__S_NAND_B32(&iFmt->iFmt_SOP2);
4310  } // decode_OP_SOP2__S_NAND_B32
4311 
4312  GPUStaticInst*
4314  {
4315  return new Inst_SOP2__S_NAND_B64(&iFmt->iFmt_SOP2);
4316  } // decode_OP_SOP2__S_NAND_B64
4317 
4318  GPUStaticInst*
4320  {
4321  return new Inst_SOP2__S_NOR_B32(&iFmt->iFmt_SOP2);
4322  } // decode_OP_SOP2__S_NOR_B32
4323 
4324  GPUStaticInst*
4326  {
4327  return new Inst_SOP2__S_NOR_B64(&iFmt->iFmt_SOP2);
4328  } // decode_OP_SOP2__S_NOR_B64
4329 
4330  GPUStaticInst*
4332  {
4333  return new Inst_SOP2__S_XNOR_B32(&iFmt->iFmt_SOP2);
4334  } // decode_OP_SOP2__S_XNOR_B32
4335 
4336  GPUStaticInst*
4338  {
4339  return new Inst_SOP2__S_XNOR_B64(&iFmt->iFmt_SOP2);
4340  } // decode_OP_SOP2__S_XNOR_B64
4341 
4342  GPUStaticInst*
4344  {
4345  return new Inst_SOP2__S_LSHL_B32(&iFmt->iFmt_SOP2);
4346  } // decode_OP_SOP2__S_LSHL_B32
4347 
4348  GPUStaticInst*
4350  {
4351  return new Inst_SOP2__S_LSHL_B64(&iFmt->iFmt_SOP2);
4352  } // decode_OP_SOP2__S_LSHL_B64
4353 
4354  GPUStaticInst*
4356  {
4357  return new Inst_SOP2__S_LSHR_B32(&iFmt->iFmt_SOP2);
4358  } // decode_OP_SOP2__S_LSHR_B32
4359 
4360  GPUStaticInst*
4362  {
4363  return new Inst_SOP2__S_LSHR_B64(&iFmt->iFmt_SOP2);
4364  } // decode_OP_SOP2__S_LSHR_B64
4365 
4366  GPUStaticInst*
4368  {
4369  return new Inst_SOP2__S_ASHR_I32(&iFmt->iFmt_SOP2);
4370  } // decode_OP_SOP2__S_ASHR_I32
4371 
4372  GPUStaticInst*
4374  {
4375  return new Inst_SOP2__S_ASHR_I64(&iFmt->iFmt_SOP2);
4376  } // decode_OP_SOP2__S_ASHR_I64
4377 
4378  GPUStaticInst*
4380  {
4381  return new Inst_SOP2__S_BFM_B32(&iFmt->iFmt_SOP2);
4382  } // decode_OP_SOP2__S_BFM_B32
4383 
4384  GPUStaticInst*
4386  {
4387  return new Inst_SOP2__S_BFM_B64(&iFmt->iFmt_SOP2);
4388  } // decode_OP_SOP2__S_BFM_B64
4389 
4390  GPUStaticInst*
4392  {
4393  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
4394  } // decode_OP_SOP2__S_MUL_I32
4395 
4396  GPUStaticInst*
4398  {
4399  return new Inst_SOP2__S_BFE_U32(&iFmt->iFmt_SOP2);
4400  } // decode_OP_SOP2__S_BFE_U32
4401 
4402  GPUStaticInst*
4404  {
4405  return new Inst_SOP2__S_BFE_I32(&iFmt->iFmt_SOP2);
4406  } // decode_OP_SOP2__S_BFE_I32
4407 
4408  GPUStaticInst*
4410  {
4411  return new Inst_SOP2__S_BFE_U64(&iFmt->iFmt_SOP2);
4412  } // decode_OP_SOP2__S_BFE_U64
4413 
4414  GPUStaticInst*
4416  {
4417  return new Inst_SOP2__S_BFE_I64(&iFmt->iFmt_SOP2);
4418  } // decode_OP_SOP2__S_BFE_I64
4419 
4420  GPUStaticInst*
4422  {
4423  return new Inst_SOP2__S_CBRANCH_G_FORK(&iFmt->iFmt_SOP2);
4424  } // decode_OP_SOP2__S_CBRANCH_G_FORK
4425 
4426  GPUStaticInst*
4428  {
4429  return new Inst_SOP2__S_ABSDIFF_I32(&iFmt->iFmt_SOP2);
4430  } // decode_OP_SOP2__S_ABSDIFF_I32
4431 
4432  GPUStaticInst*
4434  {
4435  return new Inst_SOP2__S_RFE_RESTORE_B64(&iFmt->iFmt_SOP2);
4436  } // decode_OP_SOP2__S_RFE_RESTORE_B64
4437 
4438  GPUStaticInst*
4440  {
4441  return new Inst_SOP2__S_MUL_HI_U32(&iFmt->iFmt_SOP2);
4442  }
4443 
4444  GPUStaticInst*
4446  {
4447  return new Inst_SOP2__S_MUL_HI_I32(&iFmt->iFmt_SOP2);
4448  }
4449 
4450  GPUStaticInst*
4452  {
4453  fatal("Trying to decode instruction without a class\n");
4454  return nullptr;
4455  }
4456 
4457  GPUStaticInst*
4459  {
4460  fatal("Trying to decode instruction without a class\n");
4461  return nullptr;
4462  }
4463 
4464  GPUStaticInst*
4466  {
4467  fatal("Trying to decode instruction without a class\n");
4468  return nullptr;
4469  }
4470 
4471  GPUStaticInst*
4473  {
4474  fatal("Trying to decode instruction without a class\n");
4475  return nullptr;
4476  }
4477 
4478  GPUStaticInst*
4480  {
4481  fatal("Trying to decode instruction without a class\n");
4482  return nullptr;
4483  }
4484 
4485  GPUStaticInst*
4487  {
4488  fatal("Trying to decode instruction without a class\n");
4489  return nullptr;
4490  }
4491 
4492  GPUStaticInst*
4494  {
4495  fatal("Trying to decode instruction without a class\n");
4496  return nullptr;
4497  }
4498 
4499  GPUStaticInst*
4501  {
4502  return new Inst_SOPK__S_MOVK_I32(&iFmt->iFmt_SOPK);
4503  } // decode_OP_SOPK__S_MOVK_I32
4504 
4505  GPUStaticInst*
4507  {
4508  return new Inst_SOPK__S_CMOVK_I32(&iFmt->iFmt_SOPK);
4509  } // decode_OP_SOPK__S_CMOVK_I32
4510 
4511  GPUStaticInst*
4513  {
4514  return new Inst_SOPK__S_CMPK_EQ_I32(&iFmt->iFmt_SOPK);
4515  } // decode_OP_SOPK__S_CMPK_EQ_I32
4516 
4517  GPUStaticInst*
4519  {
4520  return new Inst_SOPK__S_CMPK_LG_I32(&iFmt->iFmt_SOPK);
4521  } // decode_OP_SOPK__S_CMPK_LG_I32
4522 
4523  GPUStaticInst*
4525  {
4526  return new Inst_SOPK__S_CMPK_GT_I32(&iFmt->iFmt_SOPK);
4527  } // decode_OP_SOPK__S_CMPK_GT_I32
4528 
4529  GPUStaticInst*
4531  {
4532  return new Inst_SOPK__S_CMPK_GE_I32(&iFmt->iFmt_SOPK);
4533  } // decode_OP_SOPK__S_CMPK_GE_I32
4534 
4535  GPUStaticInst*
4537  {
4538  return new Inst_SOPK__S_CMPK_LT_I32(&iFmt->iFmt_SOPK);
4539  } // decode_OP_SOPK__S_CMPK_LT_I32
4540 
4541  GPUStaticInst*
4543  {
4544  return new Inst_SOPK__S_CMPK_LE_I32(&iFmt->iFmt_SOPK);
4545  } // decode_OP_SOPK__S_CMPK_LE_I32
4546 
4547  GPUStaticInst*
4549  {
4550  return new Inst_SOPK__S_CMPK_EQ_U32(&iFmt->iFmt_SOPK);
4551  } // decode_OP_SOPK__S_CMPK_EQ_U32
4552 
4553  GPUStaticInst*
4555  {
4556  return new Inst_SOPK__S_CMPK_LG_U32(&iFmt->iFmt_SOPK);
4557  } // decode_OP_SOPK__S_CMPK_LG_U32
4558 
4559  GPUStaticInst*
4561  {
4562  return new Inst_SOPK__S_CMPK_GT_U32(&iFmt->iFmt_SOPK);
4563  } // decode_OP_SOPK__S_CMPK_GT_U32
4564 
4565  GPUStaticInst*
4567  {
4568  return new Inst_SOPK__S_CMPK_GE_U32(&iFmt->iFmt_SOPK);
4569  } // decode_OP_SOPK__S_CMPK_GE_U32
4570 
4571  GPUStaticInst*
4573  {
4574  return new Inst_SOPK__S_CMPK_LT_U32(&iFmt->iFmt_SOPK);
4575  } // decode_OP_SOPK__S_CMPK_LT_U32
4576 
4577  GPUStaticInst*
4579  {
4580  return new Inst_SOPK__S_CMPK_LE_U32(&iFmt->iFmt_SOPK);
4581  } // decode_OP_SOPK__S_CMPK_LE_U32
4582 
4583  GPUStaticInst*
4585  {
4586  return new Inst_SOPK__S_ADDK_I32(&iFmt->iFmt_SOPK);
4587  } // decode_OP_SOPK__S_ADDK_I32
4588 
4589  GPUStaticInst*
4591  {
4592  return new Inst_SOPK__S_MULK_I32(&iFmt->iFmt_SOPK);
4593  } // decode_OP_SOPK__S_MULK_I32
4594 
4595  GPUStaticInst*
4597  {
4598  return new Inst_SOPK__S_CBRANCH_I_FORK(&iFmt->iFmt_SOPK);
4599  } // decode_OP_SOPK__S_CBRANCH_I_FORK
4600 
4601  GPUStaticInst*
4603  {
4604  return new Inst_SOPK__S_GETREG_B32(&iFmt->iFmt_SOPK);
4605  } // decode_OP_SOPK__S_GETREG_B32
4606 
4607  GPUStaticInst*
4609  {
4610  return new Inst_SOPK__S_SETREG_B32(&iFmt->iFmt_SOPK);
4611  } // decode_OP_SOPK__S_SETREG_B32
4612 
4613  GPUStaticInst*
4615  {
4616  return new Inst_SOPK__S_SETREG_IMM32_B32(&iFmt->iFmt_SOPK);
4617  } // decode_OP_SOPK__S_SETREG_IMM32_B32
4618 
4619  GPUStaticInst*
4621  {
4622  fatal("Trying to decode instruction without a class\n");
4623  return nullptr;
4624  }
4625 
4626  GPUStaticInst*
4628  {
4629  return new Inst_EXP__EXP(&iFmt->iFmt_EXP);
4630  } // decode_OP_EXP
4631 
4632  GPUStaticInst*
4634  {
4635  return new Inst_VOP3__V_CMP_CLASS_F32(&iFmt->iFmt_VOP3A);
4636  } // decode_OPU_VOP3__V_CMP_CLASS_F32
4637 
4638  GPUStaticInst*
4640  {
4641  return new Inst_VOP3__V_CMPX_CLASS_F32(&iFmt->iFmt_VOP3A);
4642  } // decode_OPU_VOP3__V_CMPX_CLASS_F32
4643 
4644  GPUStaticInst*
4646  {
4647  return new Inst_VOP3__V_CMP_CLASS_F64(&iFmt->iFmt_VOP3A);
4648  } // decode_OPU_VOP3__V_CMP_CLASS_F64
4649 
4650  GPUStaticInst*
4652  {
4653  return new Inst_VOP3__V_CMPX_CLASS_F64(&iFmt->iFmt_VOP3A);
4654  } // decode_OPU_VOP3__V_CMPX_CLASS_F64
4655 
4656  GPUStaticInst*
4658  {
4659  return new Inst_VOP3__V_CMP_CLASS_F16(&iFmt->iFmt_VOP3A);
4660  } // decode_OPU_VOP3__V_CMP_CLASS_F16
4661 
4662  GPUStaticInst*
4664  {
4665  return new Inst_VOP3__V_CMPX_CLASS_F16(&iFmt->iFmt_VOP3A);
4666  } // decode_OPU_VOP3__V_CMPX_CLASS_F16
4667 
4668  GPUStaticInst*
4670  {
4671  return new Inst_VOP3__V_CMP_F_F16(&iFmt->iFmt_VOP3A);
4672  } // decode_OPU_VOP3__V_CMP_F_F16
4673 
4674  GPUStaticInst*
4676  {
4677  return new Inst_VOP3__V_CMP_LT_F16(&iFmt->iFmt_VOP3A);
4678  } // decode_OPU_VOP3__V_CMP_LT_F16
4679 
4680  GPUStaticInst*
4682  {
4683  return new Inst_VOP3__V_CMP_EQ_F16(&iFmt->iFmt_VOP3A);
4684  } // decode_OPU_VOP3__V_CMP_EQ_F16
4685 
4686  GPUStaticInst*
4688  {
4689  return new Inst_VOP3__V_CMP_LE_F16(&iFmt->iFmt_VOP3A);
4690  } // decode_OPU_VOP3__V_CMP_LE_F16
4691 
4692  GPUStaticInst*
4694  {
4695  return new Inst_VOP3__V_CMP_GT_F16(&iFmt->iFmt_VOP3A);
4696  } // decode_OPU_VOP3__V_CMP_GT_F16
4697 
4698  GPUStaticInst*
4700  {
4701  return new Inst_VOP3__V_CMP_LG_F16(&iFmt->iFmt_VOP3A);
4702  } // decode_OPU_VOP3__V_CMP_LG_F16
4703 
4704  GPUStaticInst*
4706  {
4707  return new Inst_VOP3__V_CMP_GE_F16(&iFmt->iFmt_VOP3A);
4708  } // decode_OPU_VOP3__V_CMP_GE_F16
4709 
4710  GPUStaticInst*
4712  {
4713  return new Inst_VOP3__V_CMP_O_F16(&iFmt->iFmt_VOP3A);
4714  } // decode_OPU_VOP3__V_CMP_O_F16
4715 
4716  GPUStaticInst*
4718  {
4719  return new Inst_VOP3__V_CMP_U_F16(&iFmt->iFmt_VOP3A);
4720  } // decode_OPU_VOP3__V_CMP_U_F16
4721 
4722  GPUStaticInst*
4724  {
4725  return new Inst_VOP3__V_CMP_NGE_F16(&iFmt->iFmt_VOP3A);
4726  } // decode_OPU_VOP3__V_CMP_NGE_F16
4727 
4728  GPUStaticInst*
4730  {
4731  return new Inst_VOP3__V_CMP_NLG_F16(&iFmt->iFmt_VOP3A);
4732  } // decode_OPU_VOP3__V_CMP_NLG_F16
4733 
4734  GPUStaticInst*
4736  {
4737  return new Inst_VOP3__V_CMP_NGT_F16(&iFmt->iFmt_VOP3A);
4738  } // decode_OPU_VOP3__V_CMP_NGT_F16
4739 
4740  GPUStaticInst*
4742  {
4743  return new Inst_VOP3__V_CMP_NLE_F16(&iFmt->iFmt_VOP3A);
4744  } // decode_OPU_VOP3__V_CMP_NLE_F16
4745 
4746  GPUStaticInst*
4748  {
4749  return new Inst_VOP3__V_CMP_NEQ_F16(&iFmt->iFmt_VOP3A);
4750  } // decode_OPU_VOP3__V_CMP_NEQ_F16
4751 
4752  GPUStaticInst*
4754  {
4755  return new Inst_VOP3__V_CMP_NLT_F16(&iFmt->iFmt_VOP3A);
4756  } // decode_OPU_VOP3__V_CMP_NLT_F16
4757 
4758  GPUStaticInst*
4760  {
4761  return new Inst_VOP3__V_CMP_TRU_F16(&iFmt->iFmt_VOP3A);
4762  } // decode_OPU_VOP3__V_CMP_TRU_F16
4763 
4764  GPUStaticInst*
4766  {
4767  return new Inst_VOP3__V_CMPX_F_F16(&iFmt->iFmt_VOP3A);
4768  } // decode_OPU_VOP3__V_CMPX_F_F16
4769 
4770  GPUStaticInst*
4772  {
4773  return new Inst_VOP3__V_CMPX_LT_F16(&iFmt->iFmt_VOP3A);
4774  } // decode_OPU_VOP3__V_CMPX_LT_F16
4775 
4776  GPUStaticInst*
4778  {
4779  return new Inst_VOP3__V_CMPX_EQ_F16(&iFmt->iFmt_VOP3A);
4780  } // decode_OPU_VOP3__V_CMPX_EQ_F16
4781 
4782  GPUStaticInst*
4784  {
4785  return new Inst_VOP3__V_CMPX_LE_F16(&iFmt->iFmt_VOP3A);
4786  } // decode_OPU_VOP3__V_CMPX_LE_F16
4787 
4788  GPUStaticInst*
4790  {
4791  return new Inst_VOP3__V_CMPX_GT_F16(&iFmt->iFmt_VOP3A);
4792  } // decode_OPU_VOP3__V_CMPX_GT_F16
4793 
4794  GPUStaticInst*
4796  {
4797  return new Inst_VOP3__V_CMPX_LG_F16(&iFmt->iFmt_VOP3A);
4798  } // decode_OPU_VOP3__V_CMPX_LG_F16
4799 
4800  GPUStaticInst*
4802  {
4803  return new Inst_VOP3__V_CMPX_GE_F16(&iFmt->iFmt_VOP3A);
4804  } // decode_OPU_VOP3__V_CMPX_GE_F16
4805 
4806  GPUStaticInst*
4808  {
4809  return new Inst_VOP3__V_CMPX_O_F16(&iFmt->iFmt_VOP3A);
4810  } // decode_OPU_VOP3__V_CMPX_O_F16
4811 
4812  GPUStaticInst*
4814  {
4815  return new Inst_VOP3__V_CMPX_U_F16(&iFmt->iFmt_VOP3A);
4816  } // decode_OPU_VOP3__V_CMPX_U_F16
4817 
4818  GPUStaticInst*
4820  {
4821  return new Inst_VOP3__V_CMPX_NGE_F16(&iFmt->iFmt_VOP3A);
4822  } // decode_OPU_VOP3__V_CMPX_NGE_F16
4823 
4824  GPUStaticInst*
4826  {
4827  return new Inst_VOP3__V_CMPX_NLG_F16(&iFmt->iFmt_VOP3A);
4828  } // decode_OPU_VOP3__V_CMPX_NLG_F16
4829 
4830  GPUStaticInst*
4832  {
4833  return new Inst_VOP3__V_CMPX_NGT_F16(&iFmt->iFmt_VOP3A);
4834  } // decode_OPU_VOP3__V_CMPX_NGT_F16
4835 
4836  GPUStaticInst*
4838  {
4839  return new Inst_VOP3__V_CMPX_NLE_F16(&iFmt->iFmt_VOP3A);
4840  } // decode_OPU_VOP3__V_CMPX_NLE_F16
4841 
4842  GPUStaticInst*
4844  {
4845  return new Inst_VOP3__V_CMPX_NEQ_F16(&iFmt->iFmt_VOP3A);
4846  } // decode_OPU_VOP3__V_CMPX_NEQ_F16
4847 
4848  GPUStaticInst*
4850  {
4851  return new Inst_VOP3__V_CMPX_NLT_F16(&iFmt->iFmt_VOP3A);
4852  } // decode_OPU_VOP3__V_CMPX_NLT_F16
4853 
4854  GPUStaticInst*
4856  {
4857  return new Inst_VOP3__V_CMPX_TRU_F16(&iFmt->iFmt_VOP3A);
4858  } // decode_OPU_VOP3__V_CMPX_TRU_F16
4859 
4860  GPUStaticInst*
4862  {
4863  return new Inst_VOP3__V_CMP_F_F32(&iFmt->iFmt_VOP3A);
4864  } // decode_OPU_VOP3__V_CMP_F_F32
4865 
4866  GPUStaticInst*
4868  {
4869  return new Inst_VOP3__V_CMP_LT_F32(&iFmt->iFmt_VOP3A);
4870  } // decode_OPU_VOP3__V_CMP_LT_F32
4871 
4872  GPUStaticInst*
4874  {
4875  return new Inst_VOP3__V_CMP_EQ_F32(&iFmt->iFmt_VOP3A);
4876  } // decode_OPU_VOP3__V_CMP_EQ_F32
4877 
4878  GPUStaticInst*
4880  {
4881  return new Inst_VOP3__V_CMP_LE_F32(&iFmt->iFmt_VOP3A);
4882  } // decode_OPU_VOP3__V_CMP_LE_F32
4883 
4884  GPUStaticInst*
4886  {
4887  return new Inst_VOP3__V_CMP_GT_F32(&iFmt->iFmt_VOP3A);
4888  } // decode_OPU_VOP3__V_CMP_GT_F32
4889 
4890  GPUStaticInst*
4892  {
4893  return new Inst_VOP3__V_CMP_LG_F32(&iFmt->iFmt_VOP3A);
4894  } // decode_OPU_VOP3__V_CMP_LG_F32
4895 
4896  GPUStaticInst*
4898  {
4899  return new Inst_VOP3__V_CMP_GE_F32(&iFmt->iFmt_VOP3A);
4900  } // decode_OPU_VOP3__V_CMP_GE_F32
4901 
4902  GPUStaticInst*
4904  {
4905  return new Inst_VOP3__V_CMP_O_F32(&iFmt->iFmt_VOP3A);
4906  } // decode_OPU_VOP3__V_CMP_O_F32
4907 
4908  GPUStaticInst*
4910  {
4911  return new Inst_VOP3__V_CMP_U_F32(&iFmt->iFmt_VOP3A);
4912  } // decode_OPU_VOP3__V_CMP_U_F32
4913 
4914  GPUStaticInst*
4916  {
4917  return new Inst_VOP3__V_CMP_NGE_F32(&iFmt->iFmt_VOP3A);
4918  } // decode_OPU_VOP3__V_CMP_NGE_F32
4919 
4920  GPUStaticInst*
4922  {
4923  return new Inst_VOP3__V_CMP_NLG_F32(&iFmt->iFmt_VOP3A);
4924  } // decode_OPU_VOP3__V_CMP_NLG_F32
4925 
4926  GPUStaticInst*
4928  {
4929  return new Inst_VOP3__V_CMP_NGT_F32(&iFmt->iFmt_VOP3A);
4930  } // decode_OPU_VOP3__V_CMP_NGT_F32
4931 
4932  GPUStaticInst*
4934  {
4935  return new Inst_VOP3__V_CMP_NLE_F32(&iFmt->iFmt_VOP3A);
4936  } // decode_OPU_VOP3__V_CMP_NLE_F32
4937 
4938  GPUStaticInst*
4940  {
4941  return new Inst_VOP3__V_CMP_NEQ_F32(&iFmt->iFmt_VOP3A);
4942  } // decode_OPU_VOP3__V_CMP_NEQ_F32
4943 
4944  GPUStaticInst*
4946  {
4947  return new Inst_VOP3__V_CMP_NLT_F32(&iFmt->iFmt_VOP3A);
4948  } // decode_OPU_VOP3__V_CMP_NLT_F32
4949 
4950  GPUStaticInst*
4952  {
4953  return new Inst_VOP3__V_CMP_TRU_F32(&iFmt->iFmt_VOP3A);
4954  } // decode_OPU_VOP3__V_CMP_TRU_F32
4955 
4956  GPUStaticInst*
4958  {
4959  return new Inst_VOP3__V_CMPX_F_F32(&iFmt->iFmt_VOP3A);
4960  } // decode_OPU_VOP3__V_CMPX_F_F32
4961 
4962  GPUStaticInst*
4964  {
4965  return new Inst_VOP3__V_CMPX_LT_F32(&iFmt->iFmt_VOP3A);
4966  } // decode_OPU_VOP3__V_CMPX_LT_F32
4967 
4968  GPUStaticInst*
4970  {
4971  return new Inst_VOP3__V_CMPX_EQ_F32(&iFmt->iFmt_VOP3A);
4972  } // decode_OPU_VOP3__V_CMPX_EQ_F32
4973 
4974  GPUStaticInst*
4976  {
4977  return new Inst_VOP3__V_CMPX_LE_F32(&iFmt->iFmt_VOP3A);
4978  } // decode_OPU_VOP3__V_CMPX_LE_F32
4979 
4980  GPUStaticInst*
4982  {
4983  return new Inst_VOP3__V_CMPX_GT_F32(&iFmt->iFmt_VOP3A);
4984  } // decode_OPU_VOP3__V_CMPX_GT_F32
4985 
4986  GPUStaticInst*
4988  {
4989  return new Inst_VOP3__V_CMPX_LG_F32(&iFmt->iFmt_VOP3A);
4990  } // decode_OPU_VOP3__V_CMPX_LG_F32
4991 
4992  GPUStaticInst*
4994  {
4995  return new Inst_VOP3__V_CMPX_GE_F32(&iFmt->iFmt_VOP3A);
4996  } // decode_OPU_VOP3__V_CMPX_GE_F32
4997 
4998  GPUStaticInst*
5000  {
5001  return new Inst_VOP3__V_CMPX_O_F32(&iFmt->iFmt_VOP3A);
5002  } // decode_OPU_VOP3__V_CMPX_O_F32
5003 
5004  GPUStaticInst*
5006  {
5007  return new Inst_VOP3__V_CMPX_U_F32(&iFmt->iFmt_VOP3A);
5008  } // decode_OPU_VOP3__V_CMPX_U_F32
5009 
5010  GPUStaticInst*
5012  {
5013  return new Inst_VOP3__V_CMPX_NGE_F32(&iFmt->iFmt_VOP3A);
5014  } // decode_OPU_VOP3__V_CMPX_NGE_F32
5015 
5016  GPUStaticInst*
5018  {
5019  return new Inst_VOP3__V_CMPX_NLG_F32(&iFmt->iFmt_VOP3A);
5020  } // decode_OPU_VOP3__V_CMPX_NLG_F32
5021 
5022  GPUStaticInst*
5024  {
5025  return new Inst_VOP3__V_CMPX_NGT_F32(&iFmt->iFmt_VOP3A);
5026  } // decode_OPU_VOP3__V_CMPX_NGT_F32
5027 
5028  GPUStaticInst*
5030  {
5031  return new Inst_VOP3__V_CMPX_NLE_F32(&iFmt->iFmt_VOP3A);
5032  } // decode_OPU_VOP3__V_CMPX_NLE_F32
5033 
5034  GPUStaticInst*
5036  {
5037  return new Inst_VOP3__V_CMPX_NEQ_F32(&iFmt->iFmt_VOP3A);
5038  } // decode_OPU_VOP3__V_CMPX_NEQ_F32
5039 
5040  GPUStaticInst*
5042  {
5043  return new Inst_VOP3__V_CMPX_NLT_F32(&iFmt->iFmt_VOP3A);
5044  } // decode_OPU_VOP3__V_CMPX_NLT_F32
5045 
5046  GPUStaticInst*
5048  {
5049  return new Inst_VOP3__V_CMPX_TRU_F32(&iFmt->iFmt_VOP3A);
5050  } // decode_OPU_VOP3__V_CMPX_TRU_F32
5051 
5052  GPUStaticInst*
5054  {
5055  return new Inst_VOP3__V_CMP_F_F64(&iFmt->iFmt_VOP3A);
5056  } // decode_OPU_VOP3__V_CMP_F_F64
5057 
5058  GPUStaticInst*
5060  {
5061  return new Inst_VOP3__V_CMP_LT_F64(&iFmt->iFmt_VOP3A);
5062  } // decode_OPU_VOP3__V_CMP_LT_F64
5063 
5064  GPUStaticInst*
5066  {
5067  return new Inst_VOP3__V_CMP_EQ_F64(&iFmt->iFmt_VOP3A);
5068  } // decode_OPU_VOP3__V_CMP_EQ_F64
5069 
5070  GPUStaticInst*
5072  {
5073  return new Inst_VOP3__V_CMP_LE_F64(&iFmt->iFmt_VOP3A);
5074  } // decode_OPU_VOP3__V_CMP_LE_F64
5075 
5076  GPUStaticInst*
5078  {
5079  return new Inst_VOP3__V_CMP_GT_F64(&iFmt->iFmt_VOP3A);
5080  } // decode_OPU_VOP3__V_CMP_GT_F64
5081 
5082  GPUStaticInst*
5084  {
5085  return new Inst_VOP3__V_CMP_LG_F64(&iFmt->iFmt_VOP3A);
5086  } // decode_OPU_VOP3__V_CMP_LG_F64
5087 
5088  GPUStaticInst*
5090  {
5091  return new Inst_VOP3__V_CMP_GE_F64(&iFmt->iFmt_VOP3A);
5092  } // decode_OPU_VOP3__V_CMP_GE_F64
5093 
5094  GPUStaticInst*
5096  {
5097  return new Inst_VOP3__V_CMP_O_F64(&iFmt->iFmt_VOP3A);
5098  } // decode_OPU_VOP3__V_CMP_O_F64
5099 
5100  GPUStaticInst*
5102  {
5103  return new Inst_VOP3__V_CMP_U_F64(&iFmt->iFmt_VOP3A);
5104  } // decode_OPU_VOP3__V_CMP_U_F64
5105 
5106  GPUStaticInst*
5108  {
5109  return new Inst_VOP3__V_CMP_NGE_F64(&iFmt->iFmt_VOP3A);
5110  } // decode_OPU_VOP3__V_CMP_NGE_F64
5111 
5112  GPUStaticInst*
5114  {
5115  return new Inst_VOP3__V_CMP_NLG_F64(&iFmt->iFmt_VOP3A);
5116  } // decode_OPU_VOP3__V_CMP_NLG_F64
5117 
5118  GPUStaticInst*
5120  {
5121  return new Inst_VOP3__V_CMP_NGT_F64(&iFmt->iFmt_VOP3A);
5122  } // decode_OPU_VOP3__V_CMP_NGT_F64
5123 
5124  GPUStaticInst*
5126  {
5127  return new Inst_VOP3__V_CMP_NLE_F64(&iFmt->iFmt_VOP3A);
5128  } // decode_OPU_VOP3__V_CMP_NLE_F64
5129 
5130  GPUStaticInst*
5132  {
5133  return new Inst_VOP3__V_CMP_NEQ_F64(&iFmt->iFmt_VOP3A);
5134  } // decode_OPU_VOP3__V_CMP_NEQ_F64
5135 
5136  GPUStaticInst*
5138  {
5139  return new Inst_VOP3__V_CMP_NLT_F64(&iFmt->iFmt_VOP3A);
5140  } // decode_OPU_VOP3__V_CMP_NLT_F64
5141 
5142  GPUStaticInst*
5144  {
5145  return new Inst_VOP3__V_CMP_TRU_F64(&iFmt->iFmt_VOP3A);
5146  } // decode_OPU_VOP3__V_CMP_TRU_F64
5147 
5148  GPUStaticInst*
5150  {
5151  return new Inst_VOP3__V_CMPX_F_F64(&iFmt->iFmt_VOP3A);
5152  } // decode_OPU_VOP3__V_CMPX_F_F64
5153 
5154  GPUStaticInst*
5156  {
5157  return new Inst_VOP3__V_CMPX_LT_F64(&iFmt->iFmt_VOP3A);
5158  } // decode_OPU_VOP3__V_CMPX_LT_F64
5159 
5160  GPUStaticInst*
5162  {
5163  return new Inst_VOP3__V_CMPX_EQ_F64(&iFmt->iFmt_VOP3A);
5164  } // decode_OPU_VOP3__V_CMPX_EQ_F64
5165 
5166  GPUStaticInst*
5168  {
5169  return new Inst_VOP3__V_CMPX_LE_F64(&iFmt->iFmt_VOP3A);
5170  } // decode_OPU_VOP3__V_CMPX_LE_F64
5171 
5172  GPUStaticInst*
5174  {
5175  return new Inst_VOP3__V_CMPX_GT_F64(&iFmt->iFmt_VOP3A);
5176  } // decode_OPU_VOP3__V_CMPX_GT_F64
5177 
5178  GPUStaticInst*
5180  {
5181  return new Inst_VOP3__V_CMPX_LG_F64(&iFmt->iFmt_VOP3A);
5182  } // decode_OPU_VOP3__V_CMPX_LG_F64
5183 
5184  GPUStaticInst*
5186  {
5187  return new Inst_VOP3__V_CMPX_GE_F64(&iFmt->iFmt_VOP3A);
5188  } // decode_OPU_VOP3__V_CMPX_GE_F64
5189 
5190  GPUStaticInst*
5192  {
5193  return new Inst_VOP3__V_CMPX_O_F64(&iFmt->iFmt_VOP3A);
5194  } // decode_OPU_VOP3__V_CMPX_O_F64
5195 
5196  GPUStaticInst*
5198  {
5199  return new Inst_VOP3__V_CMPX_U_F64(&iFmt->iFmt_VOP3A);
5200  } // decode_OPU_VOP3__V_CMPX_U_F64
5201 
5202  GPUStaticInst*
5204  {
5205  return new Inst_VOP3__V_CMPX_NGE_F64(&iFmt->iFmt_VOP3A);
5206  } // decode_OPU_VOP3__V_CMPX_NGE_F64
5207 
5208  GPUStaticInst*
5210  {
5211  return new Inst_VOP3__V_CMPX_NLG_F64(&iFmt->iFmt_VOP3A);
5212  } // decode_OPU_VOP3__V_CMPX_NLG_F64
5213 
5214  GPUStaticInst*
5216  {
5217  return new Inst_VOP3__V_CMPX_NGT_F64(&iFmt->iFmt_VOP3A);
5218  } // decode_OPU_VOP3__V_CMPX_NGT_F64
5219 
5220  GPUStaticInst*
5222  {
5223  return new Inst_VOP3__V_CMPX_NLE_F64(&iFmt->iFmt_VOP3A);
5224  } // decode_OPU_VOP3__V_CMPX_NLE_F64
5225 
5226  GPUStaticInst*
5228  {
5229  return new Inst_VOP3__V_CMPX_NEQ_F64(&iFmt->iFmt_VOP3A);
5230  } // decode_OPU_VOP3__V_CMPX_NEQ_F64
5231 
5232  GPUStaticInst*
5234  {
5235  return new Inst_VOP3__V_CMPX_NLT_F64(&iFmt->iFmt_VOP3A);
5236  } // decode_OPU_VOP3__V_CMPX_NLT_F64
5237 
5238  GPUStaticInst*
5240  {
5241  return new Inst_VOP3__V_CMPX_TRU_F64(&iFmt->iFmt_VOP3A);
5242  } // decode_OPU_VOP3__V_CMPX_TRU_F64
5243 
5244  GPUStaticInst*
5246  {
5247  return new Inst_VOP3__V_CMP_F_I16(&iFmt->iFmt_VOP3A);
5248  } // decode_OPU_VOP3__V_CMP_F_I16
5249 
5250  GPUStaticInst*
5252  {
5253  return new Inst_VOP3__V_CMP_LT_I16(&iFmt->iFmt_VOP3A);
5254  } // decode_OPU_VOP3__V_CMP_LT_I16
5255 
5256  GPUStaticInst*
5258  {
5259  return new Inst_VOP3__V_CMP_EQ_I16(&iFmt->iFmt_VOP3A);
5260  } // decode_OPU_VOP3__V_CMP_EQ_I16
5261 
5262  GPUStaticInst*
5264  {
5265  return new Inst_VOP3__V_CMP_LE_I16(&iFmt->iFmt_VOP3A);
5266  } // decode_OPU_VOP3__V_CMP_LE_I16
5267 
5268  GPUStaticInst*
5270  {
5271  return new Inst_VOP3__V_CMP_GT_I16(&iFmt->iFmt_VOP3A);
5272  } // decode_OPU_VOP3__V_CMP_GT_I16
5273 
5274  GPUStaticInst*
5276  {
5277  return new Inst_VOP3__V_CMP_NE_I16(&iFmt->iFmt_VOP3A);
5278  } // decode_OPU_VOP3__V_CMP_NE_I16
5279 
5280  GPUStaticInst*
5282  {
5283  return new Inst_VOP3__V_CMP_GE_I16(&iFmt->iFmt_VOP3A);
5284  } // decode_OPU_VOP3__V_CMP_GE_I16
5285 
5286  GPUStaticInst*
5288  {
5289  return new Inst_VOP3__V_CMP_T_I16(&iFmt->iFmt_VOP3A);
5290  } // decode_OPU_VOP3__V_CMP_T_I16
5291 
5292  GPUStaticInst*
5294  {
5295  return new Inst_VOP3__V_CMP_F_U16(&iFmt->iFmt_VOP3A);
5296  } // decode_OPU_VOP3__V_CMP_F_U16
5297 
5298  GPUStaticInst*
5300  {
5301  return new Inst_VOP3__V_CMP_LT_U16(&iFmt->iFmt_VOP3A);
5302  } // decode_OPU_VOP3__V_CMP_LT_U16
5303 
5304  GPUStaticInst*
5306  {
5307  return new Inst_VOP3__V_CMP_EQ_U16(&iFmt->iFmt_VOP3A);
5308  } // decode_OPU_VOP3__V_CMP_EQ_U16
5309 
5310  GPUStaticInst*
5312  {
5313  return new Inst_VOP3__V_CMP_LE_U16(&iFmt->iFmt_VOP3A);
5314  } // decode_OPU_VOP3__V_CMP_LE_U16
5315 
5316  GPUStaticInst*
5318  {
5319  return new Inst_VOP3__V_CMP_GT_U16(&iFmt->iFmt_VOP3A);
5320  } // decode_OPU_VOP3__V_CMP_GT_U16
5321 
5322  GPUStaticInst*
5324  {
5325  return new Inst_VOP3__V_CMP_NE_U16(&iFmt->iFmt_VOP3A);
5326  } // decode_OPU_VOP3__V_CMP_NE_U16
5327 
5328  GPUStaticInst*
5330  {
5331  return new Inst_VOP3__V_CMP_GE_U16(&iFmt->iFmt_VOP3A);
5332  } // decode_OPU_VOP3__V_CMP_GE_U16
5333 
5334  GPUStaticInst*
5336  {
5337  return new Inst_VOP3__V_CMP_T_U16(&iFmt->iFmt_VOP3A);
5338  } // decode_OPU_VOP3__V_CMP_T_U16
5339 
5340  GPUStaticInst*
5342  {
5343  return new Inst_VOP3__V_CMPX_F_I16(&iFmt->iFmt_VOP3A);
5344  } // decode_OPU_VOP3__V_CMPX_F_I16
5345 
5346  GPUStaticInst*
5348  {
5349  return new Inst_VOP3__V_CMPX_LT_I16(&iFmt->iFmt_VOP3A);
5350  } // decode_OPU_VOP3__V_CMPX_LT_I16
5351 
5352  GPUStaticInst*
5354  {
5355  return new Inst_VOP3__V_CMPX_EQ_I16(&iFmt->iFmt_VOP3A);
5356  } // decode_OPU_VOP3__V_CMPX_EQ_I16
5357 
5358  GPUStaticInst*
5360  {
5361  return new Inst_VOP3__V_CMPX_LE_I16(&iFmt->iFmt_VOP3A);
5362  } // decode_OPU_VOP3__V_CMPX_LE_I16
5363 
5364  GPUStaticInst*
5366  {
5367  return new Inst_VOP3__V_CMPX_GT_I16(&iFmt->iFmt_VOP3A);
5368  } // decode_OPU_VOP3__V_CMPX_GT_I16
5369 
5370  GPUStaticInst*
5372  {
5373  return new Inst_VOP3__V_CMPX_NE_I16(&iFmt->iFmt_VOP3A);
5374  } // decode_OPU_VOP3__V_CMPX_NE_I16
5375 
5376  GPUStaticInst*
5378  {
5379  return new Inst_VOP3__V_CMPX_GE_I16(&iFmt->iFmt_VOP3A);
5380  } // decode_OPU_VOP3__V_CMPX_GE_I16
5381 
5382  GPUStaticInst*
5384  {
5385  return new Inst_VOP3__V_CMPX_T_I16(&iFmt->iFmt_VOP3A);
5386  } // decode_OPU_VOP3__V_CMPX_T_I16
5387 
5388  GPUStaticInst*
5390  {
5391  return new Inst_VOP3__V_CMPX_F_U16(&iFmt->iFmt_VOP3A);
5392  } // decode_OPU_VOP3__V_CMPX_F_U16
5393 
5394  GPUStaticInst*
5396  {
5397  return new Inst_VOP3__V_CMPX_LT_U16(&iFmt->iFmt_VOP3A);
5398  } // decode_OPU_VOP3__V_CMPX_LT_U16
5399 
5400  GPUStaticInst*
5402  {
5403  return new Inst_VOP3__V_CMPX_EQ_U16(&iFmt->iFmt_VOP3A);
5404  } // decode_OPU_VOP3__V_CMPX_EQ_U16
5405 
5406  GPUStaticInst*
5408  {
5409  return new Inst_VOP3__V_CMPX_LE_U16(&iFmt->iFmt_VOP3A);
5410  } // decode_OPU_VOP3__V_CMPX_LE_U16
5411 
5412  GPUStaticInst*
5414  {
5415  return new Inst_VOP3__V_CMPX_GT_U16(&iFmt->iFmt_VOP3A);
5416  } // decode_OPU_VOP3__V_CMPX_GT_U16
5417 
5418  GPUStaticInst*
5420  {
5421  return new Inst_VOP3__V_CMPX_NE_U16(&iFmt->iFmt_VOP3A);
5422  } // decode_OPU_VOP3__V_CMPX_NE_U16
5423 
5424  GPUStaticInst*
5426  {
5427  return new Inst_VOP3__V_CMPX_GE_U16(&iFmt->iFmt_VOP3A);
5428  } // decode_OPU_VOP3__V_CMPX_GE_U16
5429 
5430  GPUStaticInst*
5432  {
5433  return new Inst_VOP3__V_CMPX_T_U16(&iFmt->iFmt_VOP3A);
5434  } // decode_OPU_VOP3__V_CMPX_T_U16
5435 
5436  GPUStaticInst*
5438  {
5439  return new Inst_VOP3__V_CMP_F_I32(&iFmt->iFmt_VOP3A);
5440  } // decode_OPU_VOP3__V_CMP_F_I32
5441 
5442  GPUStaticInst*
5444  {
5445  return new Inst_VOP3__V_CMP_LT_I32(&iFmt->iFmt_VOP3A);
5446  } // decode_OPU_VOP3__V_CMP_LT_I32
5447 
5448  GPUStaticInst*
5450  {
5451  return new Inst_VOP3__V_CMP_EQ_I32(&iFmt->iFmt_VOP3A);
5452  } // decode_OPU_VOP3__V_CMP_EQ_I32
5453 
5454  GPUStaticInst*
5456  {
5457  return new Inst_VOP3__V_CMP_LE_I32(&iFmt->iFmt_VOP3A);
5458  } // decode_OPU_VOP3__V_CMP_LE_I32
5459 
5460  GPUStaticInst*
5462  {
5463  return new Inst_VOP3__V_CMP_GT_I32(&iFmt->iFmt_VOP3A);
5464  } // decode_OPU_VOP3__V_CMP_GT_I32
5465 
5466  GPUStaticInst*
5468  {
5469  return new Inst_VOP3__V_CMP_NE_I32(&iFmt->iFmt_VOP3A);
5470  } // decode_OPU_VOP3__V_CMP_NE_I32
5471 
5472  GPUStaticInst*
5474  {
5475  return new Inst_VOP3__V_CMP_GE_I32(&iFmt->iFmt_VOP3A);
5476  } // decode_OPU_VOP3__V_CMP_GE_I32
5477 
5478  GPUStaticInst*
5480  {
5481  return new Inst_VOP3__V_CMP_T_I32(&iFmt->iFmt_VOP3A);
5482  } // decode_OPU_VOP3__V_CMP_T_I32
5483 
5484  GPUStaticInst*
5486  {
5487  return new Inst_VOP3__V_CMP_F_U32(&iFmt->iFmt_VOP3A);
5488  } // decode_OPU_VOP3__V_CMP_F_U32
5489 
5490  GPUStaticInst*
5492  {
5493  return new Inst_VOP3__V_CMP_LT_U32(&iFmt->iFmt_VOP3A);
5494  } // decode_OPU_VOP3__V_CMP_LT_U32
5495 
5496  GPUStaticInst*
5498  {
5499  return new Inst_VOP3__V_CMP_EQ_U32(&iFmt->iFmt_VOP3A);
5500  } // decode_OPU_VOP3__V_CMP_EQ_U32
5501 
5502  GPUStaticInst*
5504  {
5505  return new Inst_VOP3__V_CMP_LE_U32(&iFmt->iFmt_VOP3A);
5506  } // decode_OPU_VOP3__V_CMP_LE_U32
5507 
5508  GPUStaticInst*
5510  {
5511  return new Inst_VOP3__V_CMP_GT_U32(&iFmt->iFmt_VOP3A);
5512  } // decode_OPU_VOP3__V_CMP_GT_U32
5513 
5514  GPUStaticInst*
5516  {
5517  return new Inst_VOP3__V_CMP_NE_U32(&iFmt->iFmt_VOP3A);
5518  } // decode_OPU_VOP3__V_CMP_NE_U32
5519 
5520  GPUStaticInst*
5522  {
5523  return new Inst_VOP3__V_CMP_GE_U32(&iFmt->iFmt_VOP3A);
5524  } // decode_OPU_VOP3__V_CMP_GE_U32
5525 
5526  GPUStaticInst*
5528  {
5529  return new Inst_VOP3__V_CMP_T_U32(&iFmt->iFmt_VOP3A);
5530  } // decode_OPU_VOP3__V_CMP_T_U32
5531 
5532  GPUStaticInst*
5534  {
5535  return new Inst_VOP3__V_CMPX_F_I32(&iFmt->iFmt_VOP3A);
5536  } // decode_OPU_VOP3__V_CMPX_F_I32
5537 
5538  GPUStaticInst*
5540  {
5541  return new Inst_VOP3__V_CMPX_LT_I32(&iFmt->iFmt_VOP3A);
5542  } // decode_OPU_VOP3__V_CMPX_LT_I32
5543 
5544  GPUStaticInst*
5546  {
5547  return new Inst_VOP3__V_CMPX_EQ_I32(&iFmt->iFmt_VOP3A);
5548  } // decode_OPU_VOP3__V_CMPX_EQ_I32
5549 
5550  GPUStaticInst*
5552  {
5553  return new Inst_VOP3__V_CMPX_LE_I32(&iFmt->iFmt_VOP3A);
5554  } // decode_OPU_VOP3__V_CMPX_LE_I32
5555 
5556  GPUStaticInst*
5558  {
5559  return new Inst_VOP3__V_CMPX_GT_I32(&iFmt->iFmt_VOP3A);
5560  } // decode_OPU_VOP3__V_CMPX_GT_I32
5561 
5562  GPUStaticInst*
5564  {
5565  return new Inst_VOP3__V_CMPX_NE_I32(&iFmt->iFmt_VOP3A);
5566  } // decode_OPU_VOP3__V_CMPX_NE_I32
5567 
5568  GPUStaticInst*
5570  {
5571  return new Inst_VOP3__V_CMPX_GE_I32(&iFmt->iFmt_VOP3A);
5572  } // decode_OPU_VOP3__V_CMPX_GE_I32
5573 
5574  GPUStaticInst*
5576  {
5577  return new Inst_VOP3__V_CMPX_T_I32(&iFmt->iFmt_VOP3A);
5578  } // decode_OPU_VOP3__V_CMPX_T_I32
5579 
5580  GPUStaticInst*
5582  {
5583  return new Inst_VOP3__V_CMPX_F_U32(&iFmt->iFmt_VOP3A);
5584  } // decode_OPU_VOP3__V_CMPX_F_U32
5585 
5586  GPUStaticInst*
5588  {
5589  return new Inst_VOP3__V_CMPX_LT_U32(&iFmt->iFmt_VOP3A);
5590  } // decode_OPU_VOP3__V_CMPX_LT_U32
5591 
5592  GPUStaticInst*
5594  {
5595  return new Inst_VOP3__V_CMPX_EQ_U32(&iFmt->iFmt_VOP3A);
5596  } // decode_OPU_VOP3__V_CMPX_EQ_U32
5597 
5598  GPUStaticInst*
5600  {
5601  return new Inst_VOP3__V_CMPX_LE_U32(&iFmt->iFmt_VOP3A);
5602  } // decode_OPU_VOP3__V_CMPX_LE_U32
5603 
5604  GPUStaticInst*
5606  {
5607  return new Inst_VOP3__V_CMPX_GT_U32(&iFmt->iFmt_VOP3A);
5608  } // decode_OPU_VOP3__V_CMPX_GT_U32
5609 
5610  GPUStaticInst*
5612  {
5613  return new Inst_VOP3__V_CMPX_NE_U32(&iFmt->iFmt_VOP3A);
5614  } // decode_OPU_VOP3__V_CMPX_NE_U32
5615 
5616  GPUStaticInst*
5618  {
5619  return new Inst_VOP3__V_CMPX_GE_U32(&iFmt->iFmt_VOP3A);
5620  } // decode_OPU_VOP3__V_CMPX_GE_U32
5621 
5622  GPUStaticInst*
5624  {
5625  return new Inst_VOP3__V_CMPX_T_U32(&iFmt->iFmt_VOP3A);
5626  } // decode_OPU_VOP3__V_CMPX_T_U32
5627 
5628  GPUStaticInst*
5630  {
5631  return new Inst_VOP3__V_CMP_F_I64(&iFmt->iFmt_VOP3A);
5632  } // decode_OPU_VOP3__V_CMP_F_I64
5633 
5634  GPUStaticInst*
5636  {
5637  return new Inst_VOP3__V_CMP_LT_I64(&iFmt->iFmt_VOP3A);
5638  } // decode_OPU_VOP3__V_CMP_LT_I64
5639 
5640  GPUStaticInst*
5642  {
5643  return new Inst_VOP3__V_CMP_EQ_I64(&iFmt->iFmt_VOP3A);
5644  } // decode_OPU_VOP3__V_CMP_EQ_I64
5645 
5646  GPUStaticInst*
5648  {
5649  return new Inst_VOP3__V_CMP_LE_I64(&iFmt->iFmt_VOP3A);
5650  } // decode_OPU_VOP3__V_CMP_LE_I64
5651 
5652  GPUStaticInst*
5654  {
5655  return new Inst_VOP3__V_CMP_GT_I64(&iFmt->iFmt_VOP3A);
5656  } // decode_OPU_VOP3__V_CMP_GT_I64
5657 
5658  GPUStaticInst*
5660  {
5661  return new Inst_VOP3__V_CMP_NE_I64(&iFmt->iFmt_VOP3A);
5662  } // decode_OPU_VOP3__V_CMP_NE_I64
5663 
5664  GPUStaticInst*
5666  {
5667  return new Inst_VOP3__V_CMP_GE_I64(&iFmt->iFmt_VOP3A);
5668  } // decode_OPU_VOP3__V_CMP_GE_I64
5669 
5670  GPUStaticInst*
5672  {
5673  return new Inst_VOP3__V_CMP_T_I64(&iFmt->iFmt_VOP3A);
5674  } // decode_OPU_VOP3__V_CMP_T_I64
5675 
5676  GPUStaticInst*
5678  {
5679  return new Inst_VOP3__V_CMP_F_U64(&iFmt->iFmt_VOP3A);
5680  } // decode_OPU_VOP3__V_CMP_F_U64
5681 
5682  GPUStaticInst*
5684  {
5685  return new Inst_VOP3__V_CMP_LT_U64(&iFmt->iFmt_VOP3A);
5686  } // decode_OPU_VOP3__V_CMP_LT_U64
5687 
5688  GPUStaticInst*
5690  {
5691  return new Inst_VOP3__V_CMP_EQ_U64(&iFmt->iFmt_VOP3A);
5692  } // decode_OPU_VOP3__V_CMP_EQ_U64
5693 
5694  GPUStaticInst*
5696  {
5697  return new Inst_VOP3__V_CMP_LE_U64(&iFmt->iFmt_VOP3A);
5698  } // decode_OPU_VOP3__V_CMP_LE_U64
5699 
5700  GPUStaticInst*
5702  {
5703  return new Inst_VOP3__V_CMP_GT_U64(&iFmt->iFmt_VOP3A);
5704  } // decode_OPU_VOP3__V_CMP_GT_U64
5705 
5706  GPUStaticInst*
5708  {
5709  return new Inst_VOP3__V_CMP_NE_U64(&iFmt->iFmt_VOP3A);
5710  } // decode_OPU_VOP3__V_CMP_NE_U64
5711 
5712  GPUStaticInst*
5714  {
5715  return new Inst_VOP3__V_CMP_GE_U64(&iFmt->iFmt_VOP3A);
5716  } // decode_OPU_VOP3__V_CMP_GE_U64
5717 
5718  GPUStaticInst*
5720  {
5721  return new Inst_VOP3__V_CMP_T_U64(&iFmt->iFmt_VOP3A);
5722  } // decode_OPU_VOP3__V_CMP_T_U64
5723 
5724  GPUStaticInst*
5726  {
5727  return new Inst_VOP3__V_CMPX_F_I64(&iFmt->iFmt_VOP3A);
5728  } // decode_OPU_VOP3__V_CMPX_F_I64
5729 
5730  GPUStaticInst*
5732  {
5733  return new Inst_VOP3__V_CMPX_LT_I64(&iFmt->iFmt_VOP3A);
5734  } // decode_OPU_VOP3__V_CMPX_LT_I64
5735 
5736  GPUStaticInst*
5738  {
5739  return new Inst_VOP3__V_CMPX_EQ_I64(&iFmt->iFmt_VOP3A);
5740  } // decode_OPU_VOP3__V_CMPX_EQ_I64
5741 
5742  GPUStaticInst*
5744  {
5745  return new Inst_VOP3__V_CMPX_LE_I64(&iFmt->iFmt_VOP3A);
5746  } // decode_OPU_VOP3__V_CMPX_LE_I64
5747 
5748  GPUStaticInst*
5750  {
5751  return new Inst_VOP3__V_CMPX_GT_I64(&iFmt->iFmt_VOP3A);
5752  } // decode_OPU_VOP3__V_CMPX_GT_I64
5753 
5754  GPUStaticInst*
5756  {
5757  return new Inst_VOP3__V_CMPX_NE_I64(&iFmt->iFmt_VOP3A);
5758  } // decode_OPU_VOP3__V_CMPX_NE_I64
5759 
5760  GPUStaticInst*
5762  {
5763  return new Inst_VOP3__V_CMPX_GE_I64(&iFmt->iFmt_VOP3A);
5764  } // decode_OPU_VOP3__V_CMPX_GE_I64
5765 
5766  GPUStaticInst*
5768  {
5769  return new Inst_VOP3__V_CMPX_T_I64(&iFmt->iFmt_VOP3A);
5770  } // decode_OPU_VOP3__V_CMPX_T_I64
5771 
5772  GPUStaticInst*
5774  {
5775  return new Inst_VOP3__V_CMPX_F_U64(&iFmt->iFmt_VOP3A);
5776  } // decode_OPU_VOP3__V_CMPX_F_U64
5777 
5778  GPUStaticInst*
5780  {
5781  return new Inst_VOP3__V_CMPX_LT_U64(&iFmt->iFmt_VOP3A);
5782  } // decode_OPU_VOP3__V_CMPX_LT_U64
5783 
5784  GPUStaticInst*
5786  {
5787  return new Inst_VOP3__V_CMPX_EQ_U64(&iFmt->iFmt_VOP3A);
5788  } // decode_OPU_VOP3__V_CMPX_EQ_U64
5789 
5790  GPUStaticInst*
5792  {
5793  return new Inst_VOP3__V_CMPX_LE_U64(&iFmt->iFmt_VOP3A);
5794  } // decode_OPU_VOP3__V_CMPX_LE_U64
5795 
5796  GPUStaticInst*
5798  {
5799  return new Inst_VOP3__V_CMPX_GT_U64(&iFmt->iFmt_VOP3A);
5800  } // decode_OPU_VOP3__V_CMPX_GT_U64
5801 
5802  GPUStaticInst*
5804  {
5805  return new Inst_VOP3__V_CMPX_NE_U64(&iFmt->iFmt_VOP3A);
5806  } // decode_OPU_VOP3__V_CMPX_NE_U64
5807 
5808  GPUStaticInst*
5810  {
5811  return new Inst_VOP3__V_CMPX_GE_U64(&iFmt->iFmt_VOP3A);
5812  } // decode_OPU_VOP3__V_CMPX_GE_U64
5813 
5814  GPUStaticInst*
5816  {
5817  return new Inst_VOP3__V_CMPX_T_U64(&iFmt->iFmt_VOP3A);
5818  } // decode_OPU_VOP3__V_CMPX_T_U64
5819 
5820  GPUStaticInst*
5822  {
5823  return new Inst_VOP3__V_CNDMASK_B32(&iFmt->iFmt_VOP3A);
5824  } // decode_OPU_VOP3__V_CNDMASK_B32
5825 
5826  GPUStaticInst*
5828  {
5829  return new Inst_VOP3__V_ADD_F32(&iFmt->iFmt_VOP3A);
5830  } // decode_OPU_VOP3__V_ADD_F32
5831 
5832  GPUStaticInst*
5834  {
5835  return new Inst_VOP3__V_SUB_F32(&iFmt->iFmt_VOP3A);
5836  } // decode_OPU_VOP3__V_SUB_F32
5837 
5838  GPUStaticInst*
5840  {
5841  return new Inst_VOP3__V_SUBREV_F32(&iFmt->iFmt_VOP3A);
5842  } // decode_OPU_VOP3__V_SUBREV_F32
5843 
5844  GPUStaticInst*
5846  {
5847  return new Inst_VOP3__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP3A);
5848  } // decode_OPU_VOP3__V_MUL_LEGACY_F32
5849 
5850  GPUStaticInst*
5852  {
5853  return new Inst_VOP3__V_MUL_F32(&iFmt->iFmt_VOP3A);
5854  } // decode_OPU_VOP3__V_MUL_F32
5855 
5856  GPUStaticInst*
5858  {
5859  return new Inst_VOP3__V_MUL_I32_I24(&iFmt->iFmt_VOP3A);
5860  } // decode_OPU_VOP3__V_MUL_I32_I24
5861 
5862  GPUStaticInst*
5864  {
5865  return new Inst_VOP3__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP3A);
5866  } // decode_OPU_VOP3__V_MUL_HI_I32_I24
5867 
5868  GPUStaticInst*
5870  {
5871  return new Inst_VOP3__V_MUL_U32_U24(&iFmt->iFmt_VOP3A);
5872  } // decode_OPU_VOP3__V_MUL_U32_U24
5873 
5874  GPUStaticInst*
5876  {
5877  return new Inst_VOP3__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP3A);
5878  } // decode_OPU_VOP3__V_MUL_HI_U32_U24
5879 
5880  GPUStaticInst*
5882  {
5883  return new Inst_VOP3__V_MIN_F32(&iFmt->iFmt_VOP3A);
5884  } // decode_OPU_VOP3__V_MIN_F32
5885 
5886  GPUStaticInst*
5888  {
5889  return new Inst_VOP3__V_MAX_F32(&iFmt->iFmt_VOP3A);
5890  } // decode_OPU_VOP3__V_MAX_F32
5891 
5892  GPUStaticInst*
5894  {
5895  return new Inst_VOP3__V_MIN_I32(&iFmt->iFmt_VOP3A);
5896  } // decode_OPU_VOP3__V_MIN_I32
5897 
5898  GPUStaticInst*
5900  {
5901  return new Inst_VOP3__V_MAX_I32(&iFmt->iFmt_VOP3A);
5902  } // decode_OPU_VOP3__V_MAX_I32
5903 
5904  GPUStaticInst*
5906  {
5907  return new Inst_VOP3__V_MIN_U32(&iFmt->iFmt_VOP3A);
5908  } // decode_OPU_VOP3__V_MIN_U32
5909 
5910  GPUStaticInst*
5912  {
5913  return new Inst_VOP3__V_MAX_U32(&iFmt->iFmt_VOP3A);
5914  } // decode_OPU_VOP3__V_MAX_U32
5915 
5916  GPUStaticInst*
5918  {
5919  return new Inst_VOP3__V_LSHRREV_B32(&iFmt->iFmt_VOP3A);
5920  } // decode_OPU_VOP3__V_LSHRREV_B32
5921 
5922  GPUStaticInst*
5924  {
5925  return new Inst_VOP3__V_ASHRREV_I32(&iFmt->iFmt_VOP3A);
5926  } // decode_OPU_VOP3__V_ASHRREV_I32
5927 
5928  GPUStaticInst*
5930  {
5931  return new Inst_VOP3__V_LSHLREV_B32(&iFmt->iFmt_VOP3A);
5932  } // decode_OPU_VOP3__V_LSHLREV_B32
5933 
5934  GPUStaticInst*
5936  {
5937  return new Inst_VOP3__V_AND_B32(&iFmt->iFmt_VOP3A);
5938  } // decode_OPU_VOP3__V_AND_B32
5939 
5940  GPUStaticInst*
5942  {
5943  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
5944  } // decode_OPU_VOP3__V_OR_B32
5945 
5946  GPUStaticInst*
5948  {
5949  return new Inst_VOP3__V_XOR_B32(&iFmt->iFmt_VOP3A);
5950  } // decode_OPU_VOP3__V_XOR_B32
5951 
5952  GPUStaticInst*
5954  {
5955  return new Inst_VOP3__V_MAC_F32(&iFmt->iFmt_VOP3A);
5956  } // decode_OPU_VOP3__V_MAC_F32
5957 
5958  GPUStaticInst*
5960  {
5961  return new Inst_VOP3__V_ADD_CO_U32(&iFmt->iFmt_VOP3B);
5962  } // decode_OPU_VOP3__V_ADD_CO_U32
5963 
5964  GPUStaticInst*
5966  {
5967  return new Inst_VOP3__V_SUB_CO_U32(&iFmt->iFmt_VOP3B);
5968  } // decode_OPU_VOP3__V_SUB_CO_U32
5969 
5970  GPUStaticInst*
5972  {
5973  return new Inst_VOP3__V_SUBREV_CO_U32(&iFmt->iFmt_VOP3B);
5974  } // decode_OPU_VOP3__V_SUBREV_CO_U32
5975 
5976  GPUStaticInst*
5978  {
5979  return new Inst_VOP3__V_ADDC_CO_U32(&iFmt->iFmt_VOP3B);
5980  } // decode_OPU_VOP3__V_ADDC_CO_U32
5981 
5982  GPUStaticInst*
5984  {
5985  return new Inst_VOP3__V_SUBB_CO_U32(&iFmt->iFmt_VOP3B);
5986  } // decode_OPU_VOP3__V_SUBB_CO_U32
5987 
5988  GPUStaticInst*
5990  {
5991  return new Inst_VOP3__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP3B);
5992  } // decode_OPU_VOP3__V_SUBBREV_CO_U32
5993 
5994  GPUStaticInst*
5996  {
5997  return new Inst_VOP3__V_ADD_F16(&iFmt->iFmt_VOP3A);
5998  } // decode_OPU_VOP3__V_ADD_F16
5999 
6000  GPUStaticInst*
6002  {
6003  return new Inst_VOP3__V_SUB_F16(&iFmt->iFmt_VOP3A);
6004  } // decode_OPU_VOP3__V_SUB_F16
6005 
6006  GPUStaticInst*
6008  {
6009  return new Inst_VOP3__V_SUBREV_F16(&iFmt->iFmt_VOP3A);
6010  } // decode_OPU_VOP3__V_SUBREV_F16
6011 
6012  GPUStaticInst*
6014  {
6015  return new Inst_VOP3__V_MUL_F16(&iFmt->iFmt_VOP3A);
6016  } // decode_OPU_VOP3__V_MUL_F16
6017 
6018  GPUStaticInst*
6020  {
6021  return new Inst_VOP3__V_MAC_F16(&iFmt->iFmt_VOP3A);
6022  } // decode_OPU_VOP3__V_MAC_F16
6023 
6024  GPUStaticInst*
6026  {
6027  return new Inst_VOP3__V_ADD_U16(&iFmt->iFmt_VOP3A);
6028  } // decode_OPU_VOP3__V_ADD_U16
6029 
6030  GPUStaticInst*
6032  {
6033  return new Inst_VOP3__V_SUB_U16(&iFmt->iFmt_VOP3A);
6034  } // decode_OPU_VOP3__V_SUB_U16
6035 
6036  GPUStaticInst*
6038  {
6039  return new Inst_VOP3__V_SUBREV_U16(&iFmt->iFmt_VOP3A);
6040  } // decode_OPU_VOP3__V_SUBREV_U16
6041 
6042  GPUStaticInst*
6044  {
6045  return new Inst_VOP3__V_MUL_LO_U16(&iFmt->iFmt_VOP3A);
6046  } // decode_OPU_VOP3__V_MUL_LO_U16
6047 
6048  GPUStaticInst*
6050  {
6051  return new Inst_VOP3__V_LSHLREV_B16(&iFmt->iFmt_VOP3A);
6052  } // decode_OPU_VOP3__V_LSHLREV_B16
6053 
6054  GPUStaticInst*
6056  {
6057  return new Inst_VOP3__V_LSHRREV_B16(&iFmt->iFmt_VOP3A);
6058  } // decode_OPU_VOP3__V_LSHRREV_B16
6059 
6060  GPUStaticInst*
6062  {
6063  return new Inst_VOP3__V_ASHRREV_I16(&iFmt->iFmt_VOP3A);
6064  } // decode_OPU_VOP3__V_ASHRREV_I16
6065 
6066  GPUStaticInst*
6068  {
6069  return new Inst_VOP3__V_MAX_F16(&iFmt->iFmt_VOP3A);
6070  } // decode_OPU_VOP3__V_MAX_F16
6071 
6072  GPUStaticInst*
6074  {
6075  return new Inst_VOP3__V_MIN_F16(&iFmt->iFmt_VOP3A);
6076  } // decode_OPU_VOP3__V_MIN_F16
6077 
6078  GPUStaticInst*
6080  {
6081  return new Inst_VOP3__V_MAX_U16(&iFmt->iFmt_VOP3A);
6082  } // decode_OPU_VOP3__V_MAX_U16
6083 
6084  GPUStaticInst*
6086  {
6087  return new Inst_VOP3__V_MAX_I16(&iFmt->iFmt_VOP3A);
6088  } // decode_OPU_VOP3__V_MAX_I16
6089 
6090  GPUStaticInst*
6092  {
6093  return new Inst_VOP3__V_MIN_U16(&iFmt->iFmt_VOP3A);
6094  } // decode_OPU_VOP3__V_MIN_U16
6095 
6096  GPUStaticInst*
6098  {
6099  return new Inst_VOP3__V_MIN_I16(&iFmt->iFmt_VOP3A);
6100  } // decode_OPU_VOP3__V_MIN_I16
6101 
6102  GPUStaticInst*
6104  {
6105  return new Inst_VOP3__V_LDEXP_F16(&iFmt->iFmt_VOP3A);
6106  } // decode_OPU_VOP3__V_LDEXP_F16
6107 
6108  GPUStaticInst*
6110  {
6111  return new Inst_VOP3__V_NOP(&iFmt->iFmt_VOP3A);
6112  } // decode_OPU_VOP3__V_NOP
6113 
6114  GPUStaticInst*
6116  {
6117  return new Inst_VOP3__V_MOV_B32(&iFmt->iFmt_VOP3A);
6118  } // decode_OPU_VOP3__V_MOV_B32
6119 
6120  GPUStaticInst*
6122  {
6123  return new Inst_VOP3__V_CVT_I32_F64(&iFmt->iFmt_VOP3A);
6124  } // decode_OPU_VOP3__V_CVT_I32_F64
6125 
6126  GPUStaticInst*
6128  {
6129  return new Inst_VOP3__V_CVT_F64_I32(&iFmt->iFmt_VOP3A);
6130  } // decode_OPU_VOP3__V_CVT_F64_I32
6131 
6132  GPUStaticInst*
6134  {
6135  return new Inst_VOP3__V_CVT_F32_I32(&iFmt->iFmt_VOP3A);
6136  } // decode_OPU_VOP3__V_CVT_F32_I32
6137 
6138  GPUStaticInst*
6140  {
6141  return new Inst_VOP3__V_CVT_F32_U32(&iFmt->iFmt_VOP3A);
6142  } // decode_OPU_VOP3__V_CVT_F32_U32
6143 
6144  GPUStaticInst*
6146  {
6147  return new Inst_VOP3__V_CVT_U32_F32(&iFmt->iFmt_VOP3A);
6148  } // decode_OPU_VOP3__V_CVT_U32_F32
6149 
6150  GPUStaticInst*
6152  {
6153  return new Inst_VOP3__V_CVT_I32_F32(&iFmt->iFmt_VOP3A);
6154  } // decode_OPU_VOP3__V_CVT_I32_F32
6155 
6156  GPUStaticInst*
6158  {
6159  return new Inst_VOP3__V_MOV_FED_B32(&iFmt->iFmt_VOP3A);
6160  } // decode_OPU_VOP3__V_MOV_FED_B32
6161 
6162  GPUStaticInst*
6164  {
6165  return new Inst_VOP3__V_CVT_F16_F32(&iFmt->iFmt_VOP3A);
6166  } // decode_OPU_VOP3__V_CVT_F16_F32
6167 
6168  GPUStaticInst*
6170  {
6171  return new Inst_VOP3__V_CVT_F32_F16(&iFmt->iFmt_VOP3A);
6172  } // decode_OPU_VOP3__V_CVT_F32_F16
6173 
6174  GPUStaticInst*
6176  {
6177  return new Inst_VOP3__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP3A);
6178  } // decode_OPU_VOP3__V_CVT_RPI_I32_F32
6179 
6180  GPUStaticInst*
6182  {
6183  return new Inst_VOP3__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP3A);
6184  } // decode_OPU_VOP3__V_CVT_FLR_I32_F32
6185 
6186  GPUStaticInst*
6188  {
6189  return new Inst_VOP3__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP3A);
6190  } // decode_OPU_VOP3__V_CVT_OFF_F32_I4
6191 
6192  GPUStaticInst*
6194  {
6195  return new Inst_VOP3__V_CVT_F32_F64(&iFmt->iFmt_VOP3A);
6196  } // decode_OPU_VOP3__V_CVT_F32_F64
6197 
6198  GPUStaticInst*
6200  {
6201  return new Inst_VOP3__V_CVT_F64_F32(&iFmt->iFmt_VOP3A);
6202  } // decode_OPU_VOP3__V_CVT_F64_F32
6203 
6204  GPUStaticInst*
6206  {
6207  return new Inst_VOP3__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP3A);
6208  } // decode_OPU_VOP3__V_CVT_F32_UBYTE0
6209 
6210  GPUStaticInst*
6212  {
6213  return new Inst_VOP3__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP3A);
6214  } // decode_OPU_VOP3__V_CVT_F32_UBYTE1
6215 
6216  GPUStaticInst*
6218  {
6219  return new Inst_VOP3__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP3A);
6220  } // decode_OPU_VOP3__V_CVT_F32_UBYTE2
6221 
6222  GPUStaticInst*
6224  {
6225  return new Inst_VOP3__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP3A);
6226  } // decode_OPU_VOP3__V_CVT_F32_UBYTE3
6227 
6228  GPUStaticInst*
6230  {
6231  return new Inst_VOP3__V_CVT_U32_F64(&iFmt->iFmt_VOP3A);
6232  } // decode_OPU_VOP3__V_CVT_U32_F64
6233 
6234  GPUStaticInst*
6236  {
6237  return new Inst_VOP3__V_CVT_F64_U32(&iFmt->iFmt_VOP3A);
6238  } // decode_OPU_VOP3__V_CVT_F64_U32
6239 
6240  GPUStaticInst*
6242  {
6243  return new Inst_VOP3__V_TRUNC_F64(&iFmt->iFmt_VOP3A);
6244  } // decode_OPU_VOP3__V_TRUNC_F64
6245 
6246  GPUStaticInst*
6248  {
6249  return new Inst_VOP3__V_CEIL_F64(&iFmt->iFmt_VOP3A);
6250  } // decode_OPU_VOP3__V_CEIL_F64
6251 
6252  GPUStaticInst*
6254  {
6255  return new Inst_VOP3__V_RNDNE_F64(&iFmt->iFmt_VOP3A);
6256  } // decode_OPU_VOP3__V_RNDNE_F64
6257 
6258  GPUStaticInst*
6260  {
6261  return new Inst_VOP3__V_FLOOR_F64(&iFmt->iFmt_VOP3A);
6262  } // decode_OPU_VOP3__V_FLOOR_F64
6263 
6264  GPUStaticInst*
6266  {
6267  return new Inst_VOP3__V_FRACT_F32(&iFmt->iFmt_VOP3A);
6268  } // decode_OPU_VOP3__V_FRACT_F32
6269 
6270  GPUStaticInst*
6272  {
6273  return new Inst_VOP3__V_TRUNC_F32(&iFmt->iFmt_VOP3A);
6274  } // decode_OPU_VOP3__V_TRUNC_F32
6275 
6276  GPUStaticInst*
6278  {
6279  return new Inst_VOP3__V_CEIL_F32(&iFmt->iFmt_VOP3A);
6280  } // decode_OPU_VOP3__V_CEIL_F32
6281 
6282  GPUStaticInst*
6284  {
6285  return new Inst_VOP3__V_RNDNE_F32(&iFmt->iFmt_VOP3A);
6286  } // decode_OPU_VOP3__V_RNDNE_F32
6287 
6288  GPUStaticInst*
6290  {
6291  return new Inst_VOP3__V_FLOOR_F32(&iFmt->iFmt_VOP3A);
6292  } // decode_OPU_VOP3__V_FLOOR_F32
6293 
6294  GPUStaticInst*
6296  {
6297  return new Inst_VOP3__V_EXP_F32(&iFmt->iFmt_VOP3A);
6298  } // decode_OPU_VOP3__V_EXP_F32
6299 
6300  GPUStaticInst*
6302  {
6303  return new Inst_VOP3__V_LOG_F32(&iFmt->iFmt_VOP3A);
6304  } // decode_OPU_VOP3__V_LOG_F32
6305 
6306  GPUStaticInst*
6308  {
6309  return new Inst_VOP3__V_RCP_F32(&iFmt->iFmt_VOP3A);
6310  } // decode_OPU_VOP3__V_RCP_F32
6311 
6312  GPUStaticInst*
6314  {
6315  return new Inst_VOP3__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP3A);
6316  } // decode_OPU_VOP3__V_RCP_IFLAG_F32
6317 
6318  GPUStaticInst*
6320  {
6321  return new Inst_VOP3__V_RSQ_F32(&iFmt->iFmt_VOP3A);
6322  } // decode_OPU_VOP3__V_RSQ_F32
6323 
6324  GPUStaticInst*
6326  {
6327  return new Inst_VOP3__V_RCP_F64(&iFmt->iFmt_VOP3A);
6328  } // decode_OPU_VOP3__V_RCP_F64
6329 
6330  GPUStaticInst*
6332  {
6333  return new Inst_VOP3__V_RSQ_F64(&iFmt->iFmt_VOP3A);
6334  } // decode_OPU_VOP3__V_RSQ_F64
6335 
6336  GPUStaticInst*
6338  {
6339  return new Inst_VOP3__V_SQRT_F32(&iFmt->iFmt_VOP3A);
6340  } // decode_OPU_VOP3__V_SQRT_F32
6341 
6342  GPUStaticInst*
6344  {
6345  return new Inst_VOP3__V_SQRT_F64(&iFmt->iFmt_VOP3A);
6346  } // decode_OPU_VOP3__V_SQRT_F64
6347 
6348  GPUStaticInst*
6350  {
6351  return new Inst_VOP3__V_SIN_F32(&iFmt->iFmt_VOP3A);
6352  } // decode_OPU_VOP3__V_SIN_F32
6353 
6354  GPUStaticInst*
6356  {
6357  return new Inst_VOP3__V_COS_F32(&iFmt->iFmt_VOP3A);
6358  } // decode_OPU_VOP3__V_COS_F32
6359 
6360  GPUStaticInst*
6362  {
6363  return new Inst_VOP3__V_NOT_B32(&iFmt->iFmt_VOP3A);
6364  } // decode_OPU_VOP3__V_NOT_B32
6365 
6366  GPUStaticInst*
6368  {
6369  return new Inst_VOP3__V_BFREV_B32(&iFmt->iFmt_VOP3A);
6370  } // decode_OPU_VOP3__V_BFREV_B32
6371 
6372  GPUStaticInst*
6374  {
6375  return new Inst_VOP3__V_FFBH_U32(&iFmt->iFmt_VOP3A);
6376  } // decode_OPU_VOP3__V_FFBH_U32
6377 
6378  GPUStaticInst*
6380  {
6381  return new Inst_VOP3__V_FFBL_B32(&iFmt->iFmt_VOP3A);
6382  } // decode_OPU_VOP3__V_FFBL_B32
6383 
6384  GPUStaticInst*
6386  {
6387  return new Inst_VOP3__V_FFBH_I32(&iFmt->iFmt_VOP3A);
6388  } // decode_OPU_VOP3__V_FFBH_I32
6389 
6390  GPUStaticInst*
6392  {
6393  return new Inst_VOP3__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP3A);
6394  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F64
6395 
6396  GPUStaticInst*
6398  {
6399  return new Inst_VOP3__V_FREXP_MANT_F64(&iFmt->iFmt_VOP3A);
6400  } // decode_OPU_VOP3__V_FREXP_MANT_F64
6401 
6402  GPUStaticInst*
6404  {
6405  return new Inst_VOP3__V_FRACT_F64(&iFmt->iFmt_VOP3A);
6406  } // decode_OPU_VOP3__V_FRACT_F64
6407 
6408  GPUStaticInst*
6410  {
6411  return new Inst_VOP3__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP3A);
6412  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F32
6413 
6414  GPUStaticInst*
6416  {
6417  return new Inst_VOP3__V_FREXP_MANT_F32(&iFmt->iFmt_VOP3A);
6418  } // decode_OPU_VOP3__V_FREXP_MANT_F32
6419 
6420  GPUStaticInst*
6422  {
6423  return new Inst_VOP3__V_CLREXCP(&iFmt->iFmt_VOP3A);
6424  } // decode_OPU_VOP3__V_CLREXCP
6425 
6426  GPUStaticInst*
6428  {
6429  return new Inst_VOP3__V_CVT_F16_U16(&iFmt->iFmt_VOP3A);
6430  } // decode_OPU_VOP3__V_CVT_F16_U16
6431 
6432  GPUStaticInst*
6434  {
6435  return new Inst_VOP3__V_CVT_F16_I16(&iFmt->iFmt_VOP3A);
6436  } // decode_OPU_VOP3__V_CVT_F16_I16
6437 
6438  GPUStaticInst*
6440  {
6441  return new Inst_VOP3__V_CVT_U16_F16(&iFmt->iFmt_VOP3A);
6442  } // decode_OPU_VOP3__V_CVT_U16_F16
6443 
6444  GPUStaticInst*
6446  {
6447  return new Inst_VOP3__V_CVT_I16_F16(&iFmt->iFmt_VOP3A);
6448  } // decode_OPU_VOP3__V_CVT_I16_F16
6449 
6450  GPUStaticInst*
6452  {
6453  return new Inst_VOP3__V_RCP_F16(&iFmt->iFmt_VOP3A);
6454  } // decode_OPU_VOP3__V_RCP_F16
6455 
6456  GPUStaticInst*
6458  {
6459  return new Inst_VOP3__V_SQRT_F16(&iFmt->iFmt_VOP3A);
6460  } // decode_OPU_VOP3__V_SQRT_F16
6461 
6462  GPUStaticInst*
6464  {
6465  return new Inst_VOP3__V_RSQ_F16(&iFmt->iFmt_VOP3A);
6466  } // decode_OPU_VOP3__V_RSQ_F16
6467 
6468  GPUStaticInst*
6470  {
6471  return new Inst_VOP3__V_LOG_F16(&iFmt->iFmt_VOP3A);
6472  } // decode_OPU_VOP3__V_LOG_F16
6473 
6474  GPUStaticInst*
6476  {
6477  return new Inst_VOP3__V_EXP_F16(&iFmt->iFmt_VOP3A);
6478  } // decode_OPU_VOP3__V_EXP_F16
6479 
6480  GPUStaticInst*
6482  {
6483  return new Inst_VOP3__V_FREXP_MANT_F16(&iFmt->iFmt_VOP3A);
6484  } // decode_OPU_VOP3__V_FREXP_MANT_F16
6485 
6486  GPUStaticInst*
6488  {
6489  return new Inst_VOP3__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP3A);
6490  } // decode_OPU_VOP3__V_FREXP_EXP_I16_F16
6491 
6492  GPUStaticInst*
6494  {
6495  return new Inst_VOP3__V_FLOOR_F16(&iFmt->iFmt_VOP3A);
6496  } // decode_OPU_VOP3__V_FLOOR_F16
6497 
6498  GPUStaticInst*
6500  {
6501  return new Inst_VOP3__V_CEIL_F16(&iFmt->iFmt_VOP3A);
6502  } // decode_OPU_VOP3__V_CEIL_F16
6503 
6504  GPUStaticInst*
6506  {
6507  return new Inst_VOP3__V_TRUNC_F16(&iFmt->iFmt_VOP3A);
6508  } // decode_OPU_VOP3__V_TRUNC_F16
6509 
6510  GPUStaticInst*
6512  {
6513  return new Inst_VOP3__V_RNDNE_F16(&iFmt->iFmt_VOP3A);
6514  } // decode_OPU_VOP3__V_RNDNE_F16
6515 
6516  GPUStaticInst*
6518  {
6519  return new Inst_VOP3__V_FRACT_F16(&iFmt->iFmt_VOP3A);
6520  } // decode_OPU_VOP3__V_FRACT_F16
6521 
6522  GPUStaticInst*
6524  {
6525  return new Inst_VOP3__V_SIN_F16(&iFmt->iFmt_VOP3A);
6526  } // decode_OPU_VOP3__V_SIN_F16
6527 
6528  GPUStaticInst*
6530  {
6531  return new Inst_VOP3__V_COS_F16(&iFmt->iFmt_VOP3A);
6532  } // decode_OPU_VOP3__V_COS_F16
6533 
6534  GPUStaticInst*
6536  {
6537  return new Inst_VOP3__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP3A);
6538  } // decode_OPU_VOP3__V_EXP_LEGACY_F32
6539 
6540  GPUStaticInst*
6542  {
6543  return new Inst_VOP3__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP3A);
6544  } // decode_OPU_VOP3__V_LOG_LEGACY_F32
6545 
6546  GPUStaticInst*
6548  {
6549  return new Inst_VOP3__V_MAD_LEGACY_F32(&iFmt->iFmt_VOP3A);
6550  } // decode_OPU_VOP3__V_MAD_LEGACY_F32
6551 
6552  GPUStaticInst*
6554  {
6555  return new Inst_VOP3__V_MAD_F32(&iFmt->iFmt_VOP3A);
6556  } // decode_OPU_VOP3__V_MAD_F32
6557 
6558  GPUStaticInst*
6560  {
6561  return new Inst_VOP3__V_MAD_I32_I24(&iFmt->iFmt_VOP3A);
6562  } // decode_OPU_VOP3__V_MAD_I32_I24
6563 
6564  GPUStaticInst*
6566  {
6567  return new Inst_VOP3__V_MAD_U32_U24(&iFmt->iFmt_VOP3A);
6568  } // decode_OPU_VOP3__V_MAD_U32_U24
6569 
6570  GPUStaticInst*
6572  {
6573  return new Inst_VOP3__V_CUBEID_F32(&iFmt->iFmt_VOP3A);
6574  } // decode_OPU_VOP3__V_CUBEID_F32
6575 
6576  GPUStaticInst*
6578  {
6579  return new Inst_VOP3__V_CUBESC_F32(&iFmt->iFmt_VOP3A);
6580  } // decode_OPU_VOP3__V_CUBESC_F32
6581 
6582  GPUStaticInst*
6584  {
6585  return new Inst_VOP3__V_CUBETC_F32(&iFmt->iFmt_VOP3A);
6586  } // decode_OPU_VOP3__V_CUBETC_F32
6587 
6588  GPUStaticInst*
6590  {
6591  return new Inst_VOP3__V_CUBEMA_F32(&iFmt->iFmt_VOP3A);
6592  } // decode_OPU_VOP3__V_CUBEMA_F32
6593 
6594  GPUStaticInst*
6596  {
6597  return new Inst_VOP3__V_BFE_U32(&iFmt->iFmt_VOP3A);
6598  } // decode_OPU_VOP3__V_BFE_U32
6599 
6600  GPUStaticInst*
6602  {
6603  return new Inst_VOP3__V_BFE_I32(&iFmt->iFmt_VOP3A);
6604  } // decode_OPU_VOP3__V_BFE_I32
6605 
6606  GPUStaticInst*
6608  {
6609  return new Inst_VOP3__V_BFI_B32(&iFmt->iFmt_VOP3A);
6610  } // decode_OPU_VOP3__V_BFI_B32
6611 
6612  GPUStaticInst*
6614  {
6615  return new Inst_VOP3__V_FMA_F32(&iFmt->iFmt_VOP3A);
6616  } // decode_OPU_VOP3__V_FMA_F32
6617 
6618  GPUStaticInst*
6620  {
6621  return new Inst_VOP3__V_FMA_F64(&iFmt->iFmt_VOP3A);
6622  } // decode_OPU_VOP3__V_FMA_F64
6623 
6624  GPUStaticInst*
6626  {
6627  return new Inst_VOP3__V_LERP_U8(&iFmt->iFmt_VOP3A);
6628  } // decode_OPU_VOP3__V_LERP_U8
6629 
6630  GPUStaticInst*
6632  {
6633  return new Inst_VOP3__V_ALIGNBIT_B32(&iFmt->iFmt_VOP3A);
6634  } // decode_OPU_VOP3__V_ALIGNBIT_B32
6635 
6636  GPUStaticInst*
6638  {
6639  return new Inst_VOP3__V_ALIGNBYTE_B32(&iFmt->iFmt_VOP3A);
6640  } // decode_OPU_VOP3__V_ALIGNBYTE_B32
6641 
6642  GPUStaticInst*
6644  {
6645  return new Inst_VOP3__V_MIN3_F32(&iFmt->iFmt_VOP3A);
6646  } // decode_OPU_VOP3__V_MIN3_F32
6647 
6648  GPUStaticInst*
6650  {
6651  return new Inst_VOP3__V_MIN3_I32(&iFmt->iFmt_VOP3A);
6652  } // decode_OPU_VOP3__V_MIN3_I32
6653 
6654  GPUStaticInst*
6656  {
6657  return new Inst_VOP3__V_MIN3_U32(&iFmt->iFmt_VOP3A);
6658  } // decode_OPU_VOP3__V_MIN3_U32
6659 
6660  GPUStaticInst*
6662  {
6663  return new Inst_VOP3__V_MAX3_F32(&iFmt->iFmt_VOP3A);
6664  } // decode_OPU_VOP3__V_MAX3_F32
6665 
6666  GPUStaticInst*
6668  {
6669  return new Inst_VOP3__V_MAX3_I32(&iFmt->iFmt_VOP3A);
6670  } // decode_OPU_VOP3__V_MAX3_I32
6671 
6672  GPUStaticInst*
6674  {
6675  return new Inst_VOP3__V_MAX3_U32(&iFmt->iFmt_VOP3A);
6676  } // decode_OPU_VOP3__V_MAX3_U32
6677 
6678  GPUStaticInst*
6680  {
6681  return new Inst_VOP3__V_MED3_F32(&iFmt->iFmt_VOP3A);
6682  } // decode_OPU_VOP3__V_MED3_F32
6683 
6684  GPUStaticInst*
6686  {
6687  return new Inst_VOP3__V_MED3_I32(&iFmt->iFmt_VOP3A);
6688  } // decode_OPU_VOP3__V_MED3_I32
6689 
6690  GPUStaticInst*
6692  {
6693  return new Inst_VOP3__V_MED3_U32(&iFmt->iFmt_VOP3A);
6694  } // decode_OPU_VOP3__V_MED3_U32
6695 
6696  GPUStaticInst*
6698  {
6699  return new Inst_VOP3__V_SAD_U8(&iFmt->iFmt_VOP3A);
6700  } // decode_OPU_VOP3__V_SAD_U8
6701 
6702  GPUStaticInst*
6704  {
6705  return new Inst_VOP3__V_SAD_HI_U8(&iFmt->iFmt_VOP3A);
6706  } // decode_OPU_VOP3__V_SAD_HI_U8
6707 
6708  GPUStaticInst*
6710  {
6711  return new Inst_VOP3__V_SAD_U16(&iFmt->iFmt_VOP3A);
6712  } // decode_OPU_VOP3__V_SAD_U16
6713 
6714  GPUStaticInst*
6716  {
6717  return new Inst_VOP3__V_SAD_U32(&iFmt->iFmt_VOP3A);
6718  } // decode_OPU_VOP3__V_SAD_U32
6719 
6720  GPUStaticInst*
6722  {
6723  return new Inst_VOP3__V_CVT_PK_U8_F32(&iFmt->iFmt_VOP3A);
6724  } // decode_OPU_VOP3__V_CVT_PK_U8_F32
6725 
6726  GPUStaticInst*
6728  {
6729  return new Inst_VOP3__V_DIV_FIXUP_F32(&iFmt->iFmt_VOP3A);
6730  } // decode_OPU_VOP3__V_DIV_FIXUP_F32
6731 
6732  GPUStaticInst*
6734  {
6735  return new Inst_VOP3__V_DIV_FIXUP_F64(&iFmt->iFmt_VOP3A);
6736  } // decode_OPU_VOP3__V_DIV_FIXUP_F64
6737 
6738  GPUStaticInst*
6740  {
6741  return new Inst_VOP3__V_DIV_SCALE_F32(&iFmt->iFmt_VOP3B);
6742  } // decode_OPU_VOP3__V_DIV_SCALE_F32
6743 
6744  GPUStaticInst*
6746  {
6747  return new Inst_VOP3__V_DIV_SCALE_F64(&iFmt->iFmt_VOP3B);
6748  } // decode_OPU_VOP3__V_DIV_SCALE_F64
6749 
6750  GPUStaticInst*
6752  {
6753  return new Inst_VOP3__V_DIV_FMAS_F32(&iFmt->iFmt_VOP3A);
6754  } // decode_OPU_VOP3__V_DIV_FMAS_F32
6755 
6756  GPUStaticInst*
6758  {
6759  return new Inst_VOP3__V_DIV_FMAS_F64(&iFmt->iFmt_VOP3A);
6760  } // decode_OPU_VOP3__V_DIV_FMAS_F64
6761 
6762  GPUStaticInst*
6764  {
6765  return new Inst_VOP3__V_MSAD_U8(&iFmt->iFmt_VOP3A);
6766  } // decode_OPU_VOP3__V_MSAD_U8
6767 
6768  GPUStaticInst*
6770  {
6771  return new Inst_VOP3__V_QSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6772  } // decode_OPU_VOP3__V_QSAD_PK_U16_U8
6773 
6774  GPUStaticInst*
6776  {
6777  return new Inst_VOP3__V_MQSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6778  } // decode_OPU_VOP3__V_MQSAD_PK_U16_U8
6779 
6780  GPUStaticInst*
6782  {
6783  return new Inst_VOP3__V_MQSAD_U32_U8(&iFmt->iFmt_VOP3A);
6784  } // decode_OPU_VOP3__V_MQSAD_U32_U8
6785 
6786  GPUStaticInst*
6788  {
6789  return new Inst_VOP3__V_MAD_U64_U32(&iFmt->iFmt_VOP3B);
6790  } // decode_OPU_VOP3__V_MAD_U64_U32
6791 
6792  GPUStaticInst*
6794  {
6795  return new Inst_VOP3__V_MAD_I64_I32(&iFmt->iFmt_VOP3B);
6796  } // decode_OPU_VOP3__V_MAD_I64_I32
6797 
6798  GPUStaticInst*
6800  {
6801  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
6802  } // decode_OPU_VOP3__V_MAD_LEGACY_F16
6803 
6804  GPUStaticInst*
6806  {
6807  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
6808  } // decode_OPU_VOP3__V_MAD_LEGACY_U16
6809 
6810  GPUStaticInst*
6812  {
6813  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
6814  } // decode_OPU_VOP3__V_MAD_LEGACY_I16
6815 
6816  GPUStaticInst*
6818  {
6819  return new Inst_VOP3__V_PERM_B32(&iFmt->iFmt_VOP3A);
6820  } // decode_OPU_VOP3__V_PERM_B32
6821 
6822  GPUStaticInst*
6824  {
6825  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
6826  } // decode_OPU_VOP3__V_FMA_LEGACY_F16
6827 
6828  GPUStaticInst*
6830  {
6831  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
6832  } // decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
6833 
6834  GPUStaticInst*
6836  {
6837  return new Inst_VOP3__V_CVT_PKACCUM_U8_F32(&iFmt->iFmt_VOP3A);
6838  } // decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
6839 
6840  GPUStaticInst*
6842  {
6843  fatal("Trying to decode instruction without a class\n");
6844  return nullptr;
6845  }
6846 
6847  GPUStaticInst*
6849  {
6850  fatal("Trying to decode instruction without a class\n");
6851  return nullptr;
6852  }
6853 
6854  GPUStaticInst*
6856  {
6857  fatal("Trying to decode instruction without a class\n");
6858  return nullptr;
6859  }
6860 
6861  GPUStaticInst*
6863  {
6864  fatal("Trying to decode instruction without a class\n");
6865  return nullptr;
6866  }
6867 
6868  GPUStaticInst*
6870  {
6871  fatal("Trying to decode instruction without a class\n");
6872  return nullptr;
6873  }
6874 
6875  GPUStaticInst*
6877  {
6878  fatal("Trying to decode instruction without a class\n");
6879  return nullptr;
6880  }
6881 
6882  GPUStaticInst*
6884  {
6885  fatal("Trying to decode instruction without a class\n");
6886  return nullptr;
6887  }
6888 
6889  GPUStaticInst*
6891  {
6892  fatal("Trying to decode instruction without a class\n");
6893  return nullptr;
6894  }
6895 
6896  GPUStaticInst*
6898  {
6899  fatal("Trying to decode instruction without a class\n");
6900  return nullptr;
6901  }
6902 
6903  GPUStaticInst*
6905  {
6906  fatal("Trying to decode instruction without a class\n");
6907  return nullptr;
6908  }
6909 
6910  GPUStaticInst*
6912  {
6913  fatal("Trying to decode instruction without a class\n");
6914  return nullptr;
6915  }
6916 
6917  GPUStaticInst*
6919  {
6920  fatal("Trying to decode instruction without a class\n");
6921  return nullptr;
6922  }
6923 
6924  GPUStaticInst*
6926  {
6927  return new Inst_VOP3__V_LSHL_ADD_U32(&iFmt->iFmt_VOP3A);
6928  }
6929 
6930  GPUStaticInst*
6932  {
6933  return new Inst_VOP3__V_ADD_LSHL_U32(&iFmt->iFmt_VOP3A);
6934  }
6935 
6936  GPUStaticInst*
6938  {
6939  return new Inst_VOP3__V_ADD3_U32(&iFmt->iFmt_VOP3A);
6940  }
6941 
6942  GPUStaticInst*
6944  {
6945  return new Inst_VOP3__V_LSHL_OR_B32(&iFmt->iFmt_VOP3A);
6946  }
6947 
6948  GPUStaticInst*
6950  {
6951  return new Inst_VOP3__V_AND_OR_B32(&iFmt->iFmt_VOP3A);
6952  }
6953 
6954  GPUStaticInst*
6956  {
6957  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
6958  }
6959 
6960  GPUStaticInst*
6962  {
6963  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
6964  }
6965 
6966  GPUStaticInst*
6968  {
6969  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
6970  }
6971 
6972  GPUStaticInst*
6974  {
6975  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
6976  }
6977 
6978  GPUStaticInst*
6980  {
6981  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
6982  }
6983 
6984  GPUStaticInst*
6986  {
6987  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
6988  }
6989 
6990  GPUStaticInst*
6992  {
6993  return new Inst_VOP3__V_INTERP_P1_F32(&iFmt->iFmt_VOP3A);
6994  } // decode_OPU_VOP3__V_INTERP_P1_F32
6995 
6996  GPUStaticInst*
6998  {
6999  return new Inst_VOP3__V_INTERP_P2_F32(&iFmt->iFmt_VOP3A);
7000  } // decode_OPU_VOP3__V_INTERP_P2_F32
7001 
7002  GPUStaticInst*
7004  {
7005  return new Inst_VOP3__V_INTERP_MOV_F32(&iFmt->iFmt_VOP3A);
7006  } // decode_OPU_VOP3__V_INTERP_MOV_F32
7007 
7008  GPUStaticInst*
7010  {
7011  return new Inst_VOP3__V_INTERP_P1LL_F16(&iFmt->iFmt_VOP3A);
7012  } // decode_OPU_VOP3__V_INTERP_P1LL_F16
7013 
7014  GPUStaticInst*
7016  {
7017  return new Inst_VOP3__V_INTERP_P1LV_F16(&iFmt->iFmt_VOP3A);
7018  } // decode_OPU_VOP3__V_INTERP_P1LV_F16
7019 
7020  GPUStaticInst*
7022  {
7023  fatal("Trying to decode instruction without a class\n");
7024  return nullptr;
7025  }
7026 
7027  GPUStaticInst*
7029  {
7030  return new Inst_VOP3__V_INTERP_P2_F16(&iFmt->iFmt_VOP3A);
7031  } // decode_OPU_VOP3__V_INTERP_P2_F16
7032 
7033  GPUStaticInst*
7035  {
7036  return new Inst_VOP3__V_ADD_F64(&iFmt->iFmt_VOP3A);
7037  } // decode_OPU_VOP3__V_ADD_F64
7038 
7039  GPUStaticInst*
7041  {
7042  return new Inst_VOP3__V_MUL_F64(&iFmt->iFmt_VOP3A);
7043  } // decode_OPU_VOP3__V_MUL_F64
7044 
7045  GPUStaticInst*
7047  {
7048  return new Inst_VOP3__V_MIN_F64(&iFmt->iFmt_VOP3A);
7049  } // decode_OPU_VOP3__V_MIN_F64
7050 
7051  GPUStaticInst*
7053  {
7054  return new Inst_VOP3__V_MAX_F64(&iFmt->iFmt_VOP3A);
7055  } // decode_OPU_VOP3__V_MAX_F64
7056 
7057  GPUStaticInst*
7059  {
7060  return new Inst_VOP3__V_LDEXP_F64(&iFmt->iFmt_VOP3A);
7061  } // decode_OPU_VOP3__V_LDEXP_F64
7062 
7063  GPUStaticInst*
7065  {
7066  return new Inst_VOP3__V_MUL_LO_U32(&iFmt->iFmt_VOP3A);
7067  } // decode_OPU_VOP3__V_MUL_LO_U32
7068 
7069  GPUStaticInst*
7071  {
7072  return new Inst_VOP3__V_MUL_HI_U32(&iFmt->iFmt_VOP3A);
7073  } // decode_OPU_VOP3__V_MUL_HI_U32
7074 
7075  GPUStaticInst*
7077  {
7078  return new Inst_VOP3__V_MUL_HI_I32(&iFmt->iFmt_VOP3A);
7079  } // decode_OPU_VOP3__V_MUL_HI_I32
7080 
7081  GPUStaticInst*
7083  {
7084  return new Inst_VOP3__V_LDEXP_F32(&iFmt->iFmt_VOP3A);
7085  } // decode_OPU_VOP3__V_LDEXP_F32
7086 
7087  GPUStaticInst*
7089  {
7090  return new Inst_VOP3__V_READLANE_B32(&iFmt->iFmt_VOP3A);
7091  } // decode_OPU_VOP3__V_READLANE_B32
7092 
7093  GPUStaticInst*
7095  {
7096  return new Inst_VOP3__V_WRITELANE_B32(&iFmt->iFmt_VOP3A);
7097  } // decode_OPU_VOP3__V_WRITELANE_B32
7098 
7099  GPUStaticInst*
7101  {
7102  return new Inst_VOP3__V_BCNT_U32_B32(&iFmt->iFmt_VOP3A);
7103  } // decode_OPU_VOP3__V_BCNT_U32_B32
7104 
7105  GPUStaticInst*
7107  {
7108  return new Inst_VOP3__V_MBCNT_LO_U32_B32(&iFmt->iFmt_VOP3A);
7109  } // decode_OPU_VOP3__V_MBCNT_LO_U32_B32
7110 
7111  GPUStaticInst*
7113  {
7114  return new Inst_VOP3__V_MBCNT_HI_U32_B32(&iFmt->iFmt_VOP3A);
7115  } // decode_OPU_VOP3__V_MBCNT_HI_U32_B32
7116 
7117  GPUStaticInst*
7119  {
7120  return new Inst_VOP3__V_LSHLREV_B64(&iFmt->iFmt_VOP3A);
7121  } // decode_OPU_VOP3__V_LSHLREV_B64
7122 
7123  GPUStaticInst*
7125  {
7126  return new Inst_VOP3__V_LSHRREV_B64(&iFmt->iFmt_VOP3A);
7127  } // decode_OPU_VOP3__V_LSHRREV_B64
7128 
7129  GPUStaticInst*
7131  {
7132  return new Inst_VOP3__V_ASHRREV_I64(&iFmt->iFmt_VOP3A);
7133  } // decode_OPU_VOP3__V_ASHRREV_I64
7134 
7135  GPUStaticInst*
7137  {
7138  return new Inst_VOP3__V_TRIG_PREOP_F64(&iFmt->iFmt_VOP3A);
7139  } // decode_OPU_VOP3__V_TRIG_PREOP_F64
7140 
7141  GPUStaticInst*
7143  {
7144  return new Inst_VOP3__V_BFM_B32(&iFmt->iFmt_VOP3A);
7145  } // decode_OPU_VOP3__V_BFM_B32
7146 
7147  GPUStaticInst*
7149  {
7150  return new Inst_VOP3__V_CVT_PKNORM_I16_F32(&iFmt->iFmt_VOP3A);
7151  } // decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
7152 
7153  GPUStaticInst*
7155  {
7156  return new Inst_VOP3__V_CVT_PKNORM_U16_F32(&iFmt->iFmt_VOP3A);
7157  } // decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
7158 
7159  GPUStaticInst*
7161  {
7162  return new Inst_VOP3__V_CVT_PKRTZ_F16_F32(&iFmt->iFmt_VOP3A);
7163  } // decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
7164 
7165  GPUStaticInst*
7167  {
7168  return new Inst_VOP3__V_CVT_PK_U16_U32(&iFmt->iFmt_VOP3A);
7169  } // decode_OPU_VOP3__V_CVT_PK_U16_U32
7170 
7171  GPUStaticInst*
7173  {
7174  return new Inst_VOP3__V_CVT_PK_I16_I32(&iFmt->iFmt_VOP3A);
7175  } // decode_OPU_VOP3__V_CVT_PK_I16_I32
7176 
7177  GPUStaticInst*
7179  {
7180  fatal("Trying to decode instruction without a class\n");
7181  return nullptr;
7182  }
7183 
7184  GPUStaticInst*
7186  {
7187  fatal("Trying to decode instruction without a class\n");
7188  return nullptr;
7189  }
7190 
7191  GPUStaticInst*
7193  {
7194  fatal("Trying to decode instruction without a class\n");
7195  return nullptr;
7196  }
7197 
7198  GPUStaticInst*
7200  {
7201  fatal("Trying to decode instruction without a class\n");
7202  return nullptr;
7203  }
7204 
7205  GPUStaticInst*
7207  {
7208  fatal("Trying to decode instruction without a class\n");
7209  return nullptr;
7210  }
7211 
7212  GPUStaticInst*
7214  {
7215  fatal("Trying to decode instruction without a class\n");
7216  return nullptr;
7217  }
7218 
7219  GPUStaticInst*
7221  {
7222  fatal("Trying to decode instruction without a class\n");
7223  return nullptr;
7224  }
7225 
7226  GPUStaticInst*
7228  {
7229  return new Inst_DS__DS_ADD_U32(&iFmt->iFmt_DS);
7230  } // decode_OP_DS__DS_ADD_U32
7231 
7232  GPUStaticInst*
7234  {
7235  return new Inst_DS__DS_SUB_U32(&iFmt->iFmt_DS);
7236  } // decode_OP_DS__DS_SUB_U32
7237 
7238  GPUStaticInst*
7240  {
7241  return new Inst_DS__DS_RSUB_U32(&iFmt->iFmt_DS);
7242  } // decode_OP_DS__DS_RSUB_U32
7243 
7244  GPUStaticInst*
7246  {
7247  return new Inst_DS__DS_INC_U32(&iFmt->iFmt_DS);
7248  } // decode_OP_DS__DS_INC_U32
7249 
7250  GPUStaticInst*
7252  {
7253  return new Inst_DS__DS_DEC_U32(&iFmt->iFmt_DS);
7254  } // decode_OP_DS__DS_DEC_U32
7255 
7256  GPUStaticInst*
7258  {
7259  return new Inst_DS__DS_MIN_I32(&iFmt->iFmt_DS);
7260  } // decode_OP_DS__DS_MIN_I32
7261 
7262  GPUStaticInst*
7264  {
7265  return new Inst_DS__DS_MAX_I32(&iFmt->iFmt_DS);
7266  } // decode_OP_DS__DS_MAX_I32
7267 
7268  GPUStaticInst*
7270  {
7271  return new Inst_DS__DS_MIN_U32(&iFmt->iFmt_DS);
7272  } // decode_OP_DS__DS_MIN_U32
7273 
7274  GPUStaticInst*
7276  {
7277  return new Inst_DS__DS_MAX_U32(&iFmt->iFmt_DS);
7278  } // decode_OP_DS__DS_MAX_U32
7279 
7280  GPUStaticInst*
7282  {
7283  return new Inst_DS__DS_AND_B32(&iFmt->iFmt_DS);
7284  } // decode_OP_DS__DS_AND_B32
7285 
7286  GPUStaticInst*
7288  {
7289  return new Inst_DS__DS_OR_B32(&iFmt->iFmt_DS);
7290  } // decode_OP_DS__DS_OR_B32
7291 
7292  GPUStaticInst*
7294  {
7295  return new Inst_DS__DS_XOR_B32(&iFmt->iFmt_DS);
7296  } // decode_OP_DS__DS_XOR_B32
7297 
7298  GPUStaticInst*
7300  {
7301  return new Inst_DS__DS_MSKOR_B32(&iFmt->iFmt_DS);
7302  } // decode_OP_DS__DS_MSKOR_B32
7303 
7304  GPUStaticInst*
7306  {
7307  return new Inst_DS__DS_WRITE_B32(&iFmt->iFmt_DS);
7308  } // decode_OP_DS__DS_WRITE_B32
7309 
7310  GPUStaticInst*
7312  {
7313  return new Inst_DS__DS_WRITE2_B32(&iFmt->iFmt_DS);
7314  } // decode_OP_DS__DS_WRITE2_B32
7315 
7316  GPUStaticInst*
7318  {
7319  return new Inst_DS__DS_WRITE2ST64_B32(&iFmt->iFmt_DS);
7320  } // decode_OP_DS__DS_WRITE2ST64_B32
7321 
7322  GPUStaticInst*
7324  {
7325  return new Inst_DS__DS_CMPST_B32(&iFmt->iFmt_DS);
7326  } // decode_OP_DS__DS_CMPST_B32
7327 
7328  GPUStaticInst*
7330  {
7331  return new Inst_DS__DS_CMPST_F32(&iFmt->iFmt_DS);
7332  } // decode_OP_DS__DS_CMPST_F32
7333 
7334  GPUStaticInst*
7336  {
7337  return new Inst_DS__DS_MIN_F32(&iFmt->iFmt_DS);
7338  } // decode_OP_DS__DS_MIN_F32
7339 
7340  GPUStaticInst*
7342  {
7343  return new Inst_DS__DS_MAX_F32(&iFmt->iFmt_DS);
7344  } // decode_OP_DS__DS_MAX_F32
7345 
7346  GPUStaticInst*
7348  {
7349  return new Inst_DS__DS_NOP(&iFmt->iFmt_DS);
7350  } // decode_OP_DS__DS_NOP
7351 
7352  GPUStaticInst*
7354  {
7355  return new Inst_DS__DS_ADD_F32(&iFmt->iFmt_DS);
7356  } // decode_OP_DS__DS_ADD_F32
7357 
7358  GPUStaticInst*
7360  {
7361  fatal("Trying to decode instruction without a class\n");
7362  return nullptr;
7363  }
7364 
7365  GPUStaticInst*
7367  {
7368  return new Inst_DS__DS_WRITE_B8(&iFmt->iFmt_DS);
7369  } // decode_OP_DS__DS_WRITE_B8
7370 
7371  GPUStaticInst*
7373  {
7374  return new Inst_DS__DS_WRITE_B16(&iFmt->iFmt_DS);
7375  } // decode_OP_DS__DS_WRITE_B16
7376 
7377  GPUStaticInst*
7379  {
7380  return new Inst_DS__DS_ADD_RTN_U32(&iFmt->iFmt_DS);
7381  } // decode_OP_DS__DS_ADD_RTN_U32
7382 
7383  GPUStaticInst*
7385  {
7386  return new Inst_DS__DS_SUB_RTN_U32(&iFmt->iFmt_DS);
7387  } // decode_OP_DS__DS_SUB_RTN_U32
7388 
7389  GPUStaticInst*
7391  {
7392  return new Inst_DS__DS_RSUB_RTN_U32(&iFmt->iFmt_DS);
7393  } // decode_OP_DS__DS_RSUB_RTN_U32
7394 
7395  GPUStaticInst*
7397  {
7398  return new Inst_DS__DS_INC_RTN_U32(&iFmt->iFmt_DS);
7399  } // decode_OP_DS__DS_INC_RTN_U32
7400 
7401  GPUStaticInst*
7403  {
7404  return new Inst_DS__DS_DEC_RTN_U32(&iFmt->iFmt_DS);
7405  } // decode_OP_DS__DS_DEC_RTN_U32
7406 
7407  GPUStaticInst*
7409  {
7410  return new Inst_DS__DS_MIN_RTN_I32(&iFmt->iFmt_DS);
7411  } // decode_OP_DS__DS_MIN_RTN_I32
7412 
7413  GPUStaticInst*
7415  {
7416  return new Inst_DS__DS_MAX_RTN_I32(&iFmt->iFmt_DS);
7417  } // decode_OP_DS__DS_MAX_RTN_I32
7418 
7419  GPUStaticInst*
7421  {
7422  return new Inst_DS__DS_MIN_RTN_U32(&iFmt->iFmt_DS);
7423  } // decode_OP_DS__DS_MIN_RTN_U32
7424 
7425  GPUStaticInst*
7427  {
7428  return new Inst_DS__DS_MAX_RTN_U32(&iFmt->iFmt_DS);
7429  } // decode_OP_DS__DS_MAX_RTN_U32
7430 
7431  GPUStaticInst*
7433  {
7434  return new Inst_DS__DS_AND_RTN_B32(&iFmt->iFmt_DS);
7435  } // decode_OP_DS__DS_AND_RTN_B32
7436 
7437  GPUStaticInst*
7439  {
7440  return new Inst_DS__DS_OR_RTN_B32(&iFmt->iFmt_DS);
7441  } // decode_OP_DS__DS_OR_RTN_B32
7442 
7443  GPUStaticInst*
7445  {
7446  return new Inst_DS__DS_XOR_RTN_B32(&iFmt->iFmt_DS);
7447  } // decode_OP_DS__DS_XOR_RTN_B32
7448 
7449  GPUStaticInst*
7451  {
7452  return new Inst_DS__DS_MSKOR_RTN_B32(&iFmt->iFmt_DS);
7453  } // decode_OP_DS__DS_MSKOR_RTN_B32
7454 
7455  GPUStaticInst*
7457  {
7458  return new Inst_DS__DS_WRXCHG_RTN_B32(&iFmt->iFmt_DS);
7459  } // decode_OP_DS__DS_WRXCHG_RTN_B32
7460 
7461  GPUStaticInst*
7463  {
7464  return new Inst_DS__DS_WRXCHG2_RTN_B32(&iFmt->iFmt_DS);
7465  } // decode_OP_DS__DS_WRXCHG2_RTN_B32
7466 
7467  GPUStaticInst*
7469  {
7470  return new Inst_DS__DS_WRXCHG2ST64_RTN_B32(&iFmt->iFmt_DS);
7471  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
7472 
7473  GPUStaticInst*
7475  {
7476  return new Inst_DS__DS_CMPST_RTN_B32(&iFmt->iFmt_DS);
7477  } // decode_OP_DS__DS_CMPST_RTN_B32
7478 
7479  GPUStaticInst*
7481  {
7482  return new Inst_DS__DS_CMPST_RTN_F32(&iFmt->iFmt_DS);
7483  } // decode_OP_DS__DS_CMPST_RTN_F32
7484 
7485  GPUStaticInst*
7487  {
7488  return new Inst_DS__DS_MIN_RTN_F32(&iFmt->iFmt_DS);
7489  } // decode_OP_DS__DS_MIN_RTN_F32
7490 
7491  GPUStaticInst*
7493  {
7494  return new Inst_DS__DS_MAX_RTN_F32(&iFmt->iFmt_DS);
7495  } // decode_OP_DS__DS_MAX_RTN_F32
7496 
7497  GPUStaticInst*
7499  {
7500  return new Inst_DS__DS_WRAP_RTN_B32(&iFmt->iFmt_DS);
7501  } // decode_OP_DS__DS_WRAP_RTN_B32
7502 
7503  GPUStaticInst*
7505  {
7506  return new Inst_DS__DS_ADD_RTN_F32(&iFmt->iFmt_DS);
7507  } // decode_OP_DS__DS_ADD_RTN_F32
7508 
7509  GPUStaticInst*
7511  {
7512  return new Inst_DS__DS_READ_B32(&iFmt->iFmt_DS);
7513  } // decode_OP_DS__DS_READ_B32
7514 
7515  GPUStaticInst*
7517  {
7518  return new Inst_DS__DS_READ2_B32(&iFmt->iFmt_DS);
7519  } // decode_OP_DS__DS_READ2_B32
7520 
7521  GPUStaticInst*
7523  {
7524  return new Inst_DS__DS_READ2ST64_B32(&iFmt->iFmt_DS);
7525  } // decode_OP_DS__DS_READ2ST64_B32
7526 
7527  GPUStaticInst*
7529  {
7530  return new Inst_DS__DS_READ_I8(&iFmt->iFmt_DS);
7531  } // decode_OP_DS__DS_READ_I8
7532 
7533  GPUStaticInst*
7535  {
7536  return new Inst_DS__DS_READ_U8(&iFmt->iFmt_DS);
7537  } // decode_OP_DS__DS_READ_U8
7538 
7539  GPUStaticInst*
7541  {
7542  return new Inst_DS__DS_READ_I16(&iFmt->iFmt_DS);
7543  } // decode_OP_DS__DS_READ_I16
7544 
7545  GPUStaticInst*
7547  {
7548  return new Inst_DS__DS_READ_U16(&iFmt->iFmt_DS);
7549  } // decode_OP_DS__DS_READ_U16
7550 
7551  GPUStaticInst*
7553  {
7554  return new Inst_DS__DS_SWIZZLE_B32(&iFmt->iFmt_DS);
7555  } // decode_OP_DS__DS_SWIZZLE_B32
7556 
7557  GPUStaticInst*
7559  {
7560  return new Inst_DS__DS_PERMUTE_B32(&iFmt->iFmt_DS);
7561  } // decode_OP_DS__DS_PERMUTE_B32
7562 
7563  GPUStaticInst*
7565  {
7566  return new Inst_DS__DS_BPERMUTE_B32(&iFmt->iFmt_DS);
7567  } // decode_OP_DS__DS_BPERMUTE_B32
7568 
7569  GPUStaticInst*
7571  {
7572  return new Inst_DS__DS_ADD_U64(&iFmt->iFmt_DS);
7573  } // decode_OP_DS__DS_ADD_U64
7574 
7575  GPUStaticInst*
7577  {
7578  return new Inst_DS__DS_SUB_U64(&iFmt->iFmt_DS);
7579  } // decode_OP_DS__DS_SUB_U64
7580 
7581  GPUStaticInst*
7583  {
7584  return new Inst_DS__DS_RSUB_U64(&iFmt->iFmt_DS);
7585  } // decode_OP_DS__DS_RSUB_U64
7586 
7587  GPUStaticInst*
7589  {
7590  return new Inst_DS__DS_INC_U64(&iFmt->iFmt_DS);
7591  } // decode_OP_DS__DS_INC_U64
7592 
7593  GPUStaticInst*
7595  {
7596  return new Inst_DS__DS_DEC_U64(&iFmt->iFmt_DS);
7597  } // decode_OP_DS__DS_DEC_U64
7598 
7599  GPUStaticInst*
7601  {
7602  return new Inst_DS__DS_MIN_I64(&iFmt->iFmt_DS);
7603  } // decode_OP_DS__DS_MIN_I64
7604 
7605  GPUStaticInst*
7607  {
7608  return new Inst_DS__DS_MAX_I64(&iFmt->iFmt_DS);
7609  } // decode_OP_DS__DS_MAX_I64
7610 
7611  GPUStaticInst*
7613  {
7614  return new Inst_DS__DS_MIN_U64(&iFmt->iFmt_DS);
7615  } // decode_OP_DS__DS_MIN_U64
7616 
7617  GPUStaticInst*
7619  {
7620  return new Inst_DS__DS_MAX_U64(&iFmt->iFmt_DS);
7621  } // decode_OP_DS__DS_MAX_U64
7622 
7623  GPUStaticInst*
7625  {
7626  return new Inst_DS__DS_AND_B64(&iFmt->iFmt_DS);
7627  } // decode_OP_DS__DS_AND_B64
7628 
7629  GPUStaticInst*
7631  {
7632  return new Inst_DS__DS_OR_B64(&iFmt->iFmt_DS);
7633  } // decode_OP_DS__DS_OR_B64
7634 
7635  GPUStaticInst*
7637  {
7638  return new Inst_DS__DS_XOR_B64(&iFmt->iFmt_DS);
7639  } // decode_OP_DS__DS_XOR_B64
7640 
7641  GPUStaticInst*
7643  {
7644  return new Inst_DS__DS_MSKOR_B64(&iFmt->iFmt_DS);
7645  } // decode_OP_DS__DS_MSKOR_B64
7646 
7647  GPUStaticInst*
7649  {
7650  return new Inst_DS__DS_WRITE_B64(&iFmt->iFmt_DS);
7651  } // decode_OP_DS__DS_WRITE_B64
7652 
7653  GPUStaticInst*
7655  {
7656  return new Inst_DS__DS_WRITE2_B64(&iFmt->iFmt_DS);
7657  } // decode_OP_DS__DS_WRITE2_B64
7658 
7659  GPUStaticInst*
7661  {
7662  return new Inst_DS__DS_WRITE2ST64_B64(&iFmt->iFmt_DS);
7663  } // decode_OP_DS__DS_WRITE2ST64_B64
7664 
7665  GPUStaticInst*
7667  {
7668  return new Inst_DS__DS_CMPST_B64(&iFmt->iFmt_DS);
7669  } // decode_OP_DS__DS_CMPST_B64
7670 
7671  GPUStaticInst*
7673  {
7674  return new Inst_DS__DS_CMPST_F64(&iFmt->iFmt_DS);
7675  } // decode_OP_DS__DS_CMPST_F64
7676 
7677  GPUStaticInst*
7679  {
7680  return new Inst_DS__DS_MIN_F64(&iFmt->iFmt_DS);
7681  } // decode_OP_DS__DS_MIN_F64
7682 
7683  GPUStaticInst*
7685  {
7686  return new Inst_DS__DS_MAX_F64(&iFmt->iFmt_DS);
7687  } // decode_OP_DS__DS_MAX_F64
7688 
7689  GPUStaticInst*
7691  {
7692  fatal("Trying to decode instruction without a class\n");
7693  return nullptr;
7694  }
7695 
7696  GPUStaticInst*
7698  {
7699  fatal("Trying to decode instruction without a class\n");
7700  return nullptr;
7701  }
7702 
7703  GPUStaticInst*
7705  {
7706  fatal("Trying to decode instruction without a class\n");
7707  return nullptr;
7708  }
7709 
7710  GPUStaticInst*
7712  {
7713  fatal("Trying to decode instruction without a class\n");
7714  return nullptr;
7715  }
7716 
7717  GPUStaticInst*
7719  {
7720  fatal("Trying to decode instruction without a class\n");
7721  return nullptr;
7722  }
7723 
7724  GPUStaticInst*
7726  {
7727  fatal("Trying to decode instruction without a class\n");
7728  return nullptr;
7729  }
7730 
7731  GPUStaticInst*
7733  {
7734  fatal("Trying to decode instruction without a class\n");
7735  return nullptr;
7736  }
7737 
7738  GPUStaticInst*
7740  {
7741  fatal("Trying to decode instruction without a class\n");
7742  return nullptr;
7743  }
7744 
7745  GPUStaticInst*
7747  {
7748  return new Inst_DS__DS_ADD_RTN_U64(&iFmt->iFmt_DS);
7749  } // decode_OP_DS__DS_ADD_RTN_U64
7750 
7751  GPUStaticInst*
7753  {
7754  return new Inst_DS__DS_SUB_RTN_U64(&iFmt->iFmt_DS);
7755  } // decode_OP_DS__DS_SUB_RTN_U64
7756 
7757  GPUStaticInst*
7759  {
7760  return new Inst_DS__DS_RSUB_RTN_U64(&iFmt->iFmt_DS);
7761  } // decode_OP_DS__DS_RSUB_RTN_U64
7762 
7763  GPUStaticInst*
7765  {
7766  return new Inst_DS__DS_INC_RTN_U64(&iFmt->iFmt_DS);
7767  } // decode_OP_DS__DS_INC_RTN_U64
7768 
7769  GPUStaticInst*
7771  {
7772  return new Inst_DS__DS_DEC_RTN_U64(&iFmt->iFmt_DS);
7773  } // decode_OP_DS__DS_DEC_RTN_U64
7774 
7775  GPUStaticInst*
7777  {
7778  return new Inst_DS__DS_MIN_RTN_I64(&iFmt->iFmt_DS);
7779  } // decode_OP_DS__DS_MIN_RTN_I64
7780 
7781  GPUStaticInst*
7783  {
7784  return new Inst_DS__DS_MAX_RTN_I64(&iFmt->iFmt_DS);
7785  } // decode_OP_DS__DS_MAX_RTN_I64
7786 
7787  GPUStaticInst*
7789  {
7790  return new Inst_DS__DS_MIN_RTN_U64(&iFmt->iFmt_DS);
7791  } // decode_OP_DS__DS_MIN_RTN_U64
7792 
7793  GPUStaticInst*
7795  {
7796  return new Inst_DS__DS_MAX_RTN_U64(&iFmt->iFmt_DS);
7797  } // decode_OP_DS__DS_MAX_RTN_U64
7798 
7799  GPUStaticInst*
7801  {
7802  return new Inst_DS__DS_AND_RTN_B64(&iFmt->iFmt_DS);
7803  } // decode_OP_DS__DS_AND_RTN_B64
7804 
7805  GPUStaticInst*
7807  {
7808  return new Inst_DS__DS_OR_RTN_B64(&iFmt->iFmt_DS);
7809  } // decode_OP_DS__DS_OR_RTN_B64
7810 
7811  GPUStaticInst*
7813  {
7814  return new Inst_DS__DS_XOR_RTN_B64(&iFmt->iFmt_DS);
7815  } // decode_OP_DS__DS_XOR_RTN_B64
7816 
7817  GPUStaticInst*
7819  {
7820  return new Inst_DS__DS_MSKOR_RTN_B64(&iFmt->iFmt_DS);
7821  } // decode_OP_DS__DS_MSKOR_RTN_B64
7822 
7823  GPUStaticInst*
7825  {
7826  return new Inst_DS__DS_WRXCHG_RTN_B64(&iFmt->iFmt_DS);
7827  } // decode_OP_DS__DS_WRXCHG_RTN_B64
7828 
7829  GPUStaticInst*
7831  {
7832  return new Inst_DS__DS_WRXCHG2_RTN_B64(&iFmt->iFmt_DS);
7833  } // decode_OP_DS__DS_WRXCHG2_RTN_B64
7834 
7835  GPUStaticInst*
7837  {
7838  return new Inst_DS__DS_WRXCHG2ST64_RTN_B64(&iFmt->iFmt_DS);
7839  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
7840 
7841  GPUStaticInst*
7843  {
7844  return new Inst_DS__DS_CMPST_RTN_B64(&iFmt->iFmt_DS);
7845  } // decode_OP_DS__DS_CMPST_RTN_B64
7846 
7847  GPUStaticInst*
7849  {
7850  return new Inst_DS__DS_CMPST_RTN_F64(&iFmt->iFmt_DS);
7851  } // decode_OP_DS__DS_CMPST_RTN_F64
7852 
7853  GPUStaticInst*
7855  {
7856  return new Inst_DS__DS_MIN_RTN_F64(&iFmt->iFmt_DS);
7857  } // decode_OP_DS__DS_MIN_RTN_F64
7858 
7859  GPUStaticInst*
7861  {
7862  return new Inst_DS__DS_MAX_RTN_F64(&iFmt->iFmt_DS);
7863  } // decode_OP_DS__DS_MAX_RTN_F64
7864 
7865  GPUStaticInst*
7867  {
7868  return new Inst_DS__DS_READ_B64(&iFmt->iFmt_DS);
7869  } // decode_OP_DS__DS_READ_B64
7870 
7871  GPUStaticInst*
7873  {
7874  return new Inst_DS__DS_READ2_B64(&iFmt->iFmt_DS);
7875  } // decode_OP_DS__DS_READ2_B64
7876 
7877  GPUStaticInst*
7879  {
7880  return new Inst_DS__DS_READ2ST64_B64(&iFmt->iFmt_DS);
7881  } // decode_OP_DS__DS_READ2ST64_B64
7882 
7883  GPUStaticInst*
7885  {
7886  return new Inst_DS__DS_CONDXCHG32_RTN_B64(&iFmt->iFmt_DS);
7887  } // decode_OP_DS__DS_CONDXCHG32_RTN_B64
7888 
7889  GPUStaticInst*
7891  {
7892  return new Inst_DS__DS_ADD_SRC2_U32(&iFmt->iFmt_DS);
7893  } // decode_OP_DS__DS_ADD_SRC2_U32
7894 
7895  GPUStaticInst*
7897  {
7898  return new Inst_DS__DS_SUB_SRC2_U32(&iFmt->iFmt_DS);
7899  } // decode_OP_DS__DS_SUB_SRC2_U32
7900 
7901  GPUStaticInst*
7903  {
7904  return new Inst_DS__DS_RSUB_SRC2_U32(&iFmt->iFmt_DS);
7905  } // decode_OP_DS__DS_RSUB_SRC2_U32
7906 
7907  GPUStaticInst*
7909  {
7910  return new Inst_DS__DS_INC_SRC2_U32(&iFmt->iFmt_DS);
7911  } // decode_OP_DS__DS_INC_SRC2_U32
7912 
7913  GPUStaticInst*
7915  {
7916  return new Inst_DS__DS_DEC_SRC2_U32(&iFmt->iFmt_DS);
7917  } // decode_OP_DS__DS_DEC_SRC2_U32
7918 
7919  GPUStaticInst*
7921  {
7922  return new Inst_DS__DS_MIN_SRC2_I32(&iFmt->iFmt_DS);
7923  } // decode_OP_DS__DS_MIN_SRC2_I32
7924 
7925  GPUStaticInst*
7927  {
7928  return new Inst_DS__DS_MAX_SRC2_I32(&iFmt->iFmt_DS);
7929  } // decode_OP_DS__DS_MAX_SRC2_I32
7930 
7931  GPUStaticInst*
7933  {
7934  return new Inst_DS__DS_MIN_SRC2_U32(&iFmt->iFmt_DS);
7935  } // decode_OP_DS__DS_MIN_SRC2_U32
7936 
7937  GPUStaticInst*
7939  {
7940  return new Inst_DS__DS_MAX_SRC2_U32(&iFmt->iFmt_DS);
7941  } // decode_OP_DS__DS_MAX_SRC2_U32
7942 
7943  GPUStaticInst*
7945  {
7946  return new Inst_DS__DS_AND_SRC2_B32(&iFmt->iFmt_DS);
7947  } // decode_OP_DS__DS_AND_SRC2_B32
7948 
7949  GPUStaticInst*
7951  {
7952  return new Inst_DS__DS_OR_SRC2_B32(&iFmt->iFmt_DS);
7953  } // decode_OP_DS__DS_OR_SRC2_B32
7954 
7955  GPUStaticInst*
7957  {
7958  return new Inst_DS__DS_XOR_SRC2_B32(&iFmt->iFmt_DS);
7959  } // decode_OP_DS__DS_XOR_SRC2_B32
7960 
7961  GPUStaticInst*
7963  {
7964  return new Inst_DS__DS_WRITE_SRC2_B32(&iFmt->iFmt_DS);
7965  } // decode_OP_DS__DS_WRITE_SRC2_B32
7966 
7967  GPUStaticInst*
7969  {
7970  return new Inst_DS__DS_MIN_SRC2_F32(&iFmt->iFmt_DS);
7971  } // decode_OP_DS__DS_MIN_SRC2_F32
7972 
7973  GPUStaticInst*
7975  {
7976  return new Inst_DS__DS_MAX_SRC2_F32(&iFmt->iFmt_DS);
7977  } // decode_OP_DS__DS_MAX_SRC2_F32
7978 
7979  GPUStaticInst*
7981  {
7982  return new Inst_DS__DS_ADD_SRC2_F32(&iFmt->iFmt_DS);
7983  } // decode_OP_DS__DS_ADD_SRC2_F32
7984 
7985  GPUStaticInst*
7987  {
7988  return new Inst_DS__DS_GWS_SEMA_RELEASE_ALL(&iFmt->iFmt_DS);
7989  } // decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
7990 
7991  GPUStaticInst*
7993  {
7994  return new Inst_DS__DS_GWS_INIT(&iFmt->iFmt_DS);
7995  } // decode_OP_DS__DS_GWS_INIT
7996 
7997  GPUStaticInst*
7999  {
8000  return new Inst_DS__DS_GWS_SEMA_V(&iFmt->iFmt_DS);
8001  } // decode_OP_DS__DS_GWS_SEMA_V
8002 
8003  GPUStaticInst*
8005  {
8006  return new Inst_DS__DS_GWS_SEMA_BR(&iFmt->iFmt_DS);
8007  } // decode_OP_DS__DS_GWS_SEMA_BR
8008 
8009  GPUStaticInst*
8011  {
8012  return new Inst_DS__DS_GWS_SEMA_P(&iFmt->iFmt_DS);
8013  } // decode_OP_DS__DS_GWS_SEMA_P
8014 
8015  GPUStaticInst*
8017  {
8018  return new Inst_DS__DS_GWS_BARRIER(&iFmt->iFmt_DS);
8019  } // decode_OP_DS__DS_GWS_BARRIER
8020 
8021  GPUStaticInst*
8023  {
8024  fatal("Trying to decode instruction without a class\n");
8025  return nullptr;
8026  }
8027 
8028  GPUStaticInst*
8030  {
8031  return new Inst_DS__DS_CONSUME(&iFmt->iFmt_DS);
8032  } // decode_OP_DS__DS_CONSUME
8033 
8034  GPUStaticInst*
8036  {
8037  return new Inst_DS__DS_APPEND(&iFmt->iFmt_DS);
8038  } // decode_OP_DS__DS_APPEND
8039 
8040  GPUStaticInst*
8042  {
8043  return new Inst_DS__DS_ORDERED_COUNT(&iFmt->iFmt_DS);
8044  } // decode_OP_DS__DS_ORDERED_COUNT
8045 
8046  GPUStaticInst*
8048  {
8049  return new Inst_DS__DS_ADD_SRC2_U64(&iFmt->iFmt_DS);
8050  } // decode_OP_DS__DS_ADD_SRC2_U64
8051 
8052  GPUStaticInst*
8054  {
8055  return new Inst_DS__DS_SUB_SRC2_U64(&iFmt->iFmt_DS);
8056  } // decode_OP_DS__DS_SUB_SRC2_U64
8057 
8058  GPUStaticInst*
8060  {
8061  return new Inst_DS__DS_RSUB_SRC2_U64(&iFmt->iFmt_DS);
8062  } // decode_OP_DS__DS_RSUB_SRC2_U64
8063 
8064  GPUStaticInst*
8066  {
8067  return new Inst_DS__DS_INC_SRC2_U64(&iFmt->iFmt_DS);
8068  } // decode_OP_DS__DS_INC_SRC2_U64
8069 
8070  GPUStaticInst*
8072  {
8073  return new Inst_DS__DS_DEC_SRC2_U64(&iFmt->iFmt_DS);
8074  } // decode_OP_DS__DS_DEC_SRC2_U64
8075 
8076  GPUStaticInst*
8078  {
8079  return new Inst_DS__DS_MIN_SRC2_I64(&iFmt->iFmt_DS);
8080  } // decode_OP_DS__DS_MIN_SRC2_I64
8081 
8082  GPUStaticInst*
8084  {
8085  return new Inst_DS__DS_MAX_SRC2_I64(&iFmt->iFmt_DS);
8086  } // decode_OP_DS__DS_MAX_SRC2_I64
8087 
8088  GPUStaticInst*
8090  {
8091  return new Inst_DS__DS_MIN_SRC2_U64(&iFmt->iFmt_DS);
8092  } // decode_OP_DS__DS_MIN_SRC2_U64
8093 
8094  GPUStaticInst*
8096  {
8097  return new Inst_DS__DS_MAX_SRC2_U64(&iFmt->iFmt_DS);
8098  } // decode_OP_DS__DS_MAX_SRC2_U64
8099 
8100  GPUStaticInst*
8102  {
8103  return new Inst_DS__DS_AND_SRC2_B64(&iFmt->iFmt_DS);
8104  } // decode_OP_DS__DS_AND_SRC2_B64
8105 
8106  GPUStaticInst*
8108  {
8109  return new Inst_DS__DS_OR_SRC2_B64(&iFmt->iFmt_DS);
8110  } // decode_OP_DS__DS_OR_SRC2_B64
8111 
8112  GPUStaticInst*
8114  {
8115  return new Inst_DS__DS_XOR_SRC2_B64(&iFmt->iFmt_DS);
8116  } // decode_OP_DS__DS_XOR_SRC2_B64
8117 
8118  GPUStaticInst*
8120  {
8121  return new Inst_DS__DS_WRITE_SRC2_B64(&iFmt->iFmt_DS);
8122  } // decode_OP_DS__DS_WRITE_SRC2_B64
8123 
8124  GPUStaticInst*
8126  {
8127  return new Inst_DS__DS_MIN_SRC2_F64(&iFmt->iFmt_DS);
8128  } // decode_OP_DS__DS_MIN_SRC2_F64
8129 
8130  GPUStaticInst*
8132  {
8133  return new Inst_DS__DS_MAX_SRC2_F64(&iFmt->iFmt_DS);
8134  } // decode_OP_DS__DS_MAX_SRC2_F64
8135 
8136  GPUStaticInst*
8138  {
8139  return new Inst_DS__DS_WRITE_B96(&iFmt->iFmt_DS);
8140  } // decode_OP_DS__DS_WRITE_B96
8141 
8142  GPUStaticInst*
8144  {
8145  return new Inst_DS__DS_WRITE_B128(&iFmt->iFmt_DS);
8146  } // decode_OP_DS__DS_WRITE_B128
8147 
8148  GPUStaticInst*
8150  {
8151  return new Inst_DS__DS_READ_B96(&iFmt->iFmt_DS);
8152  } // decode_OP_DS__DS_READ_B96
8153 
8154  GPUStaticInst*
8156  {
8157  return new Inst_DS__DS_READ_B128(&iFmt->iFmt_DS);
8158  } // decode_OP_DS__DS_READ_B128
8159 
8160  GPUStaticInst*
8162  {
8163  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
8164  } // decode_OP_FLAT__FLAT_LOAD_UBYTE
8165 
8166  GPUStaticInst*
8168  {
8169  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
8170  } // decode_OP_FLAT__FLAT_LOAD_SBYTE
8171 
8172  GPUStaticInst*
8174  {
8175  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
8176  } // decode_OP_FLAT__FLAT_LOAD_USHORT
8177 
8178  GPUStaticInst*
8180  {
8181  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
8182  } // decode_OP_FLAT__FLAT_LOAD_SSHORT
8183 
8184  GPUStaticInst*
8186  {
8187  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
8188  } // decode_OP_FLAT__FLAT_LOAD_DWORD
8189 
8190  GPUStaticInst*
8192  {
8193  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
8194  } // decode_OP_FLAT__FLAT_LOAD_DWORDX2
8195 
8196  GPUStaticInst*
8198  {
8199  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
8200  } // decode_OP_FLAT__FLAT_LOAD_DWORDX3
8201 
8202  GPUStaticInst*
8204  {
8205  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
8206  } // decode_OP_FLAT__FLAT_LOAD_DWORDX4
8207 
8208  GPUStaticInst*
8210  {
8211  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
8212  } // decode_OP_FLAT__FLAT_STORE_BYTE
8213 
8214  GPUStaticInst*
8216  {
8217  fatal("Trying to decode instruction without a class\n");
8218  return nullptr;
8219  }
8220 
8221  GPUStaticInst*
8223  {
8224  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
8225  } // decode_OP_FLAT__FLAT_STORE_SHORT
8226 
8227  GPUStaticInst*
8229  {
8230  fatal("Trying to decode instruction without a class\n");
8231  return nullptr;
8232  }
8233 
8234  GPUStaticInst*
8236  {
8237  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
8238  } // decode_OP_FLAT__FLAT_STORE_DWORD
8239 
8240  GPUStaticInst*
8242  {
8243  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
8244  } // decode_OP_FLAT__FLAT_STORE_DWORDX2
8245 
8246  GPUStaticInst*
8248  {
8249  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
8250  } // decode_OP_FLAT__FLAT_STORE_DWORDX3
8251 
8252  GPUStaticInst*
8254  {
8255  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
8256  } // decode_OP_FLAT__FLAT_STORE_DWORDX4
8257 
8258  GPUStaticInst*
8260  {
8261  fatal("Trying to decode instruction without a class\n");
8262  return nullptr;
8263  }
8264 
8265  GPUStaticInst*
8267  {
8268  fatal("Trying to decode instruction without a class\n");
8269  return nullptr;
8270  }
8271 
8272  GPUStaticInst*
8274  {
8275  fatal("Trying to decode instruction without a class\n");
8276  return nullptr;
8277  }
8278 
8279  GPUStaticInst*
8281  {
8282  fatal("Trying to decode instruction without a class\n");
8283  return nullptr;
8284  }
8285 
8286  GPUStaticInst*
8288  {
8289  fatal("Trying to decode instruction without a class\n");
8290  return nullptr;
8291  }
8292 
8293  GPUStaticInst*
8295  {
8296  fatal("Trying to decode instruction without a class\n");
8297  return nullptr;
8298  }
8299 
8300  GPUStaticInst*
8302  {
8303  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
8304  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP
8305 
8306  GPUStaticInst*
8308  {
8309  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
8310  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
8311 
8312  GPUStaticInst*
8314  {
8315  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
8316  } // decode_OP_FLAT__FLAT_ATOMIC_ADD
8317 
8318  GPUStaticInst*
8320  {
8321  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
8322  } // decode_OP_FLAT__FLAT_ATOMIC_SUB
8323 
8324  GPUStaticInst*
8326  {
8327  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
8328  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN
8329 
8330  GPUStaticInst*
8332  {
8333  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
8334  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN
8335 
8336  GPUStaticInst*
8338  {
8339  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
8340  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX
8341 
8342  GPUStaticInst*
8344  {
8345  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
8346  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX
8347 
8348  GPUStaticInst*
8350  {
8351  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
8352  } // decode_OP_FLAT__FLAT_ATOMIC_AND
8353 
8354  GPUStaticInst*
8356  {
8357  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
8358  } // decode_OP_FLAT__FLAT_ATOMIC_OR
8359 
8360  GPUStaticInst*
8362  {
8363  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
8364  } // decode_OP_FLAT__FLAT_ATOMIC_XOR
8365 
8366  GPUStaticInst*
8368  {
8369  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
8370  } // decode_OP_FLAT__FLAT_ATOMIC_INC
8371 
8372  GPUStaticInst*
8374  {
8375  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
8376  } // decode_OP_FLAT__FLAT_ATOMIC_DEC
8377 
8378  GPUStaticInst*
8380  {
8381  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
8382  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
8383 
8384  GPUStaticInst*
8386  {
8387  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
8388  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
8389 
8390  GPUStaticInst*
8392  {
8393  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
8394  } // decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
8395 
8396  GPUStaticInst*
8398  {
8399  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
8400  } // decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
8401 
8402  GPUStaticInst*
8404  {
8405  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
8406  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
8407 
8408  GPUStaticInst*
8410  {
8411  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
8412  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
8413 
8414  GPUStaticInst*
8416  {
8417  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
8418  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
8419 
8420  GPUStaticInst*
8422  {
8423  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
8424  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
8425 
8426  GPUStaticInst*
8428  {
8429  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
8430  } // decode_OP_FLAT__FLAT_ATOMIC_AND_X2
8431 
8432  GPUStaticInst*
8434  {
8435  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
8436  } // decode_OP_FLAT__FLAT_ATOMIC_OR_X2
8437 
8438  GPUStaticInst*
8440  {
8441  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
8442  } // decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
8443 
8444  GPUStaticInst*
8446  {
8447  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
8448  } // decode_OP_FLAT__FLAT_ATOMIC_INC_X2
8449 
8450  GPUStaticInst*
8452  {
8453  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
8454  } // decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
8455 
8456  GPUStaticInst*
8458  {
8459  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
8460  }
8461 
8462  GPUStaticInst*
8464  {
8465  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
8466  }
8467 
8468  GPUStaticInst*
8470  {
8471  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
8472  }
8473 
8474  GPUStaticInst*
8476  {
8477  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
8478  }
8479 
8480  GPUStaticInst*
8482  {
8483  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
8484  }
8485 
8486  GPUStaticInst*
8488  {
8489  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
8490  }
8491 
8492  GPUStaticInst*
8494  {
8495  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
8496  }
8497 
8498  GPUStaticInst*
8500  {
8501  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
8502  }
8503 
8504  GPUStaticInst*
8506  {
8507  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
8508  }
8509 
8510  GPUStaticInst*
8512  {
8513  fatal("Trying to decode instruction without a class\n");
8514  return nullptr;
8515  }
8516 
8517  GPUStaticInst*
8519  {
8520  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
8521  }
8522 
8523  GPUStaticInst*
8525  {
8526  fatal("Trying to decode instruction without a class\n");
8527  return nullptr;
8528  }
8529 
8530  GPUStaticInst*
8532  {
8533  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
8534  return nullptr;
8535  }
8536 
8537  GPUStaticInst*
8539  {
8540  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
8541  }
8542 
8543  GPUStaticInst*
8545  {
8546  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
8547  }
8548 
8549  GPUStaticInst*
8551  {
8552  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
8553  }
8554 
8555  GPUStaticInst*
8557  {
8558  fatal("Trying to decode instruction without a class\n");
8559  return nullptr;
8560  }
8561 
8562  GPUStaticInst*
8564  {
8565  fatal("Trying to decode instruction without a class\n");
8566  return nullptr;
8567  }
8568 
8569  GPUStaticInst*
8571  {
8572  fatal("Trying to decode instruction without a class\n");
8573  return nullptr;
8574  }
8575 
8576  GPUStaticInst*
8578  {
8579  fatal("Trying to decode instruction without a class\n");
8580  return nullptr;
8581  }
8582 
8583  GPUStaticInst*
8585  {
8586  fatal("Trying to decode instruction without a class\n");
8587  return nullptr;
8588  }
8589 
8590  GPUStaticInst*
8592  {
8593  fatal("Trying to decode instruction without a class\n");
8594  return nullptr;
8595  }
8596 
8597  GPUStaticInst*
8599  {
8600  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
8601  }
8602 
8603  GPUStaticInst*
8605  {
8606  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
8607  }
8608 
8609  GPUStaticInst*
8611  {
8612  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
8613  }
8614 
8615  GPUStaticInst*
8617  {
8618  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
8619  }
8620 
8621  GPUStaticInst*
8623  {
8624  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
8625  }
8626 
8627  GPUStaticInst*
8629  {
8630  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
8631  }
8632 
8633  GPUStaticInst*
8635  {
8636  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
8637  }
8638 
8639  GPUStaticInst*
8641  {
8642  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
8643  }
8644 
8645  GPUStaticInst*
8647  {
8648  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
8649  }
8650 
8651  GPUStaticInst*
8653  {
8654  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
8655  }
8656 
8657  GPUStaticInst*
8659  {
8660  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
8661  }
8662 
8663  GPUStaticInst*
8665  {
8666  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
8667  }
8668 
8669  GPUStaticInst*
8671  {
8672  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
8673  }
8674 
8675  GPUStaticInst*
8677  {
8678  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
8679  }
8680 
8681  GPUStaticInst*
8683  {
8684  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
8685  }
8686 
8687  GPUStaticInst*
8689  {
8690  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
8691  }
8692 
8693  GPUStaticInst*
8695  {
8696  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
8697  }
8698 
8699  GPUStaticInst*
8701  {
8702  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
8703  }
8704 
8705  GPUStaticInst*
8707  {
8708  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
8709  }
8710 
8711  GPUStaticInst*
8713  {
8714  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
8715  }
8716 
8717  GPUStaticInst*
8719  {
8720  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
8721  }
8722 
8723  GPUStaticInst*
8725  {
8726  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
8727  }
8728 
8729  GPUStaticInst*
8731  {
8732  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
8733  }
8734 
8735  GPUStaticInst*
8737  {
8738  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
8739  }
8740 
8741  GPUStaticInst*
8743  {
8744  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
8745  }
8746 
8747  GPUStaticInst*
8749  {
8750  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
8751  }
8752 
8753  GPUStaticInst*
8755  {
8756  return new Inst_MIMG__IMAGE_LOAD(&iFmt->iFmt_MIMG);
8757  } // decode_OP_MIMG__IMAGE_LOAD
8758 
8759  GPUStaticInst*
8761  {
8762  return new Inst_MIMG__IMAGE_LOAD_MIP(&iFmt->iFmt_MIMG);
8763  } // decode_OP_MIMG__IMAGE_LOAD_MIP
8764 
8765  GPUStaticInst*
8767  {
8768  return new Inst_MIMG__IMAGE_LOAD_PCK(&iFmt->iFmt_MIMG);
8769  } // decode_OP_MIMG__IMAGE_LOAD_PCK
8770 
8771  GPUStaticInst*
8773  {
8774  return new Inst_MIMG__IMAGE_LOAD_PCK_SGN(&iFmt->iFmt_MIMG);
8775  } // decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
8776 
8777  GPUStaticInst*
8779  {
8780  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK(&iFmt->iFmt_MIMG);
8781  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
8782 
8783  GPUStaticInst*
8785  {
8786  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(&iFmt->iFmt_MIMG);
8787  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
8788 
8789  GPUStaticInst*
8791  {
8792  return new Inst_MIMG__IMAGE_STORE(&iFmt->iFmt_MIMG);
8793  } // decode_OP_MIMG__IMAGE_STORE
8794 
8795  GPUStaticInst*
8797  {
8798  return new Inst_MIMG__IMAGE_STORE_MIP(&iFmt->iFmt_MIMG);
8799  } // decode_OP_MIMG__IMAGE_STORE_MIP
8800 
8801  GPUStaticInst*
8803  {
8804  return new Inst_MIMG__IMAGE_STORE_PCK(&iFmt->iFmt_MIMG);
8805  } // decode_OP_MIMG__IMAGE_STORE_PCK
8806 
8807  GPUStaticInst*
8809  {
8810  return new Inst_MIMG__IMAGE_STORE_MIP_PCK(&iFmt->iFmt_MIMG);
8811  } // decode_OP_MIMG__IMAGE_STORE_MIP_PCK
8812 
8813  GPUStaticInst*
8815  {
8816  return new Inst_MIMG__IMAGE_GET_RESINFO(&iFmt->iFmt_MIMG);
8817  } // decode_OP_MIMG__IMAGE_GET_RESINFO
8818 
8819  GPUStaticInst*
8821  {
8822  return new Inst_MIMG__IMAGE_ATOMIC_SWAP(&iFmt->iFmt_MIMG);
8823  } // decode_OP_MIMG__IMAGE_ATOMIC_SWAP
8824 
8825  GPUStaticInst*
8827  {
8828  return new Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(&iFmt->iFmt_MIMG);
8829  } // decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
8830 
8831  GPUStaticInst*
8833  {
8834  return new Inst_MIMG__IMAGE_ATOMIC_ADD(&iFmt->iFmt_MIMG);
8835  } // decode_OP_MIMG__IMAGE_ATOMIC_ADD
8836 
8837  GPUStaticInst*
8839  {
8840  return new Inst_MIMG__IMAGE_ATOMIC_SUB(&iFmt->iFmt_MIMG);
8841  } // decode_OP_MIMG__IMAGE_ATOMIC_SUB
8842 
8843  GPUStaticInst*
8845  {
8846  return new Inst_MIMG__IMAGE_ATOMIC_SMIN(&iFmt->iFmt_MIMG);
8847  } // decode_OP_MIMG__IMAGE_ATOMIC_SMIN
8848 
8849  GPUStaticInst*
8851  {
8852  return new Inst_MIMG__IMAGE_ATOMIC_UMIN(&iFmt->iFmt_MIMG);
8853  } // decode_OP_MIMG__IMAGE_ATOMIC_UMIN
8854 
8855  GPUStaticInst*
8857  {
8858  return new Inst_MIMG__IMAGE_ATOMIC_SMAX(&iFmt->iFmt_MIMG);
8859  } // decode_OP_MIMG__IMAGE_ATOMIC_SMAX
8860 
8861  GPUStaticInst*
8863  {
8864  return new Inst_MIMG__IMAGE_ATOMIC_UMAX(&iFmt->iFmt_MIMG);
8865  } // decode_OP_MIMG__IMAGE_ATOMIC_UMAX
8866 
8867  GPUStaticInst*
8869  {
8870  return new Inst_MIMG__IMAGE_ATOMIC_AND(&iFmt->iFmt_MIMG);
8871  } // decode_OP_MIMG__IMAGE_ATOMIC_AND
8872 
8873  GPUStaticInst*
8875  {
8876  return new Inst_MIMG__IMAGE_ATOMIC_OR(&iFmt->iFmt_MIMG);
8877  } // decode_OP_MIMG__IMAGE_ATOMIC_OR
8878 
8879  GPUStaticInst*
8881  {
8882  return new Inst_MIMG__IMAGE_ATOMIC_XOR(&iFmt->iFmt_MIMG);
8883  } // decode_OP_MIMG__IMAGE_ATOMIC_XOR
8884 
8885  GPUStaticInst*
8887  {
8888  return new Inst_MIMG__IMAGE_ATOMIC_INC(&iFmt->iFmt_MIMG);
8889  } // decode_OP_MIMG__IMAGE_ATOMIC_INC
8890 
8891  GPUStaticInst*
8893  {
8894  return new Inst_MIMG__IMAGE_ATOMIC_DEC(&iFmt->iFmt_MIMG);
8895  } // decode_OP_MIMG__IMAGE_ATOMIC_DEC
8896 
8897  GPUStaticInst*
8899  {
8900  return new Inst_MIMG__IMAGE_SAMPLE(&iFmt->iFmt_MIMG);
8901  } // decode_OP_MIMG__IMAGE_SAMPLE
8902 
8903  GPUStaticInst*
8905  {
8906  return new Inst_MIMG__IMAGE_SAMPLE_CL(&iFmt->iFmt_MIMG);
8907  } // decode_OP_MIMG__IMAGE_SAMPLE_CL
8908 
8909  GPUStaticInst*
8911  {
8912  return new Inst_MIMG__IMAGE_SAMPLE_D(&iFmt->iFmt_MIMG);
8913  } // decode_OP_MIMG__IMAGE_SAMPLE_D
8914 
8915  GPUStaticInst*
8917  {
8918  return new Inst_MIMG__IMAGE_SAMPLE_D_CL(&iFmt->iFmt_MIMG);
8919  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL
8920 
8921  GPUStaticInst*
8923  {
8924  return new Inst_MIMG__IMAGE_SAMPLE_L(&iFmt->iFmt_MIMG);
8925  } // decode_OP_MIMG__IMAGE_SAMPLE_L
8926 
8927  GPUStaticInst*
8929  {
8930  return new Inst_MIMG__IMAGE_SAMPLE_B(&iFmt->iFmt_MIMG);
8931  } // decode_OP_MIMG__IMAGE_SAMPLE_B
8932 
8933  GPUStaticInst*
8935  {
8936  return new Inst_MIMG__IMAGE_SAMPLE_B_CL(&iFmt->iFmt_MIMG);
8937  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL
8938 
8939  GPUStaticInst*
8941  {
8942  return new Inst_MIMG__IMAGE_SAMPLE_LZ(&iFmt->iFmt_MIMG);
8943  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ
8944 
8945  GPUStaticInst*
8947  {
8948  return new Inst_MIMG__IMAGE_SAMPLE_C(&iFmt->iFmt_MIMG);
8949  } // decode_OP_MIMG__IMAGE_SAMPLE_C
8950 
8951  GPUStaticInst*
8953  {
8954  return new Inst_MIMG__IMAGE_SAMPLE_C_CL(&iFmt->iFmt_MIMG);
8955  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL
8956 
8957  GPUStaticInst*
8959  {
8960  return new Inst_MIMG__IMAGE_SAMPLE_C_D(&iFmt->iFmt_MIMG);
8961  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D
8962 
8963  GPUStaticInst*
8965  {
8966  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL(&iFmt->iFmt_MIMG);
8967  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
8968 
8969  GPUStaticInst*
8971  {
8972  return new Inst_MIMG__IMAGE_SAMPLE_C_L(&iFmt->iFmt_MIMG);
8973  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L
8974 
8975  GPUStaticInst*
8977  {
8978  return new Inst_MIMG__IMAGE_SAMPLE_C_B(&iFmt->iFmt_MIMG);
8979  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B
8980 
8981  GPUStaticInst*
8983  {
8984  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL(&iFmt->iFmt_MIMG);
8985  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
8986 
8987  GPUStaticInst*
8989  {
8990  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ(&iFmt->iFmt_MIMG);
8991  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
8992 
8993  GPUStaticInst*
8995  {
8996  return new Inst_MIMG__IMAGE_SAMPLE_O(&iFmt->iFmt_MIMG);
8997  } // decode_OP_MIMG__IMAGE_SAMPLE_O
8998 
8999  GPUStaticInst*
9001  {
9002  return new Inst_MIMG__IMAGE_SAMPLE_CL_O(&iFmt->iFmt_MIMG);
9003  } // decode_OP_MIMG__IMAGE_SAMPLE_CL_O
9004 
9005  GPUStaticInst*
9007  {
9008  return new Inst_MIMG__IMAGE_SAMPLE_D_O(&iFmt->iFmt_MIMG);
9009  } // decode_OP_MIMG__IMAGE_SAMPLE_D_O
9010 
9011  GPUStaticInst*
9013  {
9014  return new Inst_MIMG__IMAGE_SAMPLE_D_CL_O(&iFmt->iFmt_MIMG);
9015  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
9016 
9017  GPUStaticInst*
9019  {
9020  return new Inst_MIMG__IMAGE_SAMPLE_L_O(&iFmt->iFmt_MIMG);
9021  } // decode_OP_MIMG__IMAGE_SAMPLE_L_O
9022 
9023  GPUStaticInst*
9025  {
9026  return new Inst_MIMG__IMAGE_SAMPLE_B_O(&iFmt->iFmt_MIMG);
9027  } // decode_OP_MIMG__IMAGE_SAMPLE_B_O
9028 
9029  GPUStaticInst*
9031  {
9032  return new Inst_MIMG__IMAGE_SAMPLE_B_CL_O(&iFmt->iFmt_MIMG);
9033  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
9034 
9035  GPUStaticInst*
9037  {
9038  return new Inst_MIMG__IMAGE_SAMPLE_LZ_O(&iFmt->iFmt_MIMG);
9039  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
9040 
9041  GPUStaticInst*
9043  {
9044  return new Inst_MIMG__IMAGE_SAMPLE_C_O(&iFmt->iFmt_MIMG);
9045  } // decode_OP_MIMG__IMAGE_SAMPLE_C_O
9046 
9047  GPUStaticInst*
9049  {
9050  return new Inst_MIMG__IMAGE_SAMPLE_C_CL_O(&iFmt->iFmt_MIMG);
9051  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
9052 
9053  GPUStaticInst*
9055  {
9056  return new Inst_MIMG__IMAGE_SAMPLE_C_D_O(&iFmt->iFmt_MIMG);
9057  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
9058 
9059  GPUStaticInst*
9061  {
9062  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(&iFmt->iFmt_MIMG);
9063  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
9064 
9065  GPUStaticInst*
9067  {
9068  return new Inst_MIMG__IMAGE_SAMPLE_C_L_O(&iFmt->iFmt_MIMG);
9069  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
9070 
9071  GPUStaticInst*
9073  {
9074  return new Inst_MIMG__IMAGE_SAMPLE_C_B_O(&iFmt->iFmt_MIMG);
9075  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
9076 
9077  GPUStaticInst*
9079  {
9080  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(&iFmt->iFmt_MIMG);
9081  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
9082 
9083  GPUStaticInst*
9085  {
9086  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(&iFmt->iFmt_MIMG);
9087  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
9088 
9089  GPUStaticInst*
9091  {
9092  return new Inst_MIMG__IMAGE_GATHER4(&iFmt->iFmt_MIMG);
9093  } // decode_OP_MIMG__IMAGE_GATHER4
9094 
9095  GPUStaticInst*
9097  {
9098  return new Inst_MIMG__IMAGE_GATHER4_CL(&iFmt->iFmt_MIMG);
9099  } // decode_OP_MIMG__IMAGE_GATHER4_CL
9100 
9101  GPUStaticInst*
9103  {
9104  fatal("Trying to decode instruction without a class\n");
9105  return nullptr;
9106  }
9107 
9108  GPUStaticInst*
9110  {
9111  return new Inst_MIMG__IMAGE_GATHER4_L(&iFmt->iFmt_MIMG);
9112  } // decode_OP_MIMG__IMAGE_GATHER4_L
9113 
9114  GPUStaticInst*
9116  {
9117  return new Inst_MIMG__IMAGE_GATHER4_B(&iFmt->iFmt_MIMG);
9118  } // decode_OP_MIMG__IMAGE_GATHER4_B
9119 
9120  GPUStaticInst*
9122  {
9123  return new Inst_MIMG__IMAGE_GATHER4_B_CL(&iFmt->iFmt_MIMG);
9124  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL
9125 
9126  GPUStaticInst*
9128  {
9129  return new Inst_MIMG__IMAGE_GATHER4_LZ(&iFmt->iFmt_MIMG);
9130  } // decode_OP_MIMG__IMAGE_GATHER4_LZ
9131 
9132  GPUStaticInst*
9134  {
9135  return new Inst_MIMG__IMAGE_GATHER4_C(&iFmt->iFmt_MIMG);
9136  } // decode_OP_MIMG__IMAGE_GATHER4_C
9137 
9138  GPUStaticInst*
9140  {
9141  return new Inst_MIMG__IMAGE_GATHER4_C_CL(&iFmt->iFmt_MIMG);
9142  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL
9143 
9144  GPUStaticInst*
9146  {
9147  fatal("Trying to decode instruction without a class\n");
9148  return nullptr;
9149  }
9150 
9151  GPUStaticInst*
9153  {
9154  fatal("Trying to decode instruction without a class\n");
9155  return nullptr;
9156  }
9157 
9158  GPUStaticInst*
9160  {
9161  return new Inst_MIMG__IMAGE_GATHER4_C_L(&iFmt->iFmt_MIMG);
9162  } // decode_OP_MIMG__IMAGE_GATHER4_C_L
9163 
9164  GPUStaticInst*
9166  {
9167  return new Inst_MIMG__IMAGE_GATHER4_C_B(&iFmt->iFmt_MIMG);
9168  } // decode_OP_MIMG__IMAGE_GATHER4_C_B
9169 
9170  GPUStaticInst*
9172  {
9173  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL(&iFmt->iFmt_MIMG);
9174  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
9175 
9176  GPUStaticInst*
9178  {
9179  return new Inst_MIMG__IMAGE_GATHER4_C_LZ(&iFmt->iFmt_MIMG);
9180  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ
9181 
9182  GPUStaticInst*
9184  {
9185  return new Inst_MIMG__IMAGE_GATHER4_O(&iFmt->iFmt_MIMG);
9186  } // decode_OP_MIMG__IMAGE_GATHER4_O
9187 
9188  GPUStaticInst*
9190  {
9191  return new Inst_MIMG__IMAGE_GATHER4_CL_O(&iFmt->iFmt_MIMG);
9192  } // decode_OP_MIMG__IMAGE_GATHER4_CL_O
9193 
9194  GPUStaticInst*
9196  {
9197  return new Inst_MIMG__IMAGE_GATHER4_L_O(&iFmt->iFmt_MIMG);
9198  } // decode_OP_MIMG__IMAGE_GATHER4_L_O
9199 
9200  GPUStaticInst*
9202  {
9203  return new Inst_MIMG__IMAGE_GATHER4_B_O(&iFmt->iFmt_MIMG);
9204  } // decode_OP_MIMG__IMAGE_GATHER4_B_O
9205 
9206  GPUStaticInst*
9208  {
9209  return new Inst_MIMG__IMAGE_GATHER4_B_CL_O(&iFmt->iFmt_MIMG);
9210  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
9211 
9212  GPUStaticInst*
9214  {
9215  return new Inst_MIMG__IMAGE_GATHER4_LZ_O(&iFmt->iFmt_MIMG);
9216  } // decode_OP_MIMG__IMAGE_GATHER4_LZ_O
9217 
9218  GPUStaticInst*
9220  {
9221  return new Inst_MIMG__IMAGE_GATHER4_C_O(&iFmt->iFmt_MIMG);
9222  } // decode_OP_MIMG__IMAGE_GATHER4_C_O
9223 
9224  GPUStaticInst*
9226  {
9227  return new Inst_MIMG__IMAGE_GATHER4_C_CL_O(&iFmt->iFmt_MIMG);
9228  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
9229 
9230  GPUStaticInst*
9232  {
9233  return new Inst_MIMG__IMAGE_GATHER4_C_L_O(&iFmt->iFmt_MIMG);
9234  } // decode_OP_MIMG__IMAGE_GATHER4_C_L_O
9235 
9236  GPUStaticInst*
9238  {
9239  return new Inst_MIMG__IMAGE_GATHER4_C_B_O(&iFmt->iFmt_MIMG);
9240  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_O
9241 
9242  GPUStaticInst*
9244  {
9245  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(&iFmt->iFmt_MIMG);
9246  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
9247 
9248  GPUStaticInst*
9250  {
9251  return new Inst_MIMG__IMAGE_GATHER4_C_LZ_O(&iFmt->iFmt_MIMG);
9252  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
9253 
9254  GPUStaticInst*
9256  {
9257  return new Inst_MIMG__IMAGE_GET_LOD(&iFmt->iFmt_MIMG);
9258  } // decode_OP_MIMG__IMAGE_GET_LOD
9259 
9260  GPUStaticInst*
9262  {
9263  return new Inst_MIMG__IMAGE_SAMPLE_CD(&iFmt->iFmt_MIMG);
9264  } // decode_OP_MIMG__IMAGE_SAMPLE_CD
9265 
9266  GPUStaticInst*
9268  {
9269  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL(&iFmt->iFmt_MIMG);
9270  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
9271 
9272  GPUStaticInst*
9274  {
9275  return new Inst_MIMG__IMAGE_SAMPLE_C_CD(&iFmt->iFmt_MIMG);
9276  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD
9277 
9278  GPUStaticInst*
9280  {
9281  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(&iFmt->iFmt_MIMG);
9282  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
9283 
9284  GPUStaticInst*
9286  {
9287  return new Inst_MIMG__IMAGE_SAMPLE_CD_O(&iFmt->iFmt_MIMG);
9288  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_O
9289 
9290  GPUStaticInst*
9292  {
9293  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(&iFmt->iFmt_MIMG);
9294  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
9295 
9296  GPUStaticInst*
9298  {
9299  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_O(&iFmt->iFmt_MIMG);
9300  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
9301 
9302  GPUStaticInst*
9304  {
9305  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(&iFmt->iFmt_MIMG);
9306  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
9307 
9308  GPUStaticInst*
9310  {
9311  return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MTBUF);
9312  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
9313 
9314  GPUStaticInst*
9316  {
9318  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
9319 
9320  GPUStaticInst*
9322  {
9324  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
9325 
9326  GPUStaticInst*
9328  {
9330  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
9331 
9332  GPUStaticInst*
9334  {
9336  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
9337 
9338  GPUStaticInst*
9340  {
9342  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
9343 
9344  GPUStaticInst*
9346  {
9348  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
9349 
9350  GPUStaticInst*
9352  {
9354  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
9355 
9356  GPUStaticInst*
9358  {
9360  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
9361 
9362  GPUStaticInst*
9364  {
9366  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
9367 
9368  GPUStaticInst*
9370  {
9372  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
9373 
9374  GPUStaticInst*
9376  {
9378  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
9379 
9380  GPUStaticInst*
9382  {
9384  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
9385 
9386  GPUStaticInst*
9388  {
9390  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
9391 
9392  GPUStaticInst*
9394  {
9396  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
9397 
9398  GPUStaticInst*
9400  {
9401  return new
9403  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
9404 
9405  GPUStaticInst*
9407  {
9408  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MUBUF);
9409  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
9410 
9411  GPUStaticInst*
9413  {
9414  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MUBUF);
9415  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
9416 
9417  GPUStaticInst*
9419  {
9421  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
9422 
9423  GPUStaticInst*
9425  {
9427  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
9428 
9429  GPUStaticInst*
9431  {
9432  return new Inst_MUBUF__BUFFER_STORE_FORMAT_X(&iFmt->iFmt_MUBUF);
9433  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
9434 
9435  GPUStaticInst*
9437  {
9439  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
9440 
9441  GPUStaticInst*
9443  {
9445  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
9446 
9447  GPUStaticInst*
9449  {
9451  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
9452 
9453  GPUStaticInst*
9455  {
9457  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
9458 
9459  GPUStaticInst*
9461  {
9463  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
9464 
9465  GPUStaticInst*
9467  {
9469  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
9470 
9471  GPUStaticInst*
9473  {
9475  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
9476 
9477  GPUStaticInst*
9479  {
9481  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
9482 
9483  GPUStaticInst*
9485  {
9487  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
9488 
9489  GPUStaticInst*
9491  {
9493  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
9494 
9495  GPUStaticInst*
9497  {
9499  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
9500 
9501  GPUStaticInst*
9503  {
9504  return new Inst_MUBUF__BUFFER_LOAD_UBYTE(&iFmt->iFmt_MUBUF);
9505  } // decode_OP_MUBUF__BUFFER_LOAD_UBYTE
9506 
9507  GPUStaticInst*
9509  {
9510  return new Inst_MUBUF__BUFFER_LOAD_SBYTE(&iFmt->iFmt_MUBUF);
9511  } // decode_OP_MUBUF__BUFFER_LOAD_SBYTE
9512 
9513  GPUStaticInst*
9515  {
9516  return new Inst_MUBUF__BUFFER_LOAD_USHORT(&iFmt->iFmt_MUBUF);
9517  } // decode_OP_MUBUF__BUFFER_LOAD_USHORT
9518 
9519  GPUStaticInst*
9521  {
9522  return new Inst_MUBUF__BUFFER_LOAD_SSHORT(&iFmt->iFmt_MUBUF);
9523  } // decode_OP_MUBUF__BUFFER_LOAD_SSHORT
9524 
9525  GPUStaticInst*
9527  {
9528  return new Inst_MUBUF__BUFFER_LOAD_DWORD(&iFmt->iFmt_MUBUF);
9529  } // decode_OP_MUBUF__BUFFER_LOAD_DWORD
9530 
9531  GPUStaticInst*
9533  {
9534  return new Inst_MUBUF__BUFFER_LOAD_DWORDX2(&iFmt->iFmt_MUBUF);
9535  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
9536 
9537  GPUStaticInst*
9539  {
9540  return new Inst_MUBUF__BUFFER_LOAD_DWORDX3(&iFmt->iFmt_MUBUF);
9541  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
9542 
9543  GPUStaticInst*
9545  {
9546  return new Inst_MUBUF__BUFFER_LOAD_DWORDX4(&iFmt->iFmt_MUBUF);
9547  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
9548 
9549  GPUStaticInst*
9551  {
9552  return new Inst_MUBUF__BUFFER_STORE_BYTE(&iFmt->iFmt_MUBUF);
9553  } // decode_OP_MUBUF__BUFFER_STORE_BYTE
9554 
9555  GPUStaticInst*
9557  {
9558  fatal("Trying to decode instruction without a class\n");
9559  return nullptr;
9560  }
9561 
9562  GPUStaticInst*
9564  {
9565  return new Inst_MUBUF__BUFFER_STORE_SHORT(&iFmt->iFmt_MUBUF);
9566  } // decode_OP_MUBUF__BUFFER_STORE_SHORT
9567 
9568  GPUStaticInst*
9570  {
9571  fatal("Trying to decode instruction without a class\n");
9572  return nullptr;
9573  }
9574 
9575  GPUStaticInst*
9577  {
9578  return new Inst_MUBUF__BUFFER_STORE_DWORD(&iFmt->iFmt_MUBUF);
9579  } // decode_OP_MUBUF__BUFFER_STORE_DWORD
9580 
9581  GPUStaticInst*
9583  {
9584  return new Inst_MUBUF__BUFFER_STORE_DWORDX2(&iFmt->iFmt_MUBUF);
9585  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX2
9586 
9587  GPUStaticInst*
9589  {
9590  return new Inst_MUBUF__BUFFER_STORE_DWORDX3(&iFmt->iFmt_MUBUF);
9591  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX3
9592 
9593  GPUStaticInst*
9595  {
9596  return new Inst_MUBUF__BUFFER_STORE_DWORDX4(&iFmt->iFmt_MUBUF);
9597  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX4
9598 
9599  GPUStaticInst*
9601  {
9603  } // decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
9604 
9605  GPUStaticInst*
9607  {
9608  return new Inst_MUBUF__BUFFER_WBINVL1(&iFmt->iFmt_MUBUF);
9609  } // decode_OP_MUBUF__BUFFER_WBINVL1
9610 
9611  GPUStaticInst*
9613  {
9614  return new Inst_MUBUF__BUFFER_WBINVL1_VOL(&iFmt->iFmt_MUBUF);
9615  } // decode_OP_MUBUF__BUFFER_WBINVL1_VOL
9616 
9617  GPUStaticInst*
9619  {
9620  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP(&iFmt->iFmt_MUBUF);
9621  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
9622 
9623  GPUStaticInst*
9625  {
9626  return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(&iFmt->iFmt_MUBUF);
9627  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
9628 
9629  GPUStaticInst*
9631  {
9632  return new Inst_MUBUF__BUFFER_ATOMIC_ADD(&iFmt->iFmt_MUBUF);
9633  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD
9634 
9635  GPUStaticInst*
9637  {
9638  return new Inst_MUBUF__BUFFER_ATOMIC_SUB(&iFmt->iFmt_MUBUF);
9639  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB
9640 
9641  GPUStaticInst*
9643  {
9644  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN(&iFmt->iFmt_MUBUF);
9645  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
9646 
9647  GPUStaticInst*
9649  {
9650  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN(&iFmt->iFmt_MUBUF);
9651  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
9652 
9653  GPUStaticInst*
9655  {
9656  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX(&iFmt->iFmt_MUBUF);
9657  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
9658 
9659  GPUStaticInst*
9661  {
9662  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX(&iFmt->iFmt_MUBUF);
9663  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
9664 
9665  GPUStaticInst*
9667  {
9668  return new Inst_MUBUF__BUFFER_ATOMIC_AND(&iFmt->iFmt_MUBUF);
9669  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND
9670 
9671  GPUStaticInst*
9673  {
9674  return new Inst_MUBUF__BUFFER_ATOMIC_OR(&iFmt->iFmt_MUBUF);
9675  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR
9676 
9677  GPUStaticInst*
9679  {
9680  return new Inst_MUBUF__BUFFER_ATOMIC_XOR(&iFmt->iFmt_MUBUF);
9681  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR
9682 
9683  GPUStaticInst*
9685  {
9686  return new Inst_MUBUF__BUFFER_ATOMIC_INC(&iFmt->iFmt_MUBUF);
9687  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC
9688 
9689  GPUStaticInst*
9691  {
9692  return new Inst_MUBUF__BUFFER_ATOMIC_DEC(&iFmt->iFmt_MUBUF);
9693  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC
9694 
9695  GPUStaticInst*
9697  {
9698  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(&iFmt->iFmt_MUBUF);
9699  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
9700 
9701  GPUStaticInst*
9703  {
9705  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
9706 
9707  GPUStaticInst*
9709  {
9710  return new Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(&iFmt->iFmt_MUBUF);
9711  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
9712 
9713  GPUStaticInst*
9715  {
9716  return new Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(&iFmt->iFmt_MUBUF);
9717  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
9718 
9719  GPUStaticInst*
9721  {
9722  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(&iFmt->iFmt_MUBUF);
9723  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
9724 
9725  GPUStaticInst*
9727  {
9728  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(&iFmt->iFmt_MUBUF);
9729  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
9730 
9731  GPUStaticInst*
9733  {
9734  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(&iFmt->iFmt_MUBUF);
9735  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
9736 
9737  GPUStaticInst*
9739  {
9740  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(&iFmt->iFmt_MUBUF);
9741  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
9742 
9743  GPUStaticInst*
9745  {
9746  return new Inst_MUBUF__BUFFER_ATOMIC_AND_X2(&iFmt->iFmt_MUBUF);
9747  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
9748 
9749  GPUStaticInst*
9751  {
9752  return new Inst_MUBUF__BUFFER_ATOMIC_OR_X2(&iFmt->iFmt_MUBUF);
9753  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
9754 
9755  GPUStaticInst*
9757  {
9758  return new Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(&iFmt->iFmt_MUBUF);
9759  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
9760 
9761  GPUStaticInst*
9763  {
9764  return new Inst_MUBUF__BUFFER_ATOMIC_INC_X2(&iFmt->iFmt_MUBUF);
9765  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
9766 
9767  GPUStaticInst*
9769  {
9770  return new Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(&iFmt->iFmt_MUBUF);
9771  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
9772 
9773  GPUStaticInst*
9775  {
9776  fatal("Trying to decode instruction without a class\n");
9777  return nullptr;
9778  }
9779 
9780  GPUStaticInst*
9782  {
9783  fatal("Trying to decode instruction without a class\n");
9784  return nullptr;
9785  }
9786 
9787  GPUStaticInst*
9789  {
9790  fatal("Trying to decode instruction without a class\n");
9791  return nullptr;
9792  }
9793 
9794  GPUStaticInst*
9796  {
9797  fatal("Trying to decode instruction without a class\n");
9798  return nullptr;
9799  }
9800 
9801  GPUStaticInst*
9803  {
9804  fatal("Trying to decode instruction without a class\n");
9805  return nullptr;
9806  }
9807 
9808  GPUStaticInst*
9810  {
9811  fatal("Trying to decode instruction without a class\n");
9812  return nullptr;
9813  }
9814 
9815  GPUStaticInst*
9817  {
9818  fatal("Trying to decode instruction without a class\n");
9819  return nullptr;
9820  }
9821 
9822  GPUStaticInst*
9824  {
9825  fatal("Trying to decode instruction without a class\n");
9826  return nullptr;
9827  }
9828 
9829  GPUStaticInst*
9831  {
9832  fatal("Trying to decode instruction without a class\n");
9833  return nullptr;
9834  }
9835 
9836  GPUStaticInst*
9838  {
9839  fatal("Trying to decode instruction without a class\n");
9840  return nullptr;
9841  }
9842 
9843  GPUStaticInst*
9845  {
9846  fatal("Trying to decode instruction without a class\n");
9847  return nullptr;
9848  }
9849 
9850  GPUStaticInst*
9852  {
9853  fatal("Trying to decode instruction without a class\n");
9854  return nullptr;
9855  }
9856 
9857  GPUStaticInst*
9859  {
9860  fatal("Trying to decode instruction without a class\n");
9861  return nullptr;
9862  }
9863 
9864  GPUStaticInst*
9866  {
9867  fatal("Trying to decode instruction without a class\n");
9868  return nullptr;
9869  }
9870 
9871  GPUStaticInst*
9873  {
9874  fatal("Trying to decode instruction without a class\n");
9875  return nullptr;
9876  }
9877 
9878  GPUStaticInst*
9880  {
9881  fatal("Trying to decode instruction without a class\n");
9882  return nullptr;
9883  }
9884 
9885  GPUStaticInst*
9887  {
9888  fatal("Trying to decode instruction without a class\n");
9889  return nullptr;
9890  }
9891 
9892  GPUStaticInst*
9894  {
9895  fatal("Trying to decode instruction without a class\n");
9896  return nullptr;
9897  }
9898 
9899  GPUStaticInst*
9901  {
9902  fatal("Trying to decode instruction without a class\n");
9903  return nullptr;
9904  }
9905 
9906  GPUStaticInst*
9908  {
9909  fatal("Trying to decode instruction without a class\n");
9910  return nullptr;
9911  }
9912 
9913  GPUStaticInst*
9915  {
9916  fatal("Trying to decode instruction without a class\n");
9917  return nullptr;
9918  }
9919 
9920  GPUStaticInst*
9922  {
9923  fatal("Trying to decode instruction without a class\n");
9924  return nullptr;
9925  }
9926 
9927  GPUStaticInst*
9929  {
9930  return new Inst_SMEM__S_LOAD_DWORD(&iFmt->iFmt_SMEM);
9931  } // decode_OP_SMEM__S_LOAD_DWORD
9932 
9933  GPUStaticInst*
9935  {
9936  return new Inst_SMEM__S_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
9937  } // decode_OP_SMEM__S_LOAD_DWORDX2
9938 
9939  GPUStaticInst*
9941  {
9942  return new Inst_SMEM__S_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
9943  } // decode_OP_SMEM__S_LOAD_DWORDX4
9944 
9945  GPUStaticInst*
9947  {
9948  return new Inst_SMEM__S_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
9949  } // decode_OP_SMEM__S_LOAD_DWORDX8
9950 
9951  GPUStaticInst*
9953  {
9954  return new Inst_SMEM__S_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
9955  } // decode_OP_SMEM__S_LOAD_DWORDX16
9956 
9957  GPUStaticInst*
9959  {
9960  fatal("Trying to decode instruction without a class\n");
9961  return nullptr;
9962  }
9963 
9964  GPUStaticInst*
9966  {
9967  fatal("Trying to decode instruction without a class\n");
9968  return nullptr;
9969  }
9970 
9971  GPUStaticInst*
9973  {
9974  fatal("Trying to decode instruction without a class\n");
9975  return nullptr;
9976  }
9977 
9978  GPUStaticInst*
9980  {
9981  return new Inst_SMEM__S_BUFFER_LOAD_DWORD(&iFmt->iFmt_SMEM);
9982  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORD
9983 
9984  GPUStaticInst*
9986  {
9987  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
9988  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
9989 
9990  GPUStaticInst*
9992  {
9993  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
9994  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
9995 
9996  GPUStaticInst*
9998  {
9999  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
10000  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
10001 
10002  GPUStaticInst*
10004  {
10005  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
10006  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
10007 
10008  GPUStaticInst*
10010  {
10011  return new Inst_SMEM__S_STORE_DWORD(&iFmt->iFmt_SMEM);
10012  } // decode_OP_SMEM__S_STORE_DWORD
10013 
10014  GPUStaticInst*
10016  {
10017  return new Inst_SMEM__S_STORE_DWORDX2(&iFmt->iFmt_SMEM);
10018  } // decode_OP_SMEM__S_STORE_DWORDX2
10019 
10020  GPUStaticInst*
10022  {
10023  return new Inst_SMEM__S_STORE_DWORDX4(&iFmt->iFmt_SMEM);
10024  } // decode_OP_SMEM__S_STORE_DWORDX4
10025 
10026  GPUStaticInst*
10028  {
10029  fatal("Trying to decode instruction without a class\n");
10030  return nullptr;
10031  }
10032 
10033  GPUStaticInst*
10035  {
10036  fatal("Trying to decode instruction without a class\n");
10037  return nullptr;
10038  }
10039 
10040  GPUStaticInst*
10042  {
10043  fatal("Trying to decode instruction without a class\n");
10044  return nullptr;
10045  }
10046 
10047  GPUStaticInst*
10049  {
10050  return new Inst_SMEM__S_BUFFER_STORE_DWORD(&iFmt->iFmt_SMEM);
10051  } // decode_OP_SMEM__S_BUFFER_STORE_DWORD
10052 
10053  GPUStaticInst*
10055  {
10056  return new Inst_SMEM__S_BUFFER_STORE_DWORDX2(&iFmt->iFmt_SMEM);
10057  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
10058 
10059  GPUStaticInst*
10061  {
10062  return new Inst_SMEM__S_BUFFER_STORE_DWORDX4(&iFmt->iFmt_SMEM);
10063  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
10064 
10065  GPUStaticInst*
10067  {
10068  fatal("Trying to decode instruction without a class\n");
10069  return nullptr;
10070  }
10071  GPUStaticInst*
10073  {
10074  fatal("Trying to decode instruction without a class\n");
10075  return nullptr;
10076  }
10077  GPUStaticInst*
10079  {
10080  fatal("Trying to decode instruction without a class\n");
10081  return nullptr;
10082  }
10083  GPUStaticInst*
10085  {
10086  fatal("Trying to decode instruction without a class\n");
10087  return nullptr;
10088  }
10089  GPUStaticInst*
10091  {
10092  fatal("Trying to decode instruction without a class\n");
10093  return nullptr;
10094  }
10095  GPUStaticInst*
10097  {
10098  fatal("Trying to decode instruction without a class\n");
10099  return nullptr;
10100  }
10101  GPUStaticInst*
10103  {
10104  fatal("Trying to decode instruction without a class\n");
10105  return nullptr;
10106  }
10107  GPUStaticInst*
10109  {
10110  fatal("Trying to decode instruction without a class\n");
10111  return nullptr;
10112  }
10113 
10114  GPUStaticInst*
10116  {
10117  return new Inst_SMEM__S_DCACHE_INV(&iFmt->iFmt_SMEM);
10118  } // decode_OP_SMEM__S_DCACHE_INV
10119 
10120  GPUStaticInst*
10122  {
10123  return new Inst_SMEM__S_DCACHE_WB(&iFmt->iFmt_SMEM);
10124  } // decode_OP_SMEM__S_DCACHE_WB
10125 
10126  GPUStaticInst*
10128  {
10129  return new Inst_SMEM__S_DCACHE_INV_VOL(&iFmt->iFmt_SMEM);
10130  } // decode_OP_SMEM__S_DCACHE_INV_VOL
10131 
10132  GPUStaticInst*
10134  {
10135  return new Inst_SMEM__S_DCACHE_WB_VOL(&iFmt->iFmt_SMEM);
10136  } // decode_OP_SMEM__S_DCACHE_WB_VOL
10137 
10138  GPUStaticInst*
10140  {
10141  return new Inst_SMEM__S_MEMTIME(&iFmt->iFmt_SMEM);
10142  } // decode_OP_SMEM__S_MEMTIME
10143 
10144  GPUStaticInst*
10146  {
10147  return new Inst_SMEM__S_MEMREALTIME(&iFmt->iFmt_SMEM);
10148  } // decode_OP_SMEM__S_MEMREALTIME
10149 
10150  GPUStaticInst*
10152  {
10153  return new Inst_SMEM__S_ATC_PROBE(&iFmt->iFmt_SMEM);
10154  } // decode_OP_SMEM__S_ATC_PROBE
10155 
10156  GPUStaticInst*
10158  {
10159  return new Inst_SMEM__S_ATC_PROBE_BUFFER(&iFmt->iFmt_SMEM);
10160  } // decode_OP_SMEM__S_ATC_PROBE_BUFFER
10161 
10162  GPUStaticInst*
10164  {
10165  fatal("Trying to decode instruction without a class\n");
10166  return nullptr;
10167  }
10168 
10169  GPUStaticInst*
10171  {
10172  fatal("Trying to decode instruction without a class\n");
10173  return nullptr;
10174  }
10175 
10176  GPUStaticInst*
10178  {
10179  fatal("Trying to decode instruction without a class\n");
10180  return nullptr;
10181  }
10182 
10183  GPUStaticInst*
10185  {
10186  fatal("Trying to decode instruction without a class\n");
10187  return nullptr;
10188  }
10189 
10190  GPUStaticInst*
10192  {
10193  fatal("Trying to decode instruction without a class\n");
10194  return nullptr;
10195  }
10196 
10197  GPUStaticInst*
10199  {
10200  fatal("Trying to decode instruction without a class\n");
10201  return nullptr;
10202  }
10203 
10204  GPUStaticInst*
10206  {
10207  fatal("Trying to decode instruction without a class\n");
10208  return nullptr;
10209  }
10210 
10211  GPUStaticInst*
10213  {
10214  fatal("Trying to decode instruction without a class\n");
10215  return nullptr;
10216  }
10217 
10218  GPUStaticInst*
10220  {
10221  fatal("Trying to decode instruction without a class\n");
10222  return nullptr;
10223  }
10224 
10225  GPUStaticInst*
10227  {
10228  fatal("Trying to decode instruction without a class\n");
10229  return nullptr;
10230  }
10231 
10232  GPUStaticInst*
10234  {
10235  fatal("Trying to decode instruction without a class\n");
10236  return nullptr;
10237  }
10238 
10239  GPUStaticInst*
10241  {
10242  fatal("Trying to decode instruction without a class\n");
10243  return nullptr;
10244  }
10245 
10246  GPUStaticInst*
10248  {
10249  fatal("Trying to decode instruction without a class\n");
10250  return nullptr;
10251  }
10252 
10253  GPUStaticInst*
10255  {
10256  fatal("Trying to decode instruction without a class\n");
10257  return nullptr;
10258  }
10259 
10260  GPUStaticInst*
10262  {
10263  fatal("Trying to decode instruction without a class\n");
10264  return nullptr;
10265  }
10266 
10267  GPUStaticInst*
10269  {
10270  fatal("Trying to decode instruction without a class\n");
10271  return nullptr;
10272  }
10273 
10274  GPUStaticInst*
10276  {
10277  fatal("Trying to decode instruction without a class\n");
10278  return nullptr;
10279  }
10280 
10281  GPUStaticInst*
10283  {
10284  fatal("Trying to decode instruction without a class\n");
10285  return nullptr;
10286  }
10287 
10288  GPUStaticInst*
10290  {
10291  fatal("Trying to decode instruction without a class\n");
10292  return nullptr;
10293  }
10294 
10295  GPUStaticInst*
10297  {
10298  fatal("Trying to decode instruction without a class\n");
10299  return nullptr;
10300  }
10301 
10302  GPUStaticInst*
10304  {
10305  fatal("Trying to decode instruction without a class\n");
10306  return nullptr;
10307  }
10308 
10309  GPUStaticInst*
10311  {
10312  fatal("Trying to decode instruction without a class\n");
10313  return nullptr;
10314  }
10315 
10316  GPUStaticInst*
10318  {
10319  fatal("Trying to decode instruction without a class\n");
10320  return nullptr;
10321  }
10322 
10323  GPUStaticInst*
10325  {
10326  fatal("Trying to decode instruction without a class\n");
10327  return nullptr;
10328  }
10329 
10330  GPUStaticInst*
10332  {
10333  fatal("Trying to decode instruction without a class\n");
10334  return nullptr;
10335  }
10336 
10337  GPUStaticInst*
10339  {
10340  fatal("Trying to decode instruction without a class\n");
10341  return nullptr;
10342  }
10343 
10344  GPUStaticInst*
10346  {
10347  fatal("Trying to decode instruction without a class\n");
10348  return nullptr;
10349  }
10350 
10351  GPUStaticInst*
10353  {
10354  fatal("Trying to decode instruction without a class\n");
10355  return nullptr;
10356  }
10357 
10358  GPUStaticInst*
10360  {
10361  fatal("Trying to decode instruction without a class\n");
10362  return nullptr;
10363  }
10364 
10365  GPUStaticInst*
10367  {
10368  fatal("Trying to decode instruction without a class\n");
10369  return nullptr;
10370  }
10371 
10372  GPUStaticInst*
10374  {
10375  fatal("Trying to decode instruction without a class\n");
10376  return nullptr;
10377  }
10378 
10379  GPUStaticInst*
10381  {
10382  fatal("Trying to decode instruction without a class\n");
10383  return nullptr;
10384  }
10385 
10386  GPUStaticInst*
10388  {
10389  fatal("Trying to decode instruction without a class\n");
10390  return nullptr;
10391  }
10392 
10393  GPUStaticInst*
10395  {
10396  fatal("Trying to decode instruction without a class\n");
10397  return nullptr;
10398  }
10399 
10400  GPUStaticInst*
10402  {
10403  fatal("Trying to decode instruction without a class\n");
10404  return nullptr;
10405  }
10406 
10407  GPUStaticInst*
10409  {
10410  fatal("Trying to decode instruction without a class\n");
10411  return nullptr;
10412  }
10413 
10414  GPUStaticInst*
10416  {
10417  fatal("Trying to decode instruction without a class\n");
10418  return nullptr;
10419  }
10420 
10421  GPUStaticInst*
10423  {
10424  fatal("Trying to decode instruction without a class\n");
10425  return nullptr;
10426  }
10427 
10428  GPUStaticInst*
10430  {
10431  fatal("Trying to decode instruction without a class\n");
10432  return nullptr;
10433  }
10434 
10435  GPUStaticInst*
10437  {
10438  fatal("Trying to decode instruction without a class\n");
10439  return nullptr;
10440  }
10441 
10442  GPUStaticInst*
10444  {
10445  fatal("Trying to decode instruction without a class\n");
10446  return nullptr;
10447  }
10448 
10449  GPUStaticInst*
10451  {
10452  fatal("Trying to decode instruction without a class\n");
10453  return nullptr;
10454  }
10455 
10456  GPUStaticInst*
10458  {
10459  fatal("Trying to decode instruction without a class\n");
10460  return nullptr;
10461  }
10462 
10463  GPUStaticInst*
10465  {
10466  fatal("Trying to decode instruction without a class\n");
10467  return nullptr;
10468  }
10469 
10470  GPUStaticInst*
10472  {
10473  fatal("Trying to decode instruction without a class\n");
10474  return nullptr;
10475  }
10476 
10477  GPUStaticInst*
10479  {
10480  fatal("Trying to decode instruction without a class\n");
10481  return nullptr;
10482  }
10483 
10484  GPUStaticInst*
10486  {
10487  fatal("Trying to decode instruction without a class\n");
10488  return nullptr;
10489  }
10490 
10491  GPUStaticInst*
10493  {
10494  fatal("Trying to decode instruction without a class\n");
10495  return nullptr;
10496  }
10497 
10498  GPUStaticInst*
10500  {
10501  fatal("Trying to decode instruction without a class\n");
10502  return nullptr;
10503  }
10504 
10505  GPUStaticInst*
10507  {
10508  fatal("Trying to decode instruction without a class\n");
10509  return nullptr;
10510  }
10511 
10512  GPUStaticInst*
10514  {
10515  fatal("Trying to decode instruction without a class\n");
10516  return nullptr;
10517  }
10518 
10519  GPUStaticInst*
10521  {
10522  fatal("Trying to decode instruction without a class\n");
10523  return nullptr;
10524  }
10525 
10526  GPUStaticInst*
10528  {
10529  fatal("Trying to decode instruction without a class\n");
10530  return nullptr;
10531  }
10532 
10533  GPUStaticInst*
10535  {
10536  fatal("Trying to decode instruction without a class\n");
10537  return nullptr;
10538  }
10539 
10540  GPUStaticInst*
10542  {
10543  return new Inst_SOP1__S_MOV_B32(&iFmt->iFmt_SOP1);
10544  } // decode_OP_SOP1__S_MOV_B32
10545 
10546  GPUStaticInst*
10548  {
10549  return new Inst_SOP1__S_MOV_B64(&iFmt->iFmt_SOP1);
10550  } // decode_OP_SOP1__S_MOV_B64
10551 
10552  GPUStaticInst*
10554  {
10555  return new Inst_SOP1__S_CMOV_B32(&iFmt->iFmt_SOP1);
10556  } // decode_OP_SOP1__S_CMOV_B32
10557 
10558  GPUStaticInst*
10560  {
10561  return new Inst_SOP1__S_CMOV_B64(&iFmt->iFmt_SOP1);
10562  } // decode_OP_SOP1__S_CMOV_B64
10563 
10564  GPUStaticInst*
10566  {
10567  return new Inst_SOP1__S_NOT_B32(&iFmt->iFmt_SOP1);
10568  } // decode_OP_SOP1__S_NOT_B32
10569 
10570  GPUStaticInst*
10572  {
10573  return new Inst_SOP1__S_NOT_B64(&iFmt->iFmt_SOP1);
10574  } // decode_OP_SOP1__S_NOT_B64
10575 
10576  GPUStaticInst*
10578  {
10579  return new Inst_SOP1__S_WQM_B32(&iFmt->iFmt_SOP1);
10580  } // decode_OP_SOP1__S_WQM_B32
10581 
10582  GPUStaticInst*
10584  {
10585  return new Inst_SOP1__S_WQM_B64(&iFmt->iFmt_SOP1);
10586  } // decode_OP_SOP1__S_WQM_B64
10587 
10588  GPUStaticInst*
10590  {
10591  return new Inst_SOP1__S_BREV_B32(&iFmt->iFmt_SOP1);
10592  } // decode_OP_SOP1__S_BREV_B32
10593 
10594  GPUStaticInst*
10596  {
10597  return new Inst_SOP1__S_BREV_B64(&iFmt->iFmt_SOP1);
10598  } // decode_OP_SOP1__S_BREV_B64
10599 
10600  GPUStaticInst*
10602  {
10603  return new Inst_SOP1__S_BCNT0_I32_B32(&iFmt->iFmt_SOP1);
10604  } // decode_OP_SOP1__S_BCNT0_I32_B32
10605 
10606  GPUStaticInst*
10608  {
10609  return new Inst_SOP1__S_BCNT0_I32_B64(&iFmt->iFmt_SOP1);
10610  } // decode_OP_SOP1__S_BCNT0_I32_B64
10611 
10612  GPUStaticInst*
10614  {
10615  return new Inst_SOP1__S_BCNT1_I32_B32(&iFmt->iFmt_SOP1);
10616  } // decode_OP_SOP1__S_BCNT1_I32_B32
10617 
10618  GPUStaticInst*
10620  {
10621  return new Inst_SOP1__S_BCNT1_I32_B64(&iFmt->iFmt_SOP1);
10622  } // decode_OP_SOP1__S_BCNT1_I32_B64
10623 
10624  GPUStaticInst*
10626  {
10627  return new Inst_SOP1__S_FF0_I32_B32(&iFmt->iFmt_SOP1);
10628  } // decode_OP_SOP1__S_FF0_I32_B32
10629 
10630  GPUStaticInst*
10632  {
10633  return new Inst_SOP1__S_FF0_I32_B64(&iFmt->iFmt_SOP1);
10634  } // decode_OP_SOP1__S_FF0_I32_B64
10635 
10636  GPUStaticInst*
10638  {
10639  return new Inst_SOP1__S_FF1_I32_B32(&iFmt->iFmt_SOP1);
10640  } // decode_OP_SOP1__S_FF1_I32_B32
10641 
10642  GPUStaticInst*
10644  {
10645  return new Inst_SOP1__S_FF1_I32_B64(&iFmt->iFmt_SOP1);
10646  } // decode_OP_SOP1__S_FF1_I32_B64
10647 
10648  GPUStaticInst*
10650  {
10651  return new Inst_SOP1__S_FLBIT_I32_B32(&iFmt->iFmt_SOP1);
10652  } // decode_OP_SOP1__S_FLBIT_I32_B32
10653 
10654  GPUStaticInst*
10656  {
10657  return new Inst_SOP1__S_FLBIT_I32_B64(&iFmt->iFmt_SOP1);
10658  } // decode_OP_SOP1__S_FLBIT_I32_B64
10659 
10660  GPUStaticInst*
10662  {
10663  return new Inst_SOP1__S_FLBIT_I32(&iFmt->iFmt_SOP1);
10664  } // decode_OP_SOP1__S_FLBIT_I32
10665 
10666  GPUStaticInst*
10668  {
10669  return new Inst_SOP1__S_FLBIT_I32_I64(&iFmt->iFmt_SOP1);
10670  } // decode_OP_SOP1__S_FLBIT_I32_I64
10671 
10672  GPUStaticInst*
10674  {
10675  return new Inst_SOP1__S_SEXT_I32_I8(&iFmt->iFmt_SOP1);
10676  } // decode_OP_SOP1__S_SEXT_I32_I8
10677 
10678  GPUStaticInst*
10680  {
10681  return new Inst_SOP1__S_SEXT_I32_I16(&iFmt->iFmt_SOP1);
10682  } // decode_OP_SOP1__S_SEXT_I32_I16
10683 
10684  GPUStaticInst*
10686  {
10687  return new Inst_SOP1__S_BITSET0_B32(&iFmt->iFmt_SOP1);
10688  } // decode_OP_SOP1__S_BITSET0_B32
10689 
10690  GPUStaticInst*
10692  {
10693  return new Inst_SOP1__S_BITSET0_B64(&iFmt->iFmt_SOP1);
10694  } // decode_OP_SOP1__S_BITSET0_B64
10695 
10696  GPUStaticInst*
10698  {
10699  return new Inst_SOP1__S_BITSET1_B32(&iFmt->iFmt_SOP1);
10700  } // decode_OP_SOP1__S_BITSET1_B32
10701 
10702  GPUStaticInst*
10704  {
10705  return new Inst_SOP1__S_BITSET1_B64(&iFmt->iFmt_SOP1);
10706  } // decode_OP_SOP1__S_BITSET1_B64
10707 
10708  GPUStaticInst*
10710  {
10711  return new Inst_SOP1__S_GETPC_B64(&iFmt->iFmt_SOP1);
10712  } // decode_OP_SOP1__S_GETPC_B64
10713 
10714  GPUStaticInst*
10716  {
10717  return new Inst_SOP1__S_SETPC_B64(&iFmt->iFmt_SOP1);
10718  } // decode_OP_SOP1__S_SETPC_B64
10719 
10720  GPUStaticInst*
10722  {
10723  return new Inst_SOP1__S_SWAPPC_B64(&iFmt->iFmt_SOP1);
10724  } // decode_OP_SOP1__S_SWAPPC_B64
10725 
10726  GPUStaticInst*
10728  {
10729  return new Inst_SOP1__S_RFE_B64(&iFmt->iFmt_SOP1);
10730  } // decode_OP_SOP1__S_RFE_B64
10731 
10732  GPUStaticInst*
10734  {
10735  return new Inst_SOP1__S_AND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10736  } // decode_OP_SOP1__S_AND_SAVEEXEC_B64
10737 
10738  GPUStaticInst*
10740  {
10741  return new Inst_SOP1__S_OR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10742  } // decode_OP_SOP1__S_OR_SAVEEXEC_B64
10743 
10744  GPUStaticInst*
10746  {
10747  return new Inst_SOP1__S_XOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10748  } // decode_OP_SOP1__S_XOR_SAVEEXEC_B64
10749 
10750  GPUStaticInst*
10752  {
10753  return new Inst_SOP1__S_ANDN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10754  } // decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
10755 
10756  GPUStaticInst*
10758  {
10759  return new Inst_SOP1__S_ORN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10760  } // decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
10761 
10762  GPUStaticInst*
10764  {
10765  return new Inst_SOP1__S_NAND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10766  } // decode_OP_SOP1__S_NAND_SAVEEXEC_B64
10767 
10768  GPUStaticInst*
10770  {
10771  return new Inst_SOP1__S_NOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10772  } // decode_OP_SOP1__S_NOR_SAVEEXEC_B64
10773 
10774  GPUStaticInst*
10776  {
10777  return new Inst_SOP1__S_XNOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10778  } // decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
10779 
10780  GPUStaticInst*
10782  {
10783  return new Inst_SOP1__S_QUADMASK_B32(&iFmt->iFmt_SOP1);
10784  } // decode_OP_SOP1__S_QUADMASK_B32
10785 
10786  GPUStaticInst*
10788  {
10789  return new Inst_SOP1__S_QUADMASK_B64(&iFmt->iFmt_SOP1);
10790  } // decode_OP_SOP1__S_QUADMASK_B64
10791 
10792  GPUStaticInst*
10794  {
10795  return new Inst_SOP1__S_MOVRELS_B32(&iFmt->iFmt_SOP1);
10796  } // decode_OP_SOP1__S_MOVRELS_B32
10797 
10798  GPUStaticInst*
10800  {
10801  return new Inst_SOP1__S_MOVRELS_B64(&iFmt->iFmt_SOP1);
10802  } // decode_OP_SOP1__S_MOVRELS_B64
10803 
10804  GPUStaticInst*
10806  {
10807  return new Inst_SOP1__S_MOVRELD_B32(&iFmt->iFmt_SOP1);
10808  } // decode_OP_SOP1__S_MOVRELD_B32
10809 
10810  GPUStaticInst*
10812  {
10813  return new Inst_SOP1__S_MOVRELD_B64(&iFmt->iFmt_SOP1);
10814  } // decode_OP_SOP1__S_MOVRELD_B64
10815 
10816  GPUStaticInst*
10818  {
10819  return new Inst_SOP1__S_CBRANCH_JOIN(&iFmt->iFmt_SOP1);
10820  } // decode_OP_SOP1__S_CBRANCH_JOIN
10821 
10822  GPUStaticInst*
10824  {
10825  return new Inst_SOP1__S_ABS_I32(&iFmt->iFmt_SOP1);
10826  } // decode_OP_SOP1__S_ABS_I32
10827 
10828  GPUStaticInst*
10830  {
10831  return new Inst_SOP1__S_SET_GPR_IDX_IDX(&iFmt->iFmt_SOP1);
10832  } // decode_OP_SOP1__S_SET_GPR_IDX_IDX
10833 
10834  GPUStaticInst*
10836  {
10837  fatal("Trying to decode instruction without a class\n");
10838  return nullptr;
10839  }
10840 
10841  GPUStaticInst*
10843  {
10844  fatal("Trying to decode instruction without a class\n");
10845  return nullptr;
10846  }
10847 
10848  GPUStaticInst*
10850  {
10851  fatal("Trying to decode instruction without a class\n");
10852  return nullptr;
10853  }
10854 
10855  GPUStaticInst*
10857  {
10858  fatal("Trying to decode instruction without a class\n");
10859  return nullptr;
10860  }
10861 
10862  GPUStaticInst*
10864  {
10865  fatal("Trying to decode instruction without a class\n");
10866  return nullptr;
10867  }
10868 
10869  GPUStaticInst*
10871  {
10872  return new Inst_SOPC__S_CMP_EQ_I32(&iFmt->iFmt_SOPC);
10873  } // decode_OP_SOPC__S_CMP_EQ_I32
10874 
10875  GPUStaticInst*
10877  {
10878  return new Inst_SOPC__S_CMP_LG_I32(&iFmt->iFmt_SOPC);
10879  } // decode_OP_SOPC__S_CMP_LG_I32
10880 
10881  GPUStaticInst*
10883  {
10884  return new Inst_SOPC__S_CMP_GT_I32(&iFmt->iFmt_SOPC);
10885  } // decode_OP_SOPC__S_CMP_GT_I32
10886 
10887  GPUStaticInst*
10889  {
10890  return new Inst_SOPC__S_CMP_GE_I32(&iFmt->iFmt_SOPC);
10891  } // decode_OP_SOPC__S_CMP_GE_I32
10892 
10893  GPUStaticInst*
10895  {
10896  return new Inst_SOPC__S_CMP_LT_I32(&iFmt->iFmt_SOPC);
10897  } // decode_OP_SOPC__S_CMP_LT_I32
10898 
10899  GPUStaticInst*
10901  {
10902  return new Inst_SOPC__S_CMP_LE_I32(&iFmt->iFmt_SOPC);
10903  } // decode_OP_SOPC__S_CMP_LE_I32
10904 
10905  GPUStaticInst*
10907  {
10908  return new Inst_SOPC__S_CMP_EQ_U32(&iFmt->iFmt_SOPC);
10909  } // decode_OP_SOPC__S_CMP_EQ_U32
10910 
10911  GPUStaticInst*
10913  {
10914  return new Inst_SOPC__S_CMP_LG_U32(&iFmt->iFmt_SOPC);
10915  } // decode_OP_SOPC__S_CMP_LG_U32
10916 
10917  GPUStaticInst*
10919  {
10920  return new Inst_SOPC__S_CMP_GT_U32(&iFmt->iFmt_SOPC);
10921  } // decode_OP_SOPC__S_CMP_GT_U32
10922 
10923  GPUStaticInst*
10925  {
10926  return new Inst_SOPC__S_CMP_GE_U32(&iFmt->iFmt_SOPC);
10927  } // decode_OP_SOPC__S_CMP_GE_U32
10928 
10929  GPUStaticInst*
10931  {
10932  return new Inst_SOPC__S_CMP_LT_U32(&iFmt->iFmt_SOPC);
10933  } // decode_OP_SOPC__S_CMP_LT_U32
10934 
10935  GPUStaticInst*
10937  {
10938  return new Inst_SOPC__S_CMP_LE_U32(&iFmt->iFmt_SOPC);
10939  } // decode_OP_SOPC__S_CMP_LE_U32
10940 
10941  GPUStaticInst*
10943  {
10944  return new Inst_SOPC__S_BITCMP0_B32(&iFmt->iFmt_SOPC);
10945  } // decode_OP_SOPC__S_BITCMP0_B32
10946 
10947  GPUStaticInst*
10949  {
10950  return new Inst_SOPC__S_BITCMP1_B32(&iFmt->iFmt_SOPC);
10951  } // decode_OP_SOPC__S_BITCMP1_B32
10952 
10953  GPUStaticInst*
10955  {
10956  return new Inst_SOPC__S_BITCMP0_B64(&iFmt->iFmt_SOPC);
10957  } // decode_OP_SOPC__S_BITCMP0_B64
10958 
10959  GPUStaticInst*
10961  {
10962  return new Inst_SOPC__S_BITCMP1_B64(&iFmt->iFmt_SOPC);
10963  } // decode_OP_SOPC__S_BITCMP1_B64
10964 
10965  GPUStaticInst*
10967  {
10968  return new Inst_SOPC__S_SETVSKIP(&iFmt->iFmt_SOPC);
10969  } // decode_OP_SOPC__S_SETVSKIP
10970 
10971  GPUStaticInst*
10973  {
10974  return new Inst_SOPC__S_SET_GPR_IDX_ON(&iFmt->iFmt_SOPC);
10975  } // decode_OP_SOPC__S_SET_GPR_IDX_ON
10976 
10977  GPUStaticInst*
10979  {
10980  return new Inst_SOPC__S_CMP_EQ_U64(&iFmt->iFmt_SOPC);
10981  } // decode_OP_SOPC__S_CMP_EQ_U64
10982 
10983  GPUStaticInst*
10985  {
10986  return new Inst_SOPC__S_CMP_LG_U64(&iFmt->iFmt_SOPC);
10987  } // decode_OP_SOPC__S_CMP_LG_U64
10988 
10989  GPUStaticInst*
10991  {
10992  return new Inst_SOPP__S_NOP(&iFmt->iFmt_SOPP);
10993  } // decode_OP_SOPP__S_NOP
10994 
10995  GPUStaticInst*
10997  {
10998  return new Inst_SOPP__S_ENDPGM(&iFmt->iFmt_SOPP);
10999  } // decode_OP_SOPP__S_ENDPGM
11000 
11001  GPUStaticInst*
11003  {
11004  return new Inst_SOPP__S_BRANCH(&iFmt->iFmt_SOPP);
11005  } // decode_OP_SOPP__S_BRANCH
11006 
11007  GPUStaticInst*
11009  {
11010  return new Inst_SOPP__S_WAKEUP(&iFmt->iFmt_SOPP);
11011  } // decode_OP_SOPP__S_WAKEUP
11012 
11013  GPUStaticInst*
11015  {
11016  return new Inst_SOPP__S_CBRANCH_SCC0(&iFmt->iFmt_SOPP);
11017  } // decode_OP_SOPP__S_CBRANCH_SCC0
11018 
11019  GPUStaticInst*
11021  {
11022  return new Inst_SOPP__S_CBRANCH_SCC1(&iFmt->iFmt_SOPP);
11023  } // decode_OP_SOPP__S_CBRANCH_SCC1
11024 
11025  GPUStaticInst*
11027  {
11028  return new Inst_SOPP__S_CBRANCH_VCCZ(&iFmt->iFmt_SOPP);
11029  } // decode_OP_SOPP__S_CBRANCH_VCCZ
11030 
11031  GPUStaticInst*
11033  {
11034  return new Inst_SOPP__S_CBRANCH_VCCNZ(&iFmt->iFmt_SOPP);
11035  } // decode_OP_SOPP__S_CBRANCH_VCCNZ
11036 
11037  GPUStaticInst*
11039  {
11040  return new Inst_SOPP__S_CBRANCH_EXECZ(&iFmt->iFmt_SOPP);
11041  } // decode_OP_SOPP__S_CBRANCH_EXECZ
11042 
11043  GPUStaticInst*
11045  {
11046  return new Inst_SOPP__S_CBRANCH_EXECNZ(&iFmt->iFmt_SOPP);
11047  } // decode_OP_SOPP__S_CBRANCH_EXECNZ
11048 
11049  GPUStaticInst*
11051  {
11052  return new Inst_SOPP__S_BARRIER(&iFmt->iFmt_SOPP);
11053  } // decode_OP_SOPP__S_BARRIER
11054 
11055  GPUStaticInst*
11057  {
11058  return new Inst_SOPP__S_SETKILL(&iFmt->iFmt_SOPP);
11059  } // decode_OP_SOPP__S_SETKILL
11060 
11061  GPUStaticInst*
11063  {
11064  return new Inst_SOPP__S_WAITCNT(&iFmt->iFmt_SOPP);
11065  } // decode_OP_SOPP__S_WAITCNT
11066 
11067  GPUStaticInst*
11069  {
11070  return new Inst_SOPP__S_SETHALT(&iFmt->iFmt_SOPP);
11071  } // decode_OP_SOPP__S_SETHALT
11072 
11073  GPUStaticInst*
11075  {
11076  return new Inst_SOPP__S_SLEEP(&iFmt->iFmt_SOPP);
11077  } // decode_OP_SOPP__S_SLEEP
11078 
11079  GPUStaticInst*
11081  {
11082  return new Inst_SOPP__S_SETPRIO(&iFmt->iFmt_SOPP);
11083  } // decode_OP_SOPP__S_SETPRIO
11084 
11085  GPUStaticInst*
11087  {
11088  return new Inst_SOPP__S_SENDMSG(&iFmt->iFmt_SOPP);
11089  } // decode_OP_SOPP__S_SENDMSG
11090 
11091  GPUStaticInst*
11093  {
11094  return new Inst_SOPP__S_SENDMSGHALT(&iFmt->iFmt_SOPP);
11095  } // decode_OP_SOPP__S_SENDMSGHALT
11096 
11097  GPUStaticInst*
11099  {
11100  return new Inst_SOPP__S_TRAP(&iFmt->iFmt_SOPP);
11101  } // decode_OP_SOPP__S_TRAP
11102 
11103  GPUStaticInst*
11105  {
11106  return new Inst_SOPP__S_ICACHE_INV(&iFmt->iFmt_SOPP);
11107  } // decode_OP_SOPP__S_ICACHE_INV
11108 
11109  GPUStaticInst*
11111  {
11112  return new Inst_SOPP__S_INCPERFLEVEL(&iFmt->iFmt_SOPP);
11113  } // decode_OP_SOPP__S_INCPERFLEVEL
11114 
11115  GPUStaticInst*
11117  {
11118  return new Inst_SOPP__S_DECPERFLEVEL(&iFmt->iFmt_SOPP);
11119  } // decode_OP_SOPP__S_DECPERFLEVEL
11120 
11121  GPUStaticInst*
11123  {
11124  return new Inst_SOPP__S_TTRACEDATA(&iFmt->iFmt_SOPP);
11125  } // decode_OP_SOPP__S_TTRACEDATA
11126 
11127  GPUStaticInst*
11129  {
11130  return new Inst_SOPP__S_CBRANCH_CDBGSYS(&iFmt->iFmt_SOPP);
11131  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS
11132 
11133  GPUStaticInst*
11135  {
11136  return new Inst_SOPP__S_CBRANCH_CDBGUSER(&iFmt->iFmt_SOPP);
11137  } // decode_OP_SOPP__S_CBRANCH_CDBGUSER
11138 
11139  GPUStaticInst*
11141  {
11143  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
11144 
11145  GPUStaticInst*
11147  {
11149  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
11150 
11151  GPUStaticInst*
11153  {
11154  return new Inst_SOPP__S_ENDPGM_SAVED(&iFmt->iFmt_SOPP);
11155  } // decode_OP_SOPP__S_ENDPGM_SAVED
11156 
11157  GPUStaticInst*
11159  {
11160  return new Inst_SOPP__S_SET_GPR_IDX_OFF(&iFmt->iFmt_SOPP);
11161  } // decode_OP_SOPP__S_SET_GPR_IDX_OFF
11162 
11163  GPUStaticInst*
11165  {
11166  return new Inst_SOPP__S_SET_GPR_IDX_MODE(&iFmt->iFmt_SOPP);
11167  } // decode_OP_SOPP__S_SET_GPR_IDX_MODE
11168 
11169  GPUStaticInst*
11171  {
11172  fatal("Trying to decode instruction without a class\n");
11173  return nullptr;
11174  }
11175 
11176  GPUStaticInst*
11178  {
11179  return new Inst_VINTRP__V_INTERP_P1_F32(&iFmt->iFmt_VINTRP);
11180  } // decode_OP_VINTRP__V_INTERP_P1_F32
11181 
11182  GPUStaticInst*
11184  {
11185  return new Inst_VINTRP__V_INTERP_P2_F32(&iFmt->iFmt_VINTRP);
11186  } // decode_OP_VINTRP__V_INTERP_P2_F32
11187 
11188  GPUStaticInst*
11190  {
11191  return new Inst_VINTRP__V_INTERP_MOV_F32(&iFmt->iFmt_VINTRP);
11192  } // decode_OP_VINTRP__V_INTERP_MOV_F32
11193 
11194  GPUStaticInst*
11196  {
11197  return new Inst_VOP1__V_NOP(&iFmt->iFmt_VOP1);
11198  } // decode_OP_VOP1__V_NOP
11199 
11200  GPUStaticInst*
11202  {
11203  return new Inst_VOP1__V_MOV_B32(&iFmt->iFmt_VOP1);
11204  } // decode_OP_VOP1__V_MOV_B32
11205 
11206  GPUStaticInst*
11208  {
11209  return new Inst_VOP1__V_READFIRSTLANE_B32(&iFmt->iFmt_VOP1);
11210  } // decode_OP_VOP1__V_READFIRSTLANE_B32
11211 
11212  GPUStaticInst*
11214  {
11215  return new Inst_VOP1__V_CVT_I32_F64(&iFmt->iFmt_VOP1);
11216  } // decode_OP_VOP1__V_CVT_I32_F64
11217 
11218  GPUStaticInst*
11220  {
11221  return new Inst_VOP1__V_CVT_F64_I32(&iFmt->iFmt_VOP1);
11222  } // decode_OP_VOP1__V_CVT_F64_I32
11223 
11224  GPUStaticInst*
11226  {
11227  return new Inst_VOP1__V_CVT_F32_I32(&iFmt->iFmt_VOP1);
11228  } // decode_OP_VOP1__V_CVT_F32_I32
11229 
11230  GPUStaticInst*
11232  {
11233  return new Inst_VOP1__V_CVT_F32_U32(&iFmt->iFmt_VOP1);
11234  } // decode_OP_VOP1__V_CVT_F32_U32
11235 
11236  GPUStaticInst*
11238  {
11239  return new Inst_VOP1__V_CVT_U32_F32(&iFmt->iFmt_VOP1);
11240  } // decode_OP_VOP1__V_CVT_U32_F32
11241 
11242  GPUStaticInst*
11244  {
11245  return new Inst_VOP1__V_CVT_I32_F32(&iFmt->iFmt_VOP1);
11246  } // decode_OP_VOP1__V_CVT_I32_F32
11247 
11248  GPUStaticInst*
11250  {
11251  return new Inst_VOP1__V_CVT_F16_F32(&iFmt->iFmt_VOP1);
11252  } // decode_OP_VOP1__V_CVT_F16_F32
11253 
11254  GPUStaticInst*
11256  {
11257  return new Inst_VOP1__V_CVT_F32_F16(&iFmt->iFmt_VOP1);
11258  } // decode_OP_VOP1__V_CVT_F32_F16
11259 
11260  GPUStaticInst*
11262  {
11263  return new Inst_VOP1__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP1);
11264  } // decode_OP_VOP1__V_CVT_RPI_I32_F32
11265 
11266  GPUStaticInst*
11268  {
11269  return new Inst_VOP1__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP1);
11270  } // decode_OP_VOP1__V_CVT_FLR_I32_F32
11271 
11272  GPUStaticInst*
11274  {
11275  return new Inst_VOP1__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP1);
11276  } // decode_OP_VOP1__V_CVT_OFF_F32_I4
11277 
11278  GPUStaticInst*
11280  {
11281  return new Inst_VOP1__V_CVT_F32_F64(&iFmt->iFmt_VOP1);
11282  } // decode_OP_VOP1__V_CVT_F32_F64
11283 
11284  GPUStaticInst*
11286  {
11287  return new Inst_VOP1__V_CVT_F64_F32(&iFmt->iFmt_VOP1);
11288  } // decode_OP_VOP1__V_CVT_F64_F32
11289 
11290  GPUStaticInst*
11292  {
11293  return new Inst_VOP1__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP1);
11294  } // decode_OP_VOP1__V_CVT_F32_UBYTE0
11295 
11296  GPUStaticInst*
11298  {
11299  return new Inst_VOP1__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP1);
11300  } // decode_OP_VOP1__V_CVT_F32_UBYTE1
11301 
11302  GPUStaticInst*
11304  {
11305  return new Inst_VOP1__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP1);
11306  } // decode_OP_VOP1__V_CVT_F32_UBYTE2
11307 
11308  GPUStaticInst*
11310  {
11311  return new Inst_VOP1__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP1);
11312  } // decode_OP_VOP1__V_CVT_F32_UBYTE3
11313 
11314  GPUStaticInst*
11316  {
11317  return new Inst_VOP1__V_CVT_U32_F64(&iFmt->iFmt_VOP1);
11318  } // decode_OP_VOP1__V_CVT_U32_F64
11319 
11320  GPUStaticInst*
11322  {
11323  return new Inst_VOP1__V_CVT_F64_U32(&iFmt->iFmt_VOP1);
11324  } // decode_OP_VOP1__V_CVT_F64_U32
11325 
11326  GPUStaticInst*
11328  {
11329  return new Inst_VOP1__V_TRUNC_F64(&iFmt->iFmt_VOP1);
11330  } // decode_OP_VOP1__V_TRUNC_F64
11331 
11332  GPUStaticInst*
11334  {
11335  return new Inst_VOP1__V_CEIL_F64(&iFmt->iFmt_VOP1);
11336  } // decode_OP_VOP1__V_CEIL_F64
11337 
11338  GPUStaticInst*
11340  {
11341  return new Inst_VOP1__V_RNDNE_F64(&iFmt->iFmt_VOP1);
11342  } // decode_OP_VOP1__V_RNDNE_F64
11343 
11344  GPUStaticInst*
11346  {
11347  return new Inst_VOP1__V_FLOOR_F64(&iFmt->iFmt_VOP1);
11348  } // decode_OP_VOP1__V_FLOOR_F64
11349 
11350  GPUStaticInst*
11352  {
11353  return new Inst_VOP1__V_FRACT_F32(&iFmt->iFmt_VOP1);
11354  } // decode_OP_VOP1__V_FRACT_F32
11355 
11356  GPUStaticInst*
11358  {
11359  return new Inst_VOP1__V_TRUNC_F32(&iFmt->iFmt_VOP1);
11360  } // decode_OP_VOP1__V_TRUNC_F32
11361 
11362  GPUStaticInst*
11364  {
11365  return new Inst_VOP1__V_CEIL_F32(&iFmt->iFmt_VOP1);
11366  } // decode_OP_VOP1__V_CEIL_F32
11367 
11368  GPUStaticInst*
11370  {
11371  return new Inst_VOP1__V_RNDNE_F32(&iFmt->iFmt_VOP1);
11372  } // decode_OP_VOP1__V_RNDNE_F32
11373 
11374  GPUStaticInst*
11376  {
11377  return new Inst_VOP1__V_FLOOR_F32(&iFmt->iFmt_VOP1);
11378  } // decode_OP_VOP1__V_FLOOR_F32
11379 
11380  GPUStaticInst*
11382  {
11383  return new Inst_VOP1__V_EXP_F32(&iFmt->iFmt_VOP1);
11384  } // decode_OP_VOP1__V_EXP_F32
11385 
11386  GPUStaticInst*
11388  {
11389  return new Inst_VOP1__V_LOG_F32(&iFmt->iFmt_VOP1);
11390  } // decode_OP_VOP1__V_LOG_F32
11391 
11392  GPUStaticInst*
11394  {
11395  return new Inst_VOP1__V_RCP_F32(&iFmt->iFmt_VOP1);
11396  } // decode_OP_VOP1__V_RCP_F32
11397 
11398  GPUStaticInst*
11400  {
11401  return new Inst_VOP1__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP1);
11402  } // decode_OP_VOP1__V_RCP_IFLAG_F32
11403 
11404  GPUStaticInst*
11406  {
11407  return new Inst_VOP1__V_RSQ_F32(&iFmt->iFmt_VOP1);
11408  } // decode_OP_VOP1__V_RSQ_F32
11409 
11410  GPUStaticInst*
11412  {
11413  return new Inst_VOP1__V_RCP_F64(&iFmt->iFmt_VOP1);
11414  } // decode_OP_VOP1__V_RCP_F64
11415 
11416  GPUStaticInst*
11418  {
11419  return new Inst_VOP1__V_RSQ_F64(&iFmt->iFmt_VOP1);
11420  } // decode_OP_VOP1__V_RSQ_F64
11421 
11422  GPUStaticInst*
11424  {
11425  return new Inst_VOP1__V_SQRT_F32(&iFmt->iFmt_VOP1);
11426  } // decode_OP_VOP1__V_SQRT_F32
11427 
11428  GPUStaticInst*
11430  {
11431  return new Inst_VOP1__V_SQRT_F64(&iFmt->iFmt_VOP1);
11432  } // decode_OP_VOP1__V_SQRT_F64
11433 
11434  GPUStaticInst*
11436  {
11437  return new Inst_VOP1__V_SIN_F32(&iFmt->iFmt_VOP1);
11438  } // decode_OP_VOP1__V_SIN_F32
11439 
11440  GPUStaticInst*
11442  {
11443  return new Inst_VOP1__V_COS_F32(&iFmt->iFmt_VOP1);
11444  } // decode_OP_VOP1__V_COS_F32
11445 
11446  GPUStaticInst*
11448  {
11449  return new Inst_VOP1__V_NOT_B32(&iFmt->iFmt_VOP1);
11450  } // decode_OP_VOP1__V_NOT_B32
11451 
11452  GPUStaticInst*
11454  {
11455  return new Inst_VOP1__V_BFREV_B32(&iFmt->iFmt_VOP1);
11456  } // decode_OP_VOP1__V_BFREV_B32
11457 
11458  GPUStaticInst*
11460  {
11461  return new Inst_VOP1__V_FFBH_U32(&iFmt->iFmt_VOP1);
11462  } // decode_OP_VOP1__V_FFBH_U32
11463 
11464  GPUStaticInst*
11466  {
11467  return new Inst_VOP1__V_FFBL_B32(&iFmt->iFmt_VOP1);
11468  } // decode_OP_VOP1__V_FFBL_B32
11469 
11470  GPUStaticInst*
11472  {
11473  return new Inst_VOP1__V_FFBH_I32(&iFmt->iFmt_VOP1);
11474  } // decode_OP_VOP1__V_FFBH_I32
11475 
11476  GPUStaticInst*
11478  {
11479  return new Inst_VOP1__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP1);
11480  } // decode_OP_VOP1__V_FREXP_EXP_I32_F64
11481 
11482  GPUStaticInst*
11484  {
11485  return new Inst_VOP1__V_FREXP_MANT_F64(&iFmt->iFmt_VOP1);
11486  } // decode_OP_VOP1__V_FREXP_MANT_F64
11487 
11488  GPUStaticInst*
11490  {
11491  return new Inst_VOP1__V_FRACT_F64(&iFmt->iFmt_VOP1);
11492  } // decode_OP_VOP1__V_FRACT_F64
11493 
11494  GPUStaticInst*
11496  {
11497  return new Inst_VOP1__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP1);
11498  } // decode_OP_VOP1__V_FREXP_EXP_I32_F32
11499 
11500  GPUStaticInst*
11502  {
11503  return new Inst_VOP1__V_FREXP_MANT_F32(&iFmt->iFmt_VOP1);
11504  } // decode_OP_VOP1__V_FREXP_MANT_F32
11505 
11506  GPUStaticInst*
11508  {
11509  return new Inst_VOP1__V_CLREXCP(&iFmt->iFmt_VOP1);
11510  } // decode_OP_VOP1__V_CLREXCP
11511 
11512  GPUStaticInst*
11514  {
11515  fatal("Trying to decode instruction without a class\n");
11516  return nullptr;
11517  }
11518 
11519  GPUStaticInst*
11521  {
11522  return new Inst_VOP1__V_CVT_F16_U16(&iFmt->iFmt_VOP1);
11523  } // decode_OP_VOP1__V_CVT_F16_U16
11524 
11525  GPUStaticInst*
11527  {
11528  return new Inst_VOP1__V_CVT_F16_I16(&iFmt->iFmt_VOP1);
11529  } // decode_OP_VOP1__V_CVT_F16_I16
11530 
11531  GPUStaticInst*
11533  {
11534  return new Inst_VOP1__V_CVT_U16_F16(&iFmt->iFmt_VOP1);
11535  } // decode_OP_VOP1__V_CVT_U16_F16
11536 
11537  GPUStaticInst*
11539  {
11540  return new Inst_VOP1__V_CVT_I16_F16(&iFmt->iFmt_VOP1);
11541  } // decode_OP_VOP1__V_CVT_I16_F16
11542 
11543  GPUStaticInst*
11545  {
11546  return new Inst_VOP1__V_RCP_F16(&iFmt->iFmt_VOP1);
11547  } // decode_OP_VOP1__V_RCP_F16
11548 
11549  GPUStaticInst*
11551  {
11552  return new Inst_VOP1__V_SQRT_F16(&iFmt->iFmt_VOP1);
11553  } // decode_OP_VOP1__V_SQRT_F16
11554 
11555  GPUStaticInst*
11557  {
11558  return new Inst_VOP1__V_RSQ_F16(&iFmt->iFmt_VOP1);
11559  } // decode_OP_VOP1__V_RSQ_F16
11560 
11561  GPUStaticInst*
11563  {
11564  return new Inst_VOP1__V_LOG_F16(&iFmt->iFmt_VOP1);
11565  } // decode_OP_VOP1__V_LOG_F16
11566 
11567  GPUStaticInst*
11569  {
11570  return new Inst_VOP1__V_EXP_F16(&iFmt->iFmt_VOP1);
11571  } // decode_OP_VOP1__V_EXP_F16
11572 
11573  GPUStaticInst*
11575  {
11576  return new Inst_VOP1__V_FREXP_MANT_F16(&iFmt->iFmt_VOP1);
11577  } // decode_OP_VOP1__V_FREXP_MANT_F16
11578 
11579  GPUStaticInst*
11581  {
11582  return new Inst_VOP1__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP1);
11583  } // decode_OP_VOP1__V_FREXP_EXP_I16_F16
11584 
11585  GPUStaticInst*
11587  {
11588  return new Inst_VOP1__V_FLOOR_F16(&iFmt->iFmt_VOP1);
11589  } // decode_OP_VOP1__V_FLOOR_F16
11590 
11591  GPUStaticInst*
11593  {
11594  return new Inst_VOP1__V_CEIL_F16(&iFmt->iFmt_VOP1);
11595  } // decode_OP_VOP1__V_CEIL_F16
11596 
11597  GPUStaticInst*
11599  {
11600  return new Inst_VOP1__V_TRUNC_F16(&iFmt->iFmt_VOP1);
11601  } // decode_OP_VOP1__V_TRUNC_F16
11602 
11603  GPUStaticInst*
11605  {
11606  return new Inst_VOP1__V_RNDNE_F16(&iFmt->iFmt_VOP1);
11607  } // decode_OP_VOP1__V_RNDNE_F16
11608 
11609  GPUStaticInst*
11611  {
11612  return new Inst_VOP1__V_FRACT_F16(&iFmt->iFmt_VOP1);
11613  } // decode_OP_VOP1__V_FRACT_F16
11614 
11615  GPUStaticInst*
11617  {
11618  return new Inst_VOP1__V_SIN_F16(&iFmt->iFmt_VOP1);
11619  } // decode_OP_VOP1__V_SIN_F16
11620 
11621  GPUStaticInst*
11623  {
11624  return new Inst_VOP1__V_COS_F16(&iFmt->iFmt_VOP1);
11625  } // decode_OP_VOP1__V_COS_F16
11626 
11627  GPUStaticInst*
11629  {
11630  return new Inst_VOP1__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP1);
11631  } // decode_OP_VOP1__V_EXP_LEGACY_F32
11632 
11633  GPUStaticInst*
11635  {
11636  return new Inst_VOP1__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP1);
11637  } // decode_OP_VOP1__V_LOG_LEGACY_F32
11638 
11639  GPUStaticInst*
11641  {
11642  fatal("Trying to decode instruction without a class\n");
11643  return nullptr;
11644  }
11645 
11646  GPUStaticInst*
11648  {
11649  fatal("Trying to decode instruction without a class\n");
11650  return nullptr;
11651  }
11652 
11653  GPUStaticInst*
11655  {
11656  fatal("Trying to decode instruction without a class\n");
11657  return nullptr;
11658  }
11659 
11660  GPUStaticInst*
11662  {
11663  fatal("Trying to decode instruction without a class\n");
11664  return nullptr;
11665  }
11666 
11667  GPUStaticInst*
11669  {
11670  return new Inst_VOPC__V_CMP_CLASS_F32(&iFmt->iFmt_VOPC);
11671  } // decode_OP_VOPC__V_CMP_CLASS_F32
11672 
11673  GPUStaticInst*
11675  {
11676  return new Inst_VOPC__V_CMPX_CLASS_F32(&iFmt->iFmt_VOPC);
11677  } // decode_OP_VOPC__V_CMPX_CLASS_F32
11678 
11679  GPUStaticInst*
11681  {
11682  return new Inst_VOPC__V_CMP_CLASS_F64(&iFmt->iFmt_VOPC);
11683  } // decode_OP_VOPC__V_CMP_CLASS_F64
11684 
11685  GPUStaticInst*
11687  {
11688  return new Inst_VOPC__V_CMPX_CLASS_F64(&iFmt->iFmt_VOPC);
11689  } // decode_OP_VOPC__V_CMPX_CLASS_F64
11690 
11691  GPUStaticInst*
11693  {
11694  return new Inst_VOPC__V_CMP_CLASS_F16(&iFmt->iFmt_VOPC);
11695  } // decode_OP_VOPC__V_CMP_CLASS_F16
11696 
11697  GPUStaticInst*
11699  {
11700  return new Inst_VOPC__V_CMPX_CLASS_F16(&iFmt->iFmt_VOPC);
11701  } // decode_OP_VOPC__V_CMPX_CLASS_F16
11702 
11703  GPUStaticInst*
11705  {
11706  return new Inst_VOPC__V_CMP_F_F16(&iFmt->iFmt_VOPC);
11707  } // decode_OP_VOPC__V_CMP_F_F16
11708 
11709  GPUStaticInst*
11711  {
11712  return new Inst_VOPC__V_CMP_LT_F16(&iFmt->iFmt_VOPC);
11713  } // decode_OP_VOPC__V_CMP_LT_F16
11714 
11715  GPUStaticInst*
11717  {
11718  return new Inst_VOPC__V_CMP_EQ_F16(&iFmt->iFmt_VOPC);
11719  } // decode_OP_VOPC__V_CMP_EQ_F16
11720 
11721  GPUStaticInst*
11723  {
11724  return new Inst_VOPC__V_CMP_LE_F16(&iFmt->iFmt_VOPC);
11725  } // decode_OP_VOPC__V_CMP_LE_F16
11726 
11727  GPUStaticInst*
11729  {
11730  return new Inst_VOPC__V_CMP_GT_F16(&iFmt->iFmt_VOPC);
11731  } // decode_OP_VOPC__V_CMP_GT_F16
11732 
11733  GPUStaticInst*
11735  {
11736  return new Inst_VOPC__V_CMP_LG_F16(&iFmt->iFmt_VOPC);
11737  } // decode_OP_VOPC__V_CMP_LG_F16
11738 
11739  GPUStaticInst*
11741  {
11742  return new Inst_VOPC__V_CMP_GE_F16(&iFmt->iFmt_VOPC);
11743  } // decode_OP_VOPC__V_CMP_GE_F16
11744 
11745  GPUStaticInst*
11747  {
11748  return new Inst_VOPC__V_CMP_O_F16(&iFmt->iFmt_VOPC);
11749  } // decode_OP_VOPC__V_CMP_O_F16
11750 
11751  GPUStaticInst*
11753  {
11754  return new Inst_VOPC__V_CMP_U_F16(&iFmt->iFmt_VOPC);
11755  } // decode_OP_VOPC__V_CMP_U_F16
11756 
11757  GPUStaticInst*
11759  {
11760  return new Inst_VOPC__V_CMP_NGE_F16(&iFmt->iFmt_VOPC);
11761  } // decode_OP_VOPC__V_CMP_NGE_F16
11762 
11763  GPUStaticInst*
11765  {
11766  return new Inst_VOPC__V_CMP_NLG_F16(&iFmt->iFmt_VOPC);
11767  } // decode_OP_VOPC__V_CMP_NLG_F16
11768 
11769  GPUStaticInst*
11771  {
11772  return new Inst_VOPC__V_CMP_NGT_F16(&iFmt->iFmt_VOPC);
11773  } // decode_OP_VOPC__V_CMP_NGT_F16
11774 
11775  GPUStaticInst*
11777  {
11778  return new Inst_VOPC__V_CMP_NLE_F16(&iFmt->iFmt_VOPC);
11779  } // decode_OP_VOPC__V_CMP_NLE_F16
11780 
11781  GPUStaticInst*
11783  {
11784  return new Inst_VOPC__V_CMP_NEQ_F16(&iFmt->iFmt_VOPC);
11785  } // decode_OP_VOPC__V_CMP_NEQ_F16
11786 
11787  GPUStaticInst*
11789  {
11790  return new Inst_VOPC__V_CMP_NLT_F16(&iFmt->iFmt_VOPC);
11791  } // decode_OP_VOPC__V_CMP_NLT_F16
11792 
11793  GPUStaticInst*
11795  {
11796  return new Inst_VOPC__V_CMP_TRU_F16(&iFmt->iFmt_VOPC);
11797  } // decode_OP_VOPC__V_CMP_TRU_F16
11798 
11799  GPUStaticInst*
11801  {
11802  return new Inst_VOPC__V_CMPX_F_F16(&iFmt->iFmt_VOPC);
11803  } // decode_OP_VOPC__V_CMPX_F_F16
11804 
11805  GPUStaticInst*
11807  {
11808  return new Inst_VOPC__V_CMPX_LT_F16(&iFmt->iFmt_VOPC);
11809  } // decode_OP_VOPC__V_CMPX_LT_F16
11810 
11811  GPUStaticInst*
11813  {
11814  return new Inst_VOPC__V_CMPX_EQ_F16(&iFmt->iFmt_VOPC);
11815  } // decode_OP_VOPC__V_CMPX_EQ_F16
11816 
11817  GPUStaticInst*
11819  {
11820  return new Inst_VOPC__V_CMPX_LE_F16(&iFmt->iFmt_VOPC);
11821  } // decode_OP_VOPC__V_CMPX_LE_F16
11822 
11823  GPUStaticInst*
11825  {
11826  return new Inst_VOPC__V_CMPX_GT_F16(&iFmt->iFmt_VOPC);
11827  } // decode_OP_VOPC__V_CMPX_GT_F16
11828 
11829  GPUStaticInst*
11831  {
11832  return new Inst_VOPC__V_CMPX_LG_F16(&iFmt->iFmt_VOPC);
11833  } // decode_OP_VOPC__V_CMPX_LG_F16
11834 
11835  GPUStaticInst*
11837  {
11838  return new Inst_VOPC__V_CMPX_GE_F16(&iFmt->iFmt_VOPC);
11839  } // decode_OP_VOPC__V_CMPX_GE_F16
11840 
11841  GPUStaticInst*
11843  {
11844  return new Inst_VOPC__V_CMPX_O_F16(&iFmt->iFmt_VOPC);
11845  } // decode_OP_VOPC__V_CMPX_O_F16
11846 
11847  GPUStaticInst*
11849  {
11850  return new Inst_VOPC__V_CMPX_U_F16(&iFmt->iFmt_VOPC);
11851  } // decode_OP_VOPC__V_CMPX_U_F16
11852 
11853  GPUStaticInst*
11855  {
11856  return new Inst_VOPC__V_CMPX_NGE_F16(&iFmt->iFmt_VOPC);
11857  } // decode_OP_VOPC__V_CMPX_NGE_F16
11858 
11859  GPUStaticInst*
11861  {
11862  return new Inst_VOPC__V_CMPX_NLG_F16(&iFmt->iFmt_VOPC);
11863  } // decode_OP_VOPC__V_CMPX_NLG_F16
11864 
11865  GPUStaticInst*
11867  {
11868  return new Inst_VOPC__V_CMPX_NGT_F16(&iFmt->iFmt_VOPC);
11869  } // decode_OP_VOPC__V_CMPX_NGT_F16
11870 
11871  GPUStaticInst*
11873  {
11874  return new Inst_VOPC__V_CMPX_NLE_F16(&iFmt->iFmt_VOPC);
11875  } // decode_OP_VOPC__V_CMPX_NLE_F16
11876 
11877  GPUStaticInst*
11879  {
11880  return new Inst_VOPC__V_CMPX_NEQ_F16(&iFmt->iFmt_VOPC);
11881  } // decode_OP_VOPC__V_CMPX_NEQ_F16
11882 
11883  GPUStaticInst*
11885  {
11886  return new Inst_VOPC__V_CMPX_NLT_F16(&iFmt->iFmt_VOPC);
11887  } // decode_OP_VOPC__V_CMPX_NLT_F16
11888 
11889  GPUStaticInst*
11891  {
11892  return new Inst_VOPC__V_CMPX_TRU_F16(&iFmt->iFmt_VOPC);
11893  } // decode_OP_VOPC__V_CMPX_TRU_F16
11894 
11895  GPUStaticInst*
11897  {
11898  return new Inst_VOPC__V_CMP_F_F32(&iFmt->iFmt_VOPC);
11899  } // decode_OP_VOPC__V_CMP_F_F32
11900 
11901  GPUStaticInst*
11903  {
11904  return new Inst_VOPC__V_CMP_LT_F32(&iFmt->iFmt_VOPC);
11905  } // decode_OP_VOPC__V_CMP_LT_F32
11906 
11907  GPUStaticInst*
11909  {
11910  return new Inst_VOPC__V_CMP_EQ_F32(&iFmt->iFmt_VOPC);
11911  } // decode_OP_VOPC__V_CMP_EQ_F32
11912 
11913  GPUStaticInst*
11915  {
11916  return new Inst_VOPC__V_CMP_LE_F32(&iFmt->iFmt_VOPC);
11917  } // decode_OP_VOPC__V_CMP_LE_F32
11918 
11919  GPUStaticInst*
11921  {
11922  return new Inst_VOPC__V_CMP_GT_F32(&iFmt->iFmt_VOPC);
11923  } // decode_OP_VOPC__V_CMP_GT_F32
11924 
11925  GPUStaticInst*
11927  {
11928  return new Inst_VOPC__V_CMP_LG_F32(&iFmt->iFmt_VOPC);
11929  } // decode_OP_VOPC__V_CMP_LG_F32
11930 
11931  GPUStaticInst*
11933  {
11934  return new Inst_VOPC__V_CMP_GE_F32(&iFmt->iFmt_VOPC);
11935  } // decode_OP_VOPC__V_CMP_GE_F32
11936 
11937  GPUStaticInst*
11939  {
11940  return new Inst_VOPC__V_CMP_O_F32(&iFmt->iFmt_VOPC);
11941  } // decode_OP_VOPC__V_CMP_O_F32
11942 
11943  GPUStaticInst*
11945  {
11946  return new Inst_VOPC__V_CMP_U_F32(&iFmt->iFmt_VOPC);
11947  } // decode_OP_VOPC__V_CMP_U_F32
11948 
11949  GPUStaticInst*
11951  {
11952  return new Inst_VOPC__V_CMP_NGE_F32(&iFmt->iFmt_VOPC);
11953  } // decode_OP_VOPC__V_CMP_NGE_F32
11954 
11955  GPUStaticInst*
11957  {
11958  return new Inst_VOPC__V_CMP_NLG_F32(&iFmt->iFmt_VOPC);
11959  } // decode_OP_VOPC__V_CMP_NLG_F32
11960 
11961  GPUStaticInst*
11963  {
11964  return new Inst_VOPC__V_CMP_NGT_F32(&iFmt->iFmt_VOPC);
11965  } // decode_OP_VOPC__V_CMP_NGT_F32
11966 
11967  GPUStaticInst*
11969  {
11970  return new Inst_VOPC__V_CMP_NLE_F32(&iFmt->iFmt_VOPC);
11971  } // decode_OP_VOPC__V_CMP_NLE_F32
11972 
11973  GPUStaticInst*
11975  {
11976  return new Inst_VOPC__V_CMP_NEQ_F32(&iFmt->iFmt_VOPC);
11977  } // decode_OP_VOPC__V_CMP_NEQ_F32
11978 
11979  GPUStaticInst*
11981  {
11982  return new Inst_VOPC__V_CMP_NLT_F32(&iFmt->iFmt_VOPC);
11983  } // decode_OP_VOPC__V_CMP_NLT_F32
11984 
11985  GPUStaticInst*
11987  {
11988  return new Inst_VOPC__V_CMP_TRU_F32(&iFmt->iFmt_VOPC);
11989  } // decode_OP_VOPC__V_CMP_TRU_F32
11990 
11991  GPUStaticInst*
11993  {
11994  return new Inst_VOPC__V_CMPX_F_F32(&iFmt->iFmt_VOPC);
11995  } // decode_OP_VOPC__V_CMPX_F_F32
11996 
11997  GPUStaticInst*
11999  {
12000  return new Inst_VOPC__V_CMPX_LT_F32(&iFmt->iFmt_VOPC);
12001  } // decode_OP_VOPC__V_CMPX_LT_F32
12002 
12003  GPUStaticInst*
12005  {
12006  return new Inst_VOPC__V_CMPX_EQ_F32(&iFmt->iFmt_VOPC);
12007  } // decode_OP_VOPC__V_CMPX_EQ_F32
12008 
12009  GPUStaticInst*
12011  {
12012  return new Inst_VOPC__V_CMPX_LE_F32(&iFmt->iFmt_VOPC);
12013  } // decode_OP_VOPC__V_CMPX_LE_F32
12014 
12015  GPUStaticInst*
12017  {
12018  return new Inst_VOPC__V_CMPX_GT_F32(&iFmt->iFmt_VOPC);
12019  } // decode_OP_VOPC__V_CMPX_GT_F32
12020 
12021  GPUStaticInst*
12023  {
12024  return new Inst_VOPC__V_CMPX_LG_F32(&iFmt->iFmt_VOPC);
12025  } // decode_OP_VOPC__V_CMPX_LG_F32
12026 
12027  GPUStaticInst*
12029  {
12030  return new Inst_VOPC__V_CMPX_GE_F32(&iFmt->iFmt_VOPC);
12031  } // decode_OP_VOPC__V_CMPX_GE_F32
12032 
12033  GPUStaticInst*
12035  {
12036  return new Inst_VOPC__V_CMPX_O_F32(&iFmt->iFmt_VOPC);
12037  } // decode_OP_VOPC__V_CMPX_O_F32
12038 
12039  GPUStaticInst*
12041  {
12042  return new Inst_VOPC__V_CMPX_U_F32(&iFmt->iFmt_VOPC);
12043  } // decode_OP_VOPC__V_CMPX_U_F32
12044 
12045  GPUStaticInst*
12047  {
12048  return new Inst_VOPC__V_CMPX_NGE_F32(&iFmt->iFmt_VOPC);
12049  } // decode_OP_VOPC__V_CMPX_NGE_F32
12050 
12051  GPUStaticInst*
12053  {
12054  return new Inst_VOPC__V_CMPX_NLG_F32(&iFmt->iFmt_VOPC);
12055  } // decode_OP_VOPC__V_CMPX_NLG_F32
12056 
12057  GPUStaticInst*
12059  {
12060  return new Inst_VOPC__V_CMPX_NGT_F32(&iFmt->iFmt_VOPC);
12061  } // decode_OP_VOPC__V_CMPX_NGT_F32
12062 
12063  GPUStaticInst*
12065  {
12066  return new Inst_VOPC__V_CMPX_NLE_F32(&iFmt->iFmt_VOPC);
12067  } // decode_OP_VOPC__V_CMPX_NLE_F32
12068 
12069  GPUStaticInst*
12071  {
12072  return new Inst_VOPC__V_CMPX_NEQ_F32(&iFmt->iFmt_VOPC);
12073  } // decode_OP_VOPC__V_CMPX_NEQ_F32
12074 
12075  GPUStaticInst*
12077  {
12078  return new Inst_VOPC__V_CMPX_NLT_F32(&iFmt->iFmt_VOPC);
12079  } // decode_OP_VOPC__V_CMPX_NLT_F32
12080 
12081  GPUStaticInst*
12083  {
12084  return new Inst_VOPC__V_CMPX_TRU_F32(&iFmt->iFmt_VOPC);
12085  } // decode_OP_VOPC__V_CMPX_TRU_F32
12086 
12087  GPUStaticInst*
12089  {
12090  return new Inst_VOPC__V_CMP_F_F64(&iFmt->iFmt_VOPC);
12091  } // decode_OP_VOPC__V_CMP_F_F64
12092 
12093  GPUStaticInst*
12095  {
12096  return new Inst_VOPC__V_CMP_LT_F64(&iFmt->iFmt_VOPC);
12097  } // decode_OP_VOPC__V_CMP_LT_F64
12098 
12099  GPUStaticInst*
12101  {
12102  return new Inst_VOPC__V_CMP_EQ_F64(&iFmt->iFmt_VOPC);
12103  } // decode_OP_VOPC__V_CMP_EQ_F64
12104 
12105  GPUStaticInst*
12107  {
12108  return new Inst_VOPC__V_CMP_LE_F64(&iFmt->iFmt_VOPC);
12109  } // decode_OP_VOPC__V_CMP_LE_F64
12110 
12111  GPUStaticInst*
12113  {
12114  return new Inst_VOPC__V_CMP_GT_F64(&iFmt->iFmt_VOPC);
12115  } // decode_OP_VOPC__V_CMP_GT_F64
12116 
12117  GPUStaticInst*
12119  {
12120  return new Inst_VOPC__V_CMP_LG_F64(&iFmt->iFmt_VOPC);
12121  } // decode_OP_VOPC__V_CMP_LG_F64
12122 
12123  GPUStaticInst*
12125  {
12126  return new Inst_VOPC__V_CMP_GE_F64(&iFmt->iFmt_VOPC);
12127  } // decode_OP_VOPC__V_CMP_GE_F64
12128 
12129  GPUStaticInst*
12131  {
12132  return new Inst_VOPC__V_CMP_O_F64(&iFmt->iFmt_VOPC);
12133  } // decode_OP_VOPC__V_CMP_O_F64
12134 
12135  GPUStaticInst*
12137  {
12138  return new Inst_VOPC__V_CMP_U_F64(&iFmt->iFmt_VOPC);
12139  } // decode_OP_VOPC__V_CMP_U_F64
12140 
12141  GPUStaticInst*
12143  {
12144  return new Inst_VOPC__V_CMP_NGE_F64(&iFmt->iFmt_VOPC);
12145  } // decode_OP_VOPC__V_CMP_NGE_F64
12146 
12147  GPUStaticInst*
12149  {
12150  return new Inst_VOPC__V_CMP_NLG_F64(&iFmt->iFmt_VOPC);
12151  } // decode_OP_VOPC__V_CMP_NLG_F64
12152 
12153  GPUStaticInst*
12155  {
12156  return new Inst_VOPC__V_CMP_NGT_F64(&iFmt->iFmt_VOPC);
12157  } // decode_OP_VOPC__V_CMP_NGT_F64
12158 
12159  GPUStaticInst*
12161  {
12162  return new Inst_VOPC__V_CMP_NLE_F64(&iFmt->iFmt_VOPC);
12163  } // decode_OP_VOPC__V_CMP_NLE_F64
12164 
12165  GPUStaticInst*
12167  {
12168  return new Inst_VOPC__V_CMP_NEQ_F64(&iFmt->iFmt_VOPC);
12169  } // decode_OP_VOPC__V_CMP_NEQ_F64
12170 
12171  GPUStaticInst*
12173  {
12174  return new Inst_VOPC__V_CMP_NLT_F64(&iFmt->iFmt_VOPC);
12175  } // decode_OP_VOPC__V_CMP_NLT_F64
12176 
12177  GPUStaticInst*
12179  {
12180  return new Inst_VOPC__V_CMP_TRU_F64(&iFmt->iFmt_VOPC);
12181  } // decode_OP_VOPC__V_CMP_TRU_F64
12182 
12183  GPUStaticInst*
12185  {
12186  return new Inst_VOPC__V_CMPX_F_F64(&iFmt->iFmt_VOPC);
12187  } // decode_OP_VOPC__V_CMPX_F_F64
12188 
12189  GPUStaticInst*
12191  {
12192  return new Inst_VOPC__V_CMPX_LT_F64(&iFmt->iFmt_VOPC);
12193  } // decode_OP_VOPC__V_CMPX_LT_F64
12194 
12195  GPUStaticInst*
12197  {
12198  return new Inst_VOPC__V_CMPX_EQ_F64(&iFmt->iFmt_VOPC);
12199  } // decode_OP_VOPC__V_CMPX_EQ_F64
12200 
12201  GPUStaticInst*
12203  {
12204  return new Inst_VOPC__V_CMPX_LE_F64(&iFmt->iFmt_VOPC);
12205  } // decode_OP_VOPC__V_CMPX_LE_F64
12206 
12207  GPUStaticInst*
12209  {
12210  return new Inst_VOPC__V_CMPX_GT_F64(&iFmt->iFmt_VOPC);
12211  } // decode_OP_VOPC__V_CMPX_GT_F64
12212 
12213  GPUStaticInst*
12215  {
12216  return new Inst_VOPC__V_CMPX_LG_F64(&iFmt->iFmt_VOPC);
12217  } // decode_OP_VOPC__V_CMPX_LG_F64
12218 
12219  GPUStaticInst*
12221  {
12222  return new Inst_VOPC__V_CMPX_GE_F64(&iFmt->iFmt_VOPC);
12223  } // decode_OP_VOPC__V_CMPX_GE_F64
12224 
12225  GPUStaticInst*
12227  {
12228  return new Inst_VOPC__V_CMPX_O_F64(&iFmt->iFmt_VOPC);
12229  } // decode_OP_VOPC__V_CMPX_O_F64
12230 
12231  GPUStaticInst*
12233  {
12234  return new Inst_VOPC__V_CMPX_U_F64(&iFmt->iFmt_VOPC);
12235  } // decode_OP_VOPC__V_CMPX_U_F64
12236 
12237  GPUStaticInst*
12239  {
12240  return new Inst_VOPC__V_CMPX_NGE_F64(&iFmt->iFmt_VOPC);
12241  } // decode_OP_VOPC__V_CMPX_NGE_F64
12242 
12243  GPUStaticInst*
12245  {
12246  return new Inst_VOPC__V_CMPX_NLG_F64(&iFmt->iFmt_VOPC);
12247  } // decode_OP_VOPC__V_CMPX_NLG_F64
12248 
12249  GPUStaticInst*
12251  {
12252  return new Inst_VOPC__V_CMPX_NGT_F64(&iFmt->iFmt_VOPC);
12253  } // decode_OP_VOPC__V_CMPX_NGT_F64
12254 
12255  GPUStaticInst*
12257  {
12258  return new Inst_VOPC__V_CMPX_NLE_F64(&iFmt->iFmt_VOPC);
12259  } // decode_OP_VOPC__V_CMPX_NLE_F64
12260 
12261  GPUStaticInst*
12263  {
12264  return new Inst_VOPC__V_CMPX_NEQ_F64(&iFmt->iFmt_VOPC);
12265  } // decode_OP_VOPC__V_CMPX_NEQ_F64
12266 
12267  GPUStaticInst*
12269  {
12270  return new Inst_VOPC__V_CMPX_NLT_F64(&iFmt->iFmt_VOPC);
12271  } // decode_OP_VOPC__V_CMPX_NLT_F64
12272 
12273  GPUStaticInst*
12275  {
12276  return new Inst_VOPC__V_CMPX_TRU_F64(&iFmt->iFmt_VOPC);
12277  } // decode_OP_VOPC__V_CMPX_TRU_F64
12278 
12279  GPUStaticInst*
12281  {
12282  return new Inst_VOPC__V_CMP_F_I16(&iFmt->iFmt_VOPC);
12283  } // decode_OP_VOPC__V_CMP_F_I16
12284 
12285  GPUStaticInst*
12287  {
12288  return new Inst_VOPC__V_CMP_LT_I16(&iFmt->iFmt_VOPC);
12289  } // decode_OP_VOPC__V_CMP_LT_I16
12290 
12291  GPUStaticInst*
12293  {
12294  return new Inst_VOPC__V_CMP_EQ_I16(&iFmt->iFmt_VOPC);
12295  } // decode_OP_VOPC__V_CMP_EQ_I16
12296 
12297  GPUStaticInst*
12299  {
12300  return new Inst_VOPC__V_CMP_LE_I16(&iFmt->iFmt_VOPC);
12301  } // decode_OP_VOPC__V_CMP_LE_I16
12302 
12303  GPUStaticInst*
12305  {
12306  return new Inst_VOPC__V_CMP_GT_I16(&iFmt->iFmt_VOPC);
12307  } // decode_OP_VOPC__V_CMP_GT_I16
12308 
12309  GPUStaticInst*
12311  {
12312  return new Inst_VOPC__V_CMP_NE_I16(&iFmt->iFmt_VOPC);
12313  } // decode_OP_VOPC__V_CMP_NE_I16
12314 
12315  GPUStaticInst*
12317  {
12318  return new Inst_VOPC__V_CMP_GE_I16(&iFmt->iFmt_VOPC);
12319  } // decode_OP_VOPC__V_CMP_GE_I16
12320 
12321  GPUStaticInst*
12323  {
12324  return new Inst_VOPC__V_CMP_T_I16(&iFmt->iFmt_VOPC);
12325  } // decode_OP_VOPC__V_CMP_T_I16
12326 
12327  GPUStaticInst*
12329  {
12330  return new Inst_VOPC__V_CMP_F_U16(&iFmt->iFmt_VOPC);
12331  } // decode_OP_VOPC__V_CMP_F_U16
12332 
12333  GPUStaticInst*
12335  {
12336  return new Inst_VOPC__V_CMP_LT_U16(&iFmt->iFmt_VOPC);
12337  } // decode_OP_VOPC__V_CMP_LT_U16
12338 
12339  GPUStaticInst*
12341  {
12342  return new Inst_VOPC__V_CMP_EQ_U16(&iFmt->iFmt_VOPC);
12343  } // decode_OP_VOPC__V_CMP_EQ_U16
12344 
12345  GPUStaticInst*
12347  {
12348  return new Inst_VOPC__V_CMP_LE_U16(&iFmt->iFmt_VOPC);
12349  } // decode_OP_VOPC__V_CMP_LE_U16
12350 
12351  GPUStaticInst*
12353  {
12354  return new Inst_VOPC__V_CMP_GT_U16(&iFmt->iFmt_VOPC);
12355  } // decode_OP_VOPC__V_CMP_GT_U16
12356 
12357  GPUStaticInst*
12359  {
12360  return new Inst_VOPC__V_CMP_NE_U16(&iFmt->iFmt_VOPC);
12361  } // decode_OP_VOPC__V_CMP_NE_U16
12362 
12363  GPUStaticInst*
12365  {
12366  return new Inst_VOPC__V_CMP_GE_U16(&iFmt->iFmt_VOPC);
12367  } // decode_OP_VOPC__V_CMP_GE_U16
12368 
12369  GPUStaticInst*
12371  {
12372  return new Inst_VOPC__V_CMP_T_U16(&iFmt->iFmt_VOPC);
12373  } // decode_OP_VOPC__V_CMP_T_U16
12374 
12375  GPUStaticInst*
12377  {
12378  return new Inst_VOPC__V_CMPX_F_I16(&iFmt->iFmt_VOPC);
12379  } // decode_OP_VOPC__V_CMPX_F_I16
12380 
12381  GPUStaticInst*
12383  {
12384  return new Inst_VOPC__V_CMPX_LT_I16(&iFmt->iFmt_VOPC);
12385  } // decode_OP_VOPC__V_CMPX_LT_I16
12386 
12387  GPUStaticInst*
12389  {
12390  return new Inst_VOPC__V_CMPX_EQ_I16(&iFmt->iFmt_VOPC);
12391  } // decode_OP_VOPC__V_CMPX_EQ_I16
12392 
12393  GPUStaticInst*
12395  {
12396  return new Inst_VOPC__V_CMPX_LE_I16(&iFmt->iFmt_VOPC);
12397  } // decode_OP_VOPC__V_CMPX_LE_I16
12398 
12399  GPUStaticInst*
12401  {
12402  return new Inst_VOPC__V_CMPX_GT_I16(&iFmt->iFmt_VOPC);
12403  } // decode_OP_VOPC__V_CMPX_GT_I16
12404 
12405  GPUStaticInst*
12407  {
12408  return new Inst_VOPC__V_CMPX_NE_I16(&iFmt->iFmt_VOPC);
12409  } // decode_OP_VOPC__V_CMPX_NE_I16
12410 
12411  GPUStaticInst*
12413  {
12414  return new Inst_VOPC__V_CMPX_GE_I16(&iFmt->iFmt_VOPC);
12415  } // decode_OP_VOPC__V_CMPX_GE_I16
12416 
12417  GPUStaticInst*
12419  {
12420  return new Inst_VOPC__V_CMPX_T_I16(&iFmt->iFmt_VOPC);
12421  } // decode_OP_VOPC__V_CMPX_T_I16
12422 
12423  GPUStaticInst*
12425  {
12426  return new Inst_VOPC__V_CMPX_F_U16(&iFmt->iFmt_VOPC);
12427  } // decode_OP_VOPC__V_CMPX_F_U16
12428 
12429  GPUStaticInst*
12431  {
12432  return new Inst_VOPC__V_CMPX_LT_U16(&iFmt->iFmt_VOPC);
12433  } // decode_OP_VOPC__V_CMPX_LT_U16
12434 
12435  GPUStaticInst*
12437  {
12438  return new Inst_VOPC__V_CMPX_EQ_U16(&iFmt->iFmt_VOPC);
12439  } // decode_OP_VOPC__V_CMPX_EQ_U16
12440 
12441  GPUStaticInst*
12443  {
12444  return new Inst_VOPC__V_CMPX_LE_U16(&iFmt->iFmt_VOPC);
12445  } // decode_OP_VOPC__V_CMPX_LE_U16
12446 
12447  GPUStaticInst*
12449  {
12450  return new Inst_VOPC__V_CMPX_GT_U16(&iFmt->iFmt_VOPC);
12451  } // decode_OP_VOPC__V_CMPX_GT_U16
12452 
12453  GPUStaticInst*
12455  {
12456  return new Inst_VOPC__V_CMPX_NE_U16(&iFmt->iFmt_VOPC);
12457  } // decode_OP_VOPC__V_CMPX_NE_U16
12458 
12459  GPUStaticInst*
12461  {
12462  return new Inst_VOPC__V_CMPX_GE_U16(&iFmt->iFmt_VOPC);
12463  } // decode_OP_VOPC__V_CMPX_GE_U16
12464 
12465  GPUStaticInst*
12467  {
12468  return new Inst_VOPC__V_CMPX_T_U16(&iFmt->iFmt_VOPC);
12469  } // decode_OP_VOPC__V_CMPX_T_U16
12470 
12471  GPUStaticInst*
12473  {
12474  return new Inst_VOPC__V_CMP_F_I32(&iFmt->iFmt_VOPC);
12475  } // decode_OP_VOPC__V_CMP_F_I32
12476 
12477  GPUStaticInst*
12479  {
12480  return new Inst_VOPC__V_CMP_LT_I32(&iFmt->iFmt_VOPC);
12481  } // decode_OP_VOPC__V_CMP_LT_I32
12482 
12483  GPUStaticInst*
12485  {
12486  return new Inst_VOPC__V_CMP_EQ_I32(&iFmt->iFmt_VOPC);
12487  } // decode_OP_VOPC__V_CMP_EQ_I32
12488 
12489  GPUStaticInst*
12491  {
12492  return new Inst_VOPC__V_CMP_LE_I32(&iFmt->iFmt_VOPC);
12493  } // decode_OP_VOPC__V_CMP_LE_I32
12494 
12495  GPUStaticInst*
12497  {
12498  return new Inst_VOPC__V_CMP_GT_I32(&iFmt->iFmt_VOPC);
12499  } // decode_OP_VOPC__V_CMP_GT_I32
12500 
12501  GPUStaticInst*
12503  {
12504  return new Inst_VOPC__V_CMP_NE_I32(&iFmt->iFmt_VOPC);
12505  } // decode_OP_VOPC__V_CMP_NE_I32
12506 
12507  GPUStaticInst*
12509  {
12510  return new Inst_VOPC__V_CMP_GE_I32(&iFmt->iFmt_VOPC);
12511  } // decode_OP_VOPC__V_CMP_GE_I32
12512 
12513  GPUStaticInst*
12515  {
12516  return new Inst_VOPC__V_CMP_T_I32(&iFmt->iFmt_VOPC);
12517  } // decode_OP_VOPC__V_CMP_T_I32
12518 
12519  GPUStaticInst*
12521  {
12522  return new Inst_VOPC__V_CMP_F_U32(&iFmt->iFmt_VOPC);
12523  } // decode_OP_VOPC__V_CMP_F_U32
12524 
12525  GPUStaticInst*
12527  {
12528  return new Inst_VOPC__V_CMP_LT_U32(&iFmt->iFmt_VOPC);
12529  } // decode_OP_VOPC__V_CMP_LT_U32
12530 
12531  GPUStaticInst*
12533  {
12534  return new Inst_VOPC__V_CMP_EQ_U32(&iFmt->iFmt_VOPC);
12535  } // decode_OP_VOPC__V_CMP_EQ_U32
12536 
12537  GPUStaticInst*
12539  {
12540  return new Inst_VOPC__V_CMP_LE_U32(&iFmt->iFmt_VOPC);
12541  } // decode_OP_VOPC__V_CMP_LE_U32
12542 
12543  GPUStaticInst*
12545  {
12546  return new Inst_VOPC__V_CMP_GT_U32(&iFmt->iFmt_VOPC);
12547  } // decode_OP_VOPC__V_CMP_GT_U32
12548 
12549  GPUStaticInst*
12551  {
12552  return new Inst_VOPC__V_CMP_NE_U32(&iFmt->iFmt_VOPC);
12553  } // decode_OP_VOPC__V_CMP_NE_U32
12554 
12555  GPUStaticInst*
12557  {
12558  return new Inst_VOPC__V_CMP_GE_U32(&iFmt->iFmt_VOPC);
12559  } // decode_OP_VOPC__V_CMP_GE_U32
12560 
12561  GPUStaticInst*
12563  {
12564  return new Inst_VOPC__V_CMP_T_U32(&iFmt->iFmt_VOPC);
12565  } // decode_OP_VOPC__V_CMP_T_U32
12566 
12567  GPUStaticInst*
12569  {
12570  return new Inst_VOPC__V_CMPX_F_I32(&iFmt->iFmt_VOPC);
12571  } // decode_OP_VOPC__V_CMPX_F_I32
12572 
12573  GPUStaticInst*
12575  {
12576  return new Inst_VOPC__V_CMPX_LT_I32(&iFmt->iFmt_VOPC);
12577  } // decode_OP_VOPC__V_CMPX_LT_I32
12578 
12579  GPUStaticInst*
12581  {
12582  return new Inst_VOPC__V_CMPX_EQ_I32(&iFmt->iFmt_VOPC);
12583  } // decode_OP_VOPC__V_CMPX_EQ_I32
12584 
12585  GPUStaticInst*
12587  {
12588  return new Inst_VOPC__V_CMPX_LE_I32(&iFmt->iFmt_VOPC);
12589  } // decode_OP_VOPC__V_CMPX_LE_I32
12590 
12591  GPUStaticInst*
12593  {
12594  return new Inst_VOPC__V_CMPX_GT_I32(&iFmt->iFmt_VOPC);
12595  } // decode_OP_VOPC__V_CMPX_GT_I32
12596 
12597  GPUStaticInst*
12599  {
12600  return new Inst_VOPC__V_CMPX_NE_I32(&iFmt->iFmt_VOPC);
12601  } // decode_OP_VOPC__V_CMPX_NE_I32
12602 
12603  GPUStaticInst*
12605  {
12606  return new Inst_VOPC__V_CMPX_GE_I32(&iFmt->iFmt_VOPC);
12607  } // decode_OP_VOPC__V_CMPX_GE_I32
12608 
12609  GPUStaticInst*
12611  {
12612  return new Inst_VOPC__V_CMPX_T_I32(&iFmt->iFmt_VOPC);
12613  } // decode_OP_VOPC__V_CMPX_T_I32
12614 
12615  GPUStaticInst*
12617  {
12618  return new Inst_VOPC__V_CMPX_F_U32(&iFmt->iFmt_VOPC);
12619  } // decode_OP_VOPC__V_CMPX_F_U32
12620 
12621  GPUStaticInst*
12623  {
12624  return new Inst_VOPC__V_CMPX_LT_U32(&iFmt->iFmt_VOPC);
12625  } // decode_OP_VOPC__V_CMPX_LT_U32
12626 
12627  GPUStaticInst*
12629  {
12630  return new Inst_VOPC__V_CMPX_EQ_U32(&iFmt->iFmt_VOPC);
12631  } // decode_OP_VOPC__V_CMPX_EQ_U32
12632 
12633  GPUStaticInst*
12635  {
12636  return new Inst_VOPC__V_CMPX_LE_U32(&iFmt->iFmt_VOPC);
12637  } // decode_OP_VOPC__V_CMPX_LE_U32
12638 
12639  GPUStaticInst*
12641  {
12642  return new Inst_VOPC__V_CMPX_GT_U32(&iFmt->iFmt_VOPC);
12643  } // decode_OP_VOPC__V_CMPX_GT_U32
12644 
12645  GPUStaticInst*
12647  {
12648  return new Inst_VOPC__V_CMPX_NE_U32(&iFmt->iFmt_VOPC);
12649  } // decode_OP_VOPC__V_CMPX_NE_U32
12650 
12651  GPUStaticInst*
12653  {
12654  return new Inst_VOPC__V_CMPX_GE_U32(&iFmt->iFmt_VOPC);
12655  } // decode_OP_VOPC__V_CMPX_GE_U32
12656 
12657  GPUStaticInst*
12659  {
12660  return new Inst_VOPC__V_CMPX_T_U32(&iFmt->iFmt_VOPC);
12661  } // decode_OP_VOPC__V_CMPX_T_U32
12662 
12663  GPUStaticInst*
12665  {
12666  return new Inst_VOPC__V_CMP_F_I64(&iFmt->iFmt_VOPC);
12667  } // decode_OP_VOPC__V_CMP_F_I64
12668 
12669  GPUStaticInst*
12671  {
12672  return new Inst_VOPC__V_CMP_LT_I64(&iFmt->iFmt_VOPC);
12673  } // decode_OP_VOPC__V_CMP_LT_I64
12674 
12675  GPUStaticInst*
12677  {
12678  return new Inst_VOPC__V_CMP_EQ_I64(&iFmt->iFmt_VOPC);
12679  } // decode_OP_VOPC__V_CMP_EQ_I64
12680 
12681  GPUStaticInst*
12683  {
12684  return new Inst_VOPC__V_CMP_LE_I64(&iFmt->iFmt_VOPC);
12685  } // decode_OP_VOPC__V_CMP_LE_I64
12686 
12687  GPUStaticInst*
12689  {
12690  return new Inst_VOPC__V_CMP_GT_I64(&iFmt->iFmt_VOPC);
12691  } // decode_OP_VOPC__V_CMP_GT_I64
12692 
12693  GPUStaticInst*
12695  {
12696  return new Inst_VOPC__V_CMP_NE_I64(&iFmt->iFmt_VOPC);
12697  } // decode_OP_VOPC__V_CMP_NE_I64
12698 
12699  GPUStaticInst*
12701  {
12702  return new Inst_VOPC__V_CMP_GE_I64(&iFmt->iFmt_VOPC);
12703  } // decode_OP_VOPC__V_CMP_GE_I64
12704 
12705  GPUStaticInst*
12707  {
12708  return new Inst_VOPC__V_CMP_T_I64(&iFmt->iFmt_VOPC);
12709  } // decode_OP_VOPC__V_CMP_T_I64
12710 
12711  GPUStaticInst*
12713  {
12714  return new Inst_VOPC__V_CMP_F_U64(&iFmt->iFmt_VOPC);
12715  } // decode_OP_VOPC__V_CMP_F_U64
12716 
12717  GPUStaticInst*
12719  {
12720  return new Inst_VOPC__V_CMP_LT_U64(&iFmt->iFmt_VOPC);
12721  } // decode_OP_VOPC__V_CMP_LT_U64
12722 
12723  GPUStaticInst*
12725  {
12726  return new Inst_VOPC__V_CMP_EQ_U64(&iFmt->iFmt_VOPC);
12727  } // decode_OP_VOPC__V_CMP_EQ_U64
12728 
12729  GPUStaticInst*
12731  {
12732  return new Inst_VOPC__V_CMP_LE_U64(&iFmt->iFmt_VOPC);
12733  } // decode_OP_VOPC__V_CMP_LE_U64
12734 
12735  GPUStaticInst*
12737  {
12738  return new Inst_VOPC__V_CMP_GT_U64(&iFmt->iFmt_VOPC);
12739  } // decode_OP_VOPC__V_CMP_GT_U64
12740 
12741  GPUStaticInst*
12743  {
12744  return new Inst_VOPC__V_CMP_NE_U64(&iFmt->iFmt_VOPC);
12745  } // decode_OP_VOPC__V_CMP_NE_U64
12746 
12747  GPUStaticInst*
12749  {
12750  return new Inst_VOPC__V_CMP_GE_U64(&iFmt->iFmt_VOPC);
12751  } // decode_OP_VOPC__V_CMP_GE_U64
12752 
12753  GPUStaticInst*
12755  {
12756  return new Inst_VOPC__V_CMP_T_U64(&iFmt->iFmt_VOPC);
12757  } // decode_OP_VOPC__V_CMP_T_U64
12758 
12759  GPUStaticInst*
12761  {
12762  return new Inst_VOPC__V_CMPX_F_I64(&iFmt->iFmt_VOPC);
12763  } // decode_OP_VOPC__V_CMPX_F_I64
12764 
12765  GPUStaticInst*
12767  {
12768  return new Inst_VOPC__V_CMPX_LT_I64(&iFmt->iFmt_VOPC);
12769  } // decode_OP_VOPC__V_CMPX_LT_I64
12770 
12771  GPUStaticInst*
12773  {
12774  return new Inst_VOPC__V_CMPX_EQ_I64(&iFmt->iFmt_VOPC);
12775  } // decode_OP_VOPC__V_CMPX_EQ_I64
12776 
12777  GPUStaticInst*
12779  {
12780  return new Inst_VOPC__V_CMPX_LE_I64(&iFmt->iFmt_VOPC);
12781  } // decode_OP_VOPC__V_CMPX_LE_I64
12782 
12783  GPUStaticInst*
12785  {
12786  return new Inst_VOPC__V_CMPX_GT_I64(&iFmt->iFmt_VOPC);
12787  } // decode_OP_VOPC__V_CMPX_GT_I64
12788 
12789  GPUStaticInst*
12791  {
12792  return new Inst_VOPC__V_CMPX_NE_I64(&iFmt->iFmt_VOPC);
12793  } // decode_OP_VOPC__V_CMPX_NE_I64
12794 
12795  GPUStaticInst*
12797  {
12798  return new Inst_VOPC__V_CMPX_GE_I64(&iFmt->iFmt_VOPC);
12799  } // decode_OP_VOPC__V_CMPX_GE_I64
12800 
12801  GPUStaticInst*
12803  {
12804  return new Inst_VOPC__V_CMPX_T_I64(&iFmt->iFmt_VOPC);
12805  } // decode_OP_VOPC__V_CMPX_T_I64
12806 
12807  GPUStaticInst*
12809  {
12810  return new Inst_VOPC__V_CMPX_F_U64(&iFmt->iFmt_VOPC);
12811  } // decode_OP_VOPC__V_CMPX_F_U64
12812 
12813  GPUStaticInst*
12815  {
12816  return new Inst_VOPC__V_CMPX_LT_U64(&iFmt->iFmt_VOPC);
12817  } // decode_OP_VOPC__V_CMPX_LT_U64
12818 
12819  GPUStaticInst*
12821  {
12822  return new Inst_VOPC__V_CMPX_EQ_U64(&iFmt->iFmt_VOPC);
12823  } // decode_OP_VOPC__V_CMPX_EQ_U64
12824 
12825  GPUStaticInst*
12827  {
12828  return new Inst_VOPC__V_CMPX_LE_U64(&iFmt->iFmt_VOPC);
12829  } // decode_OP_VOPC__V_CMPX_LE_U64
12830 
12831  GPUStaticInst*
12833  {
12834  return new Inst_VOPC__V_CMPX_GT_U64(&iFmt->iFmt_VOPC);
12835  } // decode_OP_VOPC__V_CMPX_GT_U64
12836 
12837  GPUStaticInst*
12839  {
12840  return new Inst_VOPC__V_CMPX_NE_U64(&iFmt->iFmt_VOPC);
12841  } // decode_OP_VOPC__V_CMPX_NE_U64
12842 
12843  GPUStaticInst*
12845  {
12846  return new Inst_VOPC__V_CMPX_GE_U64(&iFmt->iFmt_VOPC);
12847  } // decode_OP_VOPC__V_CMPX_GE_U64
12848 
12849  GPUStaticInst*
12851  {
12852  return new Inst_VOPC__V_CMPX_T_U64(&iFmt->iFmt_VOPC);
12853  } // decode_OP_VOPC__V_CMPX_T_U64
12854 
12855  GPUStaticInst*
12857  {
12858  fatal("Trying to decode instruction without a class\n");
12859  return nullptr;
12860  }
12861 
12862  GPUStaticInst*
12864  {
12865  fatal("Trying to decode instruction without a class\n");
12866  return nullptr;
12867  }
12868 
12869  GPUStaticInst*
12871  {
12872  fatal("Trying to decode instruction without a class\n");
12873  return nullptr;
12874  }
12875 
12876  GPUStaticInst*
12878  {
12879  fatal("Trying to decode instruction without a class\n");
12880  return nullptr;
12881  }
12882 
12883  GPUStaticInst*
12885  {
12886  fatal("Trying to decode instruction without a class\n");
12887  return nullptr;
12888  }
12889 
12890  GPUStaticInst*
12892  {
12893  fatal("Trying to decode instruction without a class\n");
12894  return nullptr;
12895  }
12896 
12897  GPUStaticInst*
12899  {
12900  fatal("Trying to decode instruction without a class\n");
12901  return nullptr;
12902  }
12903 
12904  GPUStaticInst*
12906  {
12907  fatal("Trying to decode instruction without a class\n");
12908  return nullptr;
12909  }
12910 
12911  GPUStaticInst*
12913  {
12914  fatal("Trying to decode instruction without a class\n");
12915  return nullptr;
12916  }
12917 
12918  GPUStaticInst*
12920  {
12921  fatal("Trying to decode instruction without a class\n");
12922  return nullptr;
12923  }
12924 
12925  GPUStaticInst*
12927  {
12928  fatal("Trying to decode instruction without a class\n");
12929  return nullptr;
12930  }
12931 
12932  GPUStaticInst*
12934  {
12935  fatal("Trying to decode instruction without a class\n");
12936  return nullptr;
12937  }
12938 
12939  GPUStaticInst*
12941  {
12942  fatal("Trying to decode instruction without a class\n");
12943  return nullptr;
12944  }
12945 
12946  GPUStaticInst*
12948  {
12949  fatal("Trying to decode instruction without a class\n");
12950  return nullptr;
12951  }
12952 
12953  GPUStaticInst*
12955  {
12956  fatal("Trying to decode instruction without a class\n");
12957  return nullptr;
12958  }
12959 
12960  GPUStaticInst*
12962  {
12963  fatal("Trying to decode instruction without a class\n");
12964  return nullptr;
12965  }
12966 
12967  GPUStaticInst*
12969  {
12970  fatal("Trying to decode instruction without a class\n");
12971  return nullptr;
12972  }
12973 
12974  GPUStaticInst*
12976  {
12977  fatal("Trying to decode instruction without a class\n");
12978  return nullptr;
12979  }
12980 
12981  GPUStaticInst*
12983  {
12984  fatal("Trying to decode instruction without a class\n");
12985  return nullptr;
12986  }
12987 
12988  GPUStaticInst*
12990  {
12991  fatal("Trying to decode instruction without a class\n");
12992  return nullptr;
12993  }
12994 
12995  GPUStaticInst*
12997  {
12998  fatal("Trying to decode instruction without a class\n");
12999  return nullptr;
13000  }
13001 
13002  GPUStaticInst*
13004  {
13005  fatal("Trying to decode instruction without a class\n");
13006  return nullptr;
13007  }
13008 
13009  GPUStaticInst*
13011  {
13012  fatal("Invalid opcode encountered: %#x\n", iFmt->imm_u32);
13013 
13014  return nullptr;
13015  }
13016 } // namespace VegaISA
13017 } // namespace gem5
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8247
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:11758
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F16
GPUStaticInst * decode_OPU_VOP3__V_MUL_F16(MachInst)
Definition: decoder.cc:6013
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:42767
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16(MachInst)
Definition: decoder.cc:7704
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst)
Definition: decoder.cc:7830
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64
Definition: instructions.hh:16785
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8391
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8379
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSGHALT
GPUStaticInst * decode_OP_SOPP__S_SENDMSGHALT(MachInst)
Definition: decoder.cc:11092
gem5::VegaISA::Inst_SOP2__S_ADD_U32
Definition: instructions.hh:45
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_I32(MachInst)
Definition: decoder.cc:10900
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:5185
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F16
GPUStaticInst * decode_OPU_VOP3__V_LOG_F16(MachInst)
Definition: decoder.cc:6469
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC1
Definition: instructions.hh:4637
gem5::VegaISA::Inst_VOP3__V_ADD_F64
Definition: instructions.hh:30231
gem5::VegaISA::Decoder::tableSubDecode_OP_MIMG
static IsaDecodeMethod tableSubDecode_OP_MIMG[128]
Definition: gpu_decoder.hh:66
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_LOD
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_LOD(MachInst)
Definition: decoder.cc:9255
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:5371
gem5::VegaISA::Inst_VOP1__V_RNDNE_F64
Definition: instructions.hh:8897
gem5::VegaISA::Inst_VOP1__V_CLREXCP
Definition: instructions.hh:9793
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:5467
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B64
GPUStaticInst * decode_OP_SOP2__S_BFM_B64(MachInst)
Definition: decoder.cc:4385
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:12196
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_B32(MachInst)
Definition: decoder.cc:4608
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32
Definition: instructions.hh:18757
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:5731
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:12508
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:12034
gem5::VegaISA::Inst_VOP3__V_MED3_I32
Definition: instructions.hh:28871
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64
Definition: instructions.hh:16513
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_P
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_P(MachInst)
Definition: decoder.cc:8010
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F16
Definition: instructions.hh:11277
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32
Definition: instructions.hh:12467
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D
Definition: instructions.hh:39707
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B32
GPUStaticInst * decode_OP_SOP1__S_WQM_B32(MachInst)
Definition: decoder.cc:10577
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F16
Definition: instructions.hh:11175
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:12694
gem5::VegaISA::Inst_SOP2__S_OR_B64
Definition: instructions.hh:555
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U32(MachInst)
Definition: decoder.cc:10912
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U64(MachInst)
Definition: decoder.cc:8059
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:4957
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64
Definition: instructions.hh:16207
gem5::VegaISA::InFmt_VINTRP::OP
unsigned int OP
Definition: gpu_decoder.hh:1780
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst)
Definition: decoder.cc:9024
gem5::VegaISA::Inst_VOP3__V_BFM_B32
Definition: instructions.hh:30843
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_U16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:6427
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
Definition: instructions.hh:37543
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16
Definition: instructions.hh:14541
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B64
GPUStaticInst * decode_OP_SOP1__S_WQM_B64(MachInst)
Definition: decoder.cc:10583
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SBYTE
Definition: instructions.hh:36373
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_B64(MachInst)
Definition: decoder.cc:7642
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:12166
gem5::VegaISA::Inst_VOP3__V_MED3_F32
Definition: instructions.hh:28835
gem5::VegaISA::Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10739
gem5::VegaISA::Inst_VOP3__V_SQRT_F16
Definition: instructions.hh:27563
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:6481
gem5::VegaISA::Inst_DS__DS_OR_RTN_B64
Definition: instructions.hh:33895
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8427
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
Definition: instructions.hh:37615
gem5::VegaISA::Inst_VOP2__V_SUB_U32
Definition: instructions.hh:8033
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9972
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL_O
Definition: instructions.hh:40967
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10745
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F32
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F32(MachInst)
Definition: decoder.cc:6337
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:4639
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8820
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64
Definition: instructions.hh:12943
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:11998
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64
Definition: instructions.hh:2857
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:38131
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U64
Definition: instructions.hh:35223
gem5::VegaISA::Inst_VOP3__V_CLREXCP
Definition: instructions.hh:27375
gem5::VegaISA::Inst_VOP3__V_CEIL_F64
Definition: instructions.hh:26447
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F16
Definition: instructions.hh:18179
gem5::VegaISA::Inst_VOP3__V_MUL_LEGACY_F32
Definition: instructions.hh:24165
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_U32(MachInst)
Definition: decoder.cc:7239
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F64
GPUStaticInst * decode_OP_VOP1__V_CEIL_F64(MachInst)
Definition: decoder.cc:11333
gem5::VegaISA::Inst_VINTRP__V_INTERP_P1_F32
Definition: instructions.hh:17193
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U64
GPUStaticInst * decode_OP_SOP2__S_BFE_U64(MachInst)
Definition: decoder.cc:4409
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:5707
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8487
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX
Definition: instructions.hh:42471
gem5::VegaISA::Inst_SOP2__S_MAX_U32
Definition: instructions.hh:351
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64
Definition: instructions.hh:20015
gem5::VegaISA::Inst_DS__DS_GWS_BARRIER
Definition: instructions.hh:35005
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:12400
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:11884
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16
Definition: instructions.hh:21443
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:5569
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B64(MachInst)
Definition: decoder.cc:7124
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32
Definition: instructions.hh:15391
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
Definition: instructions.hh:37651
gem5::VegaISA::InFmt_SMEM
Definition: gpu_decoder.hh:1723
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L_O
Definition: instructions.hh:40067
gem5::VegaISA::Inst_SOP2__S_LSHR_B64
Definition: instructions.hh:1099
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64
Definition: instructions.hh:16921
gem5::VegaISA::Inst_VOP3__V_LERP_U8
Definition: instructions.hh:28511
gem5::VegaISA::Inst_DS__DS_CONSUME
Definition: instructions.hh:35037
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:9636
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst)
Definition: decoder.cc:7112
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9532
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B32(MachInst)
Definition: decoder.cc:10625
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9538
gem5::VegaISA::Inst_VOP3__V_MAD_U16
Definition: instructions.hh:29781
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64
Definition: instructions.hh:2921
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F32
Definition: instructions.hh:8321
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B32(MachInst)
Definition: decoder.cc:10613
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK
GPUStaticInst * decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst)
Definition: decoder.cc:4421
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SETPC_B64
GPUStaticInst * decode_OP_SOP1__S_SETPC_B64(MachInst)
Definition: decoder.cc:10715
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT(MachInst)
Definition: decoder.cc:8518
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9490
gem5::VegaISA::Inst_DS__DS_CMPST_B32
Definition: instructions.hh:31569
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:11189
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
Definition: instructions.hh:41507
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:9738
gem5::VegaISA::Decoder::tableSubDecode_OP_SOP1
static IsaDecodeMethod tableSubDecode_OP_SOP1[256]
Definition: gpu_decoder.hh:71
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64
Definition: instructions.hh:17397
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORD(MachInst)
Definition: decoder.cc:8235
gem5::VegaISA::Inst_VOP1__V_SIN_F16
Definition: instructions.hh:10333
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F64
Definition: instructions.hh:8193
gem5::VegaISA::Inst_DS__DS_READ_B96
Definition: instructions.hh:35651
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16
Definition: instructions.hh:14099
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I32
Definition: instructions.hh:32031
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F32(MachInst)
Definition: decoder.cc:4909
gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32
Definition: instructions.hh:32875
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I64
Definition: instructions.hh:30775
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U32
Definition: instructions.hh:34371
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:4825
gem5::VegaISA::Inst_DS__DS_CMPST_F32
Definition: instructions.hh:31601
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F16
Definition: instructions.hh:18213
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:9708
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:11279
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:12502
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F64
GPUStaticInst * decode_OPU_VOP3__V_RCP_F64(MachInst)
Definition: decoder.cc:6325
gem5::VegaISA::Inst_VOP3__V_FLOOR_F64
Definition: instructions.hh:26511
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:9886
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B32(MachInst)
Definition: decoder.cc:10805
gem5::VegaISA::Inst_VOP3__V_MAD_I32_I24
Definition: instructions.hh:28115
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F32
Definition: instructions.hh:32473
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL
Definition: instructions.hh:39671
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B64
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B64(MachInst)
Definition: decoder.cc:7878
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B32
GPUStaticInst * decode_OP_DS__DS_AND_B32(MachInst)
Definition: decoder.cc:7281
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:5155
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8550
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MOVK_I32
GPUStaticInst * decode_OP_SOPK__S_MOVK_I32(MachInst)
Definition: decoder.cc:4500
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F32
GPUStaticInst * decode_OPU_VOP3__V_SUB_F32(MachInst)
Definition: decoder.cc:5833
gem5::VegaISA::Inst_DS__DS_READ2ST64_B64
Definition: instructions.hh:34303
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F64
Definition: instructions.hh:25775
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:10254
gem5::VegaISA::Inst_DS__DS_WRITE_B8
Definition: instructions.hh:31759
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32
Definition: instructions.hh:12365
gem5::VegaISA::Decoder::subDecode_OP_SOP1
GPUStaticInst * subDecode_OP_SOP1(MachInst)
Definition: decoder.cc:3744
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F32
Definition: instructions.hh:25903
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_I16_F16(MachInst)
Definition: decoder.cc:7178
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:3893
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9406
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:11950
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B16
Definition: instructions.hh:7693
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2
Definition: instructions.hh:43067
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_P
Definition: instructions.hh:34975
gem5::VegaISA::Inst_VOP3__V_BFI_B32
Definition: instructions.hh:28403
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8266
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:6169
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE
Definition: instructions.hh:41762
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst)
Definition: decoder.cc:11164
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F64
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F64(MachInst)
Definition: decoder.cc:11345
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCZ
Definition: instructions.hh:4667
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F64
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F64(MachInst)
Definition: decoder.cc:11327
gem5::VegaISA::Inst_VOP3__V_RSQ_F16
Definition: instructions.hh:27595
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8397
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:5221
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32
Definition: instructions.hh:15629
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F16
GPUStaticInst * decode_OP_VOP1__V_CEIL_F16(MachInst)
Definition: decoder.cc:11592
gem5::VegaISA::Inst_VOP3__V_RCP_F16
Definition: instructions.hh:27531
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10296
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U32
Definition: instructions.hh:34581
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BARRIER
GPUStaticInst * decode_OP_SOPP__S_BARRIER(MachInst)
Definition: decoder.cc:11050
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I32
GPUStaticInst * decode_OP_VOP2__V_MAX_I32(MachInst)
Definition: decoder.cc:3923
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F32
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F32(MachInst)
Definition: decoder.cc:6271
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_F16(MachInst)
Definition: decoder.cc:12968
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B64(MachInst)
Definition: decoder.cc:10799
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8301
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F64(MachInst)
Definition: decoder.cc:5053
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B8_D16_HI(MachInst)
Definition: decoder.cc:7690
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:12364
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U16(MachInst)
Definition: decoder.cc:6967
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U32(MachInst)
Definition: decoder.cc:7938
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_FED_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:6157
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I64(MachInst)
Definition: decoder.cc:12664
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_ADD_U32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_ADD_U32(MachInst)
Definition: decoder.cc:6925
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:12040
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9333
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10408
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B16
Definition: instructions.hh:7659
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B32
GPUStaticInst * decode_OP_DS__DS_READ2_B32(MachInst)
Definition: decoder.cc:7516
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B64
Definition: instructions.hh:35403
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:11890
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F32
Definition: instructions.hh:9761
gem5::VegaISA::Inst_SOP2__S_CSELECT_B32
Definition: instructions.hh:385
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:11315
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:12550
gem5::VegaISA::Inst_VOP2__V_MADAK_F32
Definition: instructions.hh:7025
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:11842
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10034
gem5::VegaISA::Inst_VOP3__V_ALIGNBYTE_B32
Definition: instructions.hh:28583
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64
Definition: instructions.hh:20185
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64
Definition: instructions.hh:23755
gem5::VegaISA::InstFormat::iFmt_VOP3P
InFmt_VOP3P iFmt_VOP3P
Definition: gpu_decoder.hh:1932
gem5::VegaISA::InFmt_SOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1743
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F64
Definition: instructions.hh:9665
gem5::VegaISA::Inst_SOP2__S_ASHR_I64
Definition: instructions.hh:1167
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR(MachInst)
Definition: decoder.cc:10422
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_F32(MachInst)
Definition: decoder.cc:7335
gem5::VegaISA::Decoder::decode_OP_DS__DS_PERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_PERMUTE_B32(MachInst)
Definition: decoder.cc:7558
gem5::VegaISA::Inst_VOP1__V_RCP_F64
Definition: instructions.hh:9281
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10352
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst)
Definition: decoder.cc:8886
gem5::VegaISA::Inst_VOP1__V_LOG_F16
Definition: instructions.hh:10045
gem5::VegaISA::Inst_SOPC__S_SETVSKIP
Definition: instructions.hh:4359
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX
Definition: instructions.hh:42508
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64
Definition: instructions.hh:23041
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F64
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F64(MachInst)
Definition: decoder.cc:6331
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F64
GPUStaticInst * decode_OP_DS__DS_MAX_F64(MachInst)
Definition: decoder.cc:7684
gem5::VegaISA::Inst_VOP3__V_NOP
Definition: instructions.hh:25715
gem5::VegaISA::Inst_SOP2__S_BFM_B32
Definition: instructions.hh:1201
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I16
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I16(MachInst)
Definition: decoder.cc:10679
gem5::VegaISA::Inst_VOP1__V_CVT_F64_I32
Definition: instructions.hh:8225
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I64
GPUStaticInst * decode_OP_SOP2__S_BFE_I64(MachInst)
Definition: decoder.cc:4415
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8287
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:12274
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I32(MachInst)
Definition: decoder.cc:7414
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst)
Definition: decoder.cc:7154
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8203
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:11255
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:11908
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64
Definition: instructions.hh:19777
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:5197
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_F32(MachInst)
Definition: decoder.cc:6553
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGUSER
Definition: instructions.hh:5211
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F32
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F32(MachInst)
Definition: decoder.cc:6265
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR_X2
Definition: instructions.hh:37759
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst)
Definition: decoder.cc:8355
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:4921
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:6409
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_INC
Definition: instructions.hh:39279
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD
Definition: instructions.hh:37039
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64
Definition: instructions.hh:16955
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:5983
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F64(MachInst)
Definition: decoder.cc:8131
gem5::VegaISA::Inst_VOP1__V_LOG_LEGACY_F32
Definition: instructions.hh:10429
gem5::VegaISA::InFmt_SOPP::OP
unsigned int OP
Definition: gpu_decoder.hh:1772
gem5::VegaISA::Inst_VOP1__V_CVT_F64_F32
Definition: instructions.hh:8609
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORD(MachInst)
Definition: decoder.cc:9928
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst)
Definition: decoder.cc:8904
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B32
GPUStaticInst * decode_OP_SOP2__S_BFM_B32(MachInst)
Definition: decoder.cc:4379
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8475
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_OR_B32(MachInst)
Definition: decoder.cc:6943
gem5::VegaISA::Inst_VOP3__V_CVT_F64_I32
Definition: instructions.hh:25807
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U16(MachInst)
Definition: decoder.cc:5293
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F16
Definition: instructions.hh:8449
gem5::VegaISA::Inst_VOP3__V_CMP_T_U32
Definition: instructions.hh:22361
gem5::VegaISA::Inst_VOP3__V_CMP_F_U32
Definition: instructions.hh:22123
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F16
Definition: instructions.hh:11243
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:38207
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64
Definition: instructions.hh:13283
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:12802
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XY
Definition: instructions.hh:35909
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:12226
gem5::VegaISA::Decoder::tableSubDecode_OPU_VOP3
static IsaDecodeMethod tableSubDecode_OPU_VOP3[768]
Definition: gpu_decoder.hh:62
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10506
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32
Definition: instructions.hh:15221
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMREALTIME
GPUStaticInst * decode_OP_SMEM__S_MEMREALTIME(MachInst)
Definition: decoder.cc:10145
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9965
gem5::VegaISA::Inst_SOP2__S_AND_B64
Definition: instructions.hh:487
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_U16(MachInst)
Definition: decoder.cc:12940
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX3
Definition: instructions.hh:36799
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:12244
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9345
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U64
Definition: instructions.hh:33691
gem5::VegaISA::Inst_VOP3__V_MQSAD_PK_U16_U8
Definition: instructions.hh:29417
gem5::VegaISA::Inst_VOP3__V_CVT_F64_F32
Definition: instructions.hh:26191
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F64(MachInst)
Definition: decoder.cc:5101
gpu_static_inst.hh
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_I16_F32
Definition: instructions.hh:30877
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F16
Definition: instructions.hh:26031
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:9696
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOP
GPUStaticInst * decode_OP_VOP1__V_NOP(MachInst)
Definition: decoder.cc:11195
gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32
Definition: instructions.hh:7059
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHRREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHRREV_B16(MachInst)
Definition: decoder.cc:12891
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F16
Definition: instructions.hh:17975
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16
Definition: instructions.hh:14507
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F64(MachInst)
Definition: decoder.cc:7860
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U64(MachInst)
Definition: decoder.cc:10978
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I32(MachInst)
Definition: decoder.cc:12472
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:5539
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETHALT
GPUStaticInst * decode_OP_SOPP__S_SETHALT(MachInst)
Definition: decoder.cc:11068
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:12262
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:6175
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32
Definition: instructions.hh:11957
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:6487
gem5::VegaISA::Decoder::decode_OP_DS__DS_ORDERED_COUNT
GPUStaticInst * decode_OP_DS__DS_ORDERED_COUNT(MachInst)
Definition: decoder.cc:8041
gem5::VegaISA::Inst_VOP3__V_MAD_I16
Definition: instructions.hh:29817
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8161
gem5::VegaISA::InstFormat::iFmt_VINTRP
InFmt_VINTRP iFmt_VINTRP
Definition: gpu_decoder.hh:1922
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16
Definition: instructions.hh:20933
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B64
GPUStaticInst * decode_OP_SOP2__S_LSHL_B64(MachInst)
Definition: decoder.cc:4349
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9520
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst)
Definition: decoder.cc:9006
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F32
GPUStaticInst * decode_OP_VOP1__V_RSQ_F32(MachInst)
Definition: decoder.cc:11405
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:11285
gem5::VegaISA::Inst_VOP3__V_FLOOR_F32
Definition: instructions.hh:26671
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:12070
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:10078
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64
Definition: instructions.hh:23313
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8294
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10041
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32
Definition: instructions.hh:12399
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:6391
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst)
Definition: decoder.cc:11140
gem5::VegaISA::Inst_VOP3__V_CMP_T_U64
Definition: instructions.hh:23449
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U32
Definition: instructions.hh:34461
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BCNT_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_BCNT_U32_B32(MachInst)
Definition: decoder.cc:7100
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:11818
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TRAP
GPUStaticInst * decode_OP_SOPP__S_TRAP(MachInst)
Definition: decoder.cc:11098
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:9907
gem5::VegaISA::Inst_VOP3__V_MAD_F16
Definition: instructions.hh:29745
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I32(MachInst)
Definition: decoder.cc:7920
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN
Definition: instructions.hh:37147
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F64
Definition: instructions.hh:29159
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:5329
gem5::VegaISA::Inst_SOP1__S_BITSET1_B64
Definition: instructions.hh:3113
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:12160
gem5::VegaISA::Inst_VOP3__V_CMP_O_F16
Definition: instructions.hh:17737
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32
Definition: instructions.hh:15663
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U32
Definition: instructions.hh:34611
gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64
Definition: instructions.hh:3495
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16
Definition: instructions.hh:21681
gem5::VegaISA::Inst_VOP2__V_SUBBREV_CO_U32
Definition: instructions.hh:7243
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:12778
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U64(MachInst)
Definition: decoder.cc:5719
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64
Definition: instructions.hh:13011
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U32(MachInst)
Definition: decoder.cc:6673
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:4699
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B64
GPUStaticInst * decode_OP_SOP2__S_XOR_B64(MachInst)
Definition: decoder.cc:4277
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:4993
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B32
GPUStaticInst * decode_OP_SOP2__S_XOR_B32(MachInst)
Definition: decoder.cc:4271
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:38397
gem5::VegaISA::Inst_DS__DS_AND_B64
Definition: instructions.hh:33197
gem5::VegaISA::Decoder::decode_OP_SOPP__S_DECPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_DECPERFLEVEL(MachInst)
Definition: decoder.cc:11116
gem5::VegaISA::Inst_SOP2__S_NOR_B64
Definition: instructions.hh:895
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL
Definition: instructions.hh:39383
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64
Definition: instructions.hh:13725
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2_B32(MachInst)
Definition: decoder.cc:7311
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:6049
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64
Definition: instructions.hh:20083
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I16(MachInst)
Definition: decoder.cc:6869
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F32
Definition: instructions.hh:27311
gem5::VegaISA::Inst_SOP2__S_ADD_I32
Definition: instructions.hh:113
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16
Definition: instructions.hh:14881
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10478
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U32
Definition: instructions.hh:32099
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:9624
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEMA_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEMA_F32(MachInst)
Definition: decoder.cc:6589
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9865
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP
Definition: instructions.hh:36967
gem5::VegaISA::Inst_SOP2__S_CSELECT_B64
Definition: instructions.hh:419
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:5497
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32
Definition: instructions.hh:12229
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8259
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:12496
gem5::VegaISA::Inst_SOP2__S_LSHL_B64
Definition: instructions.hh:1031
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst)
Definition: decoder.cc:8808
gem5::VegaISA::Inst_VOP3__V_COS_F16
Definition: instructions.hh:27947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:5713
gem5::VegaISA::Inst_DS__DS_WRITE_B64
Definition: instructions.hh:33325
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32
Definition: instructions.hh:15153
gem5::VegaISA::Inst_VOP3__V_RSQ_F64
Definition: instructions.hh:26895
gem5::VegaISA::InstFormat::imm_u32
uint32_t imm_u32
Definition: gpu_decoder.hh:1934
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CNDMASK_B32
GPUStaticInst * decode_OPU_VOP3__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:5821
gem5::VegaISA::Inst_SOP2__S_ADDC_U32
Definition: instructions.hh:181
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:10090
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F32(MachInst)
Definition: decoder.cc:7492
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL3_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL3_ADD_U32(MachInst)
Definition: decoder.cc:4465
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F64
Definition: instructions.hh:35523
gem5::VegaISA::Inst_SOP1__S_NOT_B32
Definition: instructions.hh:2377
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:12760
gem5::VegaISA::Inst_VOP1__V_FFBL_B32
Definition: instructions.hh:9569
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16
Definition: instructions.hh:21205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:5413
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P1_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:11177
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAITCNT
GPUStaticInst * decode_OP_SOPP__S_WAITCNT(MachInst)
Definition: decoder.cc:11062
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F64
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F64(MachInst)
Definition: decoder.cc:6403
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:5509
gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32
Definition: instructions.hh:2217
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN_U16(MachInst)
Definition: decoder.cc:6091
gem5::VegaISA::InstFormat::iFmt_SOPP
InFmt_SOPP iFmt_SOPP
Definition: gpu_decoder.hh:1921
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL_O
Definition: instructions.hh:41183
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9588
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F16(MachInst)
Definition: decoder.cc:7028
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32
Definition: instructions.hh:11889
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8319
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I64
Definition: instructions.hh:35283
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE3
Definition: instructions.hh:26319
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_U16(MachInst)
Definition: decoder.cc:12926
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_F32
GPUStaticInst * decode_OP_DS__DS_ADD_F32(MachInst)
Definition: decoder.cc:7353
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:11830
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:11237
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F16
GPUStaticInst * decode_OPU_VOP3__V_COS_F16(MachInst)
Definition: decoder.cc:6529
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10457
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F16
Definition: instructions.hh:18145
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9544
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD(MachInst)
Definition: decoder.cc:10163
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8307
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEID_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEID_F32(MachInst)
Definition: decoder.cc:6571
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:5725
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:5449
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U64
GPUStaticInst * decode_OP_DS__DS_DEC_U64(MachInst)
Definition: decoder.cc:7594
gem5::VegaISA::Inst_SOP2__S_MAX_I32
Definition: instructions.hh:317
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:12310
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I32(MachInst)
Definition: decoder.cc:5437
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F16
GPUStaticInst * decode_OP_VOP1__V_SIN_F16(MachInst)
Definition: decoder.cc:11616
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst)
Definition: decoder.cc:4614
gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64
Definition: instructions.hh:3399
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2
Definition: instructions.hh:5607
gem5::VegaISA::Inst_VOP2__V_SUB_F32
Definition: instructions.hh:6277
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_I32
Definition: instructions.hh:3847
gem5::VegaISA::Inst_SOPK__S_ADDK_I32
Definition: instructions.hh:2057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:4975
gem5::VegaISA::Inst_DS__DS_DEC_U32
Definition: instructions.hh:31175
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16
Definition: instructions.hh:21409
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:11866
gem5::VegaISA::Inst_DS__DS_WRITE2_B64
Definition: instructions.hh:33359
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32
Definition: instructions.hh:19403
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst)
Definition: decoder.cc:9612
gem5::VegaISA::Inst_VOP2__V_MAX_U32
Definition: instructions.hh:6719
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F16
Definition: instructions.hh:11685
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32
Definition: instructions.hh:30469
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F16(MachInst)
Definition: decoder.cc:11752
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F16
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F16(MachInst)
Definition: decoder.cc:6463
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32
Definition: instructions.hh:22055
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10226
gem5::VegaISA::InFmt_SMEM::OP
unsigned int OP
Definition: gpu_decoder.hh:1731
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9460
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL_O
Definition: instructions.hh:40139
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F16
GPUStaticInst * decode_OPU_VOP3__V_MED3_F16(MachInst)
Definition: decoder.cc:6904
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64
Definition: instructions.hh:23959
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9466
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B32(MachInst)
Definition: decoder.cc:10601
gem5::VegaISA::Decoder::subDecode_OP_SMEM
GPUStaticInst * subDecode_OP_SMEM(MachInst)
Definition: decoder.cc:3768
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B64
GPUStaticInst * decode_OP_SOP2__S_LSHR_B64(MachInst)
Definition: decoder.cc:4361
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:11914
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
Definition: instructions.hh:38939
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32
Definition: instructions.hh:18791
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8556
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPC
static IsaDecodeMethod tableSubDecode_OP_SOPC[128]
Definition: gpu_decoder.hh:72
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8736
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_U32
Definition: instructions.hh:1865
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32
Definition: instructions.hh:12569
gem5::VegaISA::Inst_DS__DS_INC_U64
Definition: instructions.hh:33005
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9399
gem5::VegaISA::Inst_VOP3__V_MIN3_U32
Definition: instructions.hh:28691
gem5::VegaISA::InFmt_VOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1787
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_U32
Definition: instructions.hh:1897
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XAD_U32
GPUStaticInst * decode_OPU_VOP3__V_XAD_U32(MachInst)
Definition: decoder.cc:6855
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B32
Definition: instructions.hh:32201
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U32(MachInst)
Definition: decoder.cc:7896
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CLREXCP
GPUStaticInst * decode_OPU_VOP3__V_CLREXCP(MachInst)
Definition: decoder.cc:6421
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:12682
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U32
Definition: instructions.hh:30401
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORD(MachInst)
Definition: decoder.cc:10009
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_U64(MachInst)
Definition: decoder.cc:7612
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64
GPUStaticInst * decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst)
Definition: decoder.cc:7136
gem5::VegaISA::Inst_SOPP__S_DECPERFLEVEL
Definition: instructions.hh:5121
gem5::VegaISA::Inst_VOP3__V_ADD_CO_U32
Definition: instructions.hh:24847
gem5::VegaISA::Inst_VOP3__V_SUBREV_CO_U32
Definition: instructions.hh:24919
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:5575
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F16
Definition: instructions.hh:11107
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:38283
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U32
Definition: instructions.hh:4039
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B
Definition: instructions.hh:39815
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:5455
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORD
Definition: instructions.hh:5571
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst)
Definition: decoder.cc:9171
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2
Definition: instructions.hh:42132
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:12592
gem5::VegaISA::Inst_VOP3__V_MUL_F32
Definition: instructions.hh:24199
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8718
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F32
GPUStaticInst * decode_OP_DS__DS_MAX_F32(MachInst)
Definition: decoder.cc:7341
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:4831
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64
Definition: instructions.hh:16819
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9934
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B32
Definition: instructions.hh:4231
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_F32(MachInst)
Definition: decoder.cc:11381
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst)
Definition: decoder.cc:8778
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16
Definition: instructions.hh:18553
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F16
Definition: instructions.hh:18281
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:5299
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10331
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32(MachInst)
Definition: decoder.cc:7070
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10345
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B16_D16_HI(MachInst)
Definition: decoder.cc:7697
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst)
Definition: decoder.cc:9060
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10275
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U64(MachInst)
Definition: decoder.cc:7764
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U64
GPUStaticInst * decode_OP_DS__DS_MAX_U64(MachInst)
Definition: decoder.cc:7618
gem5::VegaISA::Inst_SOPK__S_CMOVK_I32
Definition: instructions.hh:1641
gem5::VegaISA::Inst_VOP2__V_MUL_I32_I24
Definition: instructions.hh:6413
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst)
Definition: decoder.cc:6781
gem5::VegaISA::Inst_DS__DS_MAX_F64
Definition: instructions.hh:33523
gem5::VegaISA::Inst_VOP3__V_SUBBREV_CO_U32
Definition: instructions.hh:25031
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_F32(MachInst)
Definition: decoder.cc:6301
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:6163
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst)
Definition: decoder.cc:7884
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64
Definition: instructions.hh:19845
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:38359
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9393
gem5::VegaISA::Inst_VOP3__V_MIN3_I32
Definition: instructions.hh:28655
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:4849
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F16
Definition: instructions.hh:11447
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64
Definition: instructions.hh:19981
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst)
Definition: decoder.cc:8982
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:12532
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:12292
gem5::VegaISA::Inst_DS__DS_MAX_I64
Definition: instructions.hh:33101
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C
Definition: instructions.hh:39635
gem5::VegaISA::Inst_VOP3__V_LSHL_OR_B32
Definition: instructions.hh:29673
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10534
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:37941
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SWAP_B32
GPUStaticInst * decode_OP_VOP1__V_SWAP_B32(MachInst)
Definition: decoder.cc:11661
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B(MachInst)
Definition: decoder.cc:9115
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9502
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst)
Definition: decoder.cc:9054
gem5::VegaISA::Inst_VOP3__V_MUL_I32_I24
Definition: instructions.hh:24233
gem5::VegaISA::InstFormat::iFmt_MIMG
InFmt_MIMG iFmt_MIMG
Definition: gpu_decoder.hh:1909
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64
Definition: instructions.hh:20423
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX
Definition: instructions.hh:37183
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst)
Definition: decoder.cc:9159
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16
Definition: instructions.hh:21545
gem5::VegaISA::Inst_VOP3__V_CNDMASK_B32
Definition: instructions.hh:24027
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XOR_B32
GPUStaticInst * decode_OPU_VOP3__V_XOR_B32(MachInst)
Definition: decoder.cc:5947
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32
Definition: instructions.hh:22327
gem5::VegaISA::Inst_VOP3__V_TRUNC_F16
Definition: instructions.hh:27819
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16
Definition: instructions.hh:13997
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64
Definition: instructions.hh:17363
gem5::VegaISA::Inst_VOPC__V_CMP_O_F16
Definition: instructions.hh:10903
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F16(MachInst)
Definition: decoder.cc:4669
gem5::VegaISA::Inst_VOP3__V_MIN3_F32
Definition: instructions.hh:28619
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F16
Definition: instructions.hh:29953
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORD
Definition: instructions.hh:5859
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE_BUFFER
Definition: instructions.hh:6173
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64
Definition: instructions.hh:23687
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9781
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:3953
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F16
Definition: instructions.hh:18519
gem5::VegaISA::Inst_DS__DS_SUB_U32
Definition: instructions.hh:31079
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F64
GPUStaticInst * decode_OP_VOP1__V_FRACT_F64(MachInst)
Definition: decoder.cc:11489
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:5785
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4
Definition: instructions.hh:42206
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I32(MachInst)
Definition: decoder.cc:6667
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B64
GPUStaticInst * decode_OP_DS__DS_XOR_B64(MachInst)
Definition: decoder.cc:7636
gem5::VegaISA::Inst_VOP3__V_SIN_F16
Definition: instructions.hh:27915
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:5113
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32
Definition: instructions.hh:21987
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F16(MachInst)
Definition: decoder.cc:11704
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:9642
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32
Definition: instructions.hh:12773
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ABSDIFF_I32
GPUStaticInst * decode_OP_SOP2__S_ABSDIFF_I32(MachInst)
Definition: decoder.cc:4427
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_I32
GPUStaticInst * decode_OPU_VOP3__V_BFE_I32(MachInst)
Definition: decoder.cc:6601
gem5::VegaISA::Inst_VOP1__V_CEIL_F32
Definition: instructions.hh:9025
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F16
Definition: instructions.hh:10733
gem5::VegaISA::Inst_DS__DS_READ_U8
Definition: instructions.hh:32709
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32
Definition: instructions.hh:2761
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64
Definition: instructions.hh:16309
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:5587
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:12142
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16
Definition: instructions.hh:14711
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE(MachInst)
Definition: decoder.cc:8790
gem5::VegaISA::Inst_MIMG__IMAGE_STORE
Definition: instructions.hh:38727
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32
Definition: instructions.hh:18723
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I32(MachInst)
Definition: decoder.cc:7408
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B64
Definition: instructions.hh:33395
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64
Definition: instructions.hh:16479
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:12436
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:11668
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst)
Definition: decoder.cc:6637
gem5::VegaISA::Inst_DS__DS_MAX_U64
Definition: instructions.hh:33165
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_X
Definition: instructions.hh:38055
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10247
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10527
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64
Definition: instructions.hh:13045
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B32
Definition: instructions.hh:31533
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:12106
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9556
gem5::VegaISA::Inst_SOP2__S_MUL_I32
Definition: instructions.hh:1269
gem5::VegaISA::InFmt_VOP3A
Definition: gpu_decoder.hh:1800
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE(MachInst)
Definition: decoder.cc:8209
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F16
GPUStaticInst * decode_OP_VOP2__V_MUL_F16(MachInst)
Definition: decoder.cc:4049
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32
Definition: instructions.hh:12195
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F32
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F32(MachInst)
Definition: decoder.cc:6289
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:5347
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:9672
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst)
Definition: decoder.cc:11032
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B64
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B64(MachInst)
Definition: decoder.cc:4289
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10394
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT(MachInst)
Definition: decoder.cc:9844
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I32(MachInst)
Definition: decoder.cc:6649
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:12688
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B32
GPUStaticInst * decode_OP_SOP1__S_NOT_B32(MachInst)
Definition: decoder.cc:10565
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64
Definition: instructions.hh:10563
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8191
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:5809
gem5::VegaISA::Inst_VOP2__V_CNDMASK_B32
Definition: instructions.hh:6207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I64
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I64(MachInst)
Definition: decoder.cc:7130
gem5::VegaISA::Inst_VOP3__V_CMP_F_F32
Definition: instructions.hh:18587
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:5473
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F16
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F16(MachInst)
Definition: decoder.cc:11586
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64
Definition: instructions.hh:20389
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:4729
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:5461
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:4705
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B16
Definition: instructions.hh:25409
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10450
gem5::VegaISA::Inst_VOP2__V_SUBREV_U32
Definition: instructions.hh:8067
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B64(MachInst)
Definition: decoder.cc:8113
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC0
Definition: instructions.hh:4607
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L
Definition: instructions.hh:39491
gem5::VegaISA::Inst_VOP3__V_MAD_I64_I32
Definition: instructions.hh:29527
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B64(MachInst)
Definition: decoder.cc:8101
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:6535
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM
GPUStaticInst * decode_OP_SOPP__S_ENDPGM(MachInst)
Definition: decoder.cc:10996
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC(MachInst)
Definition: decoder.cc:8664
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:5005
gem5::VegaISA::Inst_SOP2__S_XOR_B64
Definition: instructions.hh:623
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F64
Definition: instructions.hh:8769
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_F32
Definition: instructions.hh:34821
gem5::VegaISA::Inst_VOP3__V_BFREV_B32
Definition: instructions.hh:27087
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_U8(MachInst)
Definition: decoder.cc:6697
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B32
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B32(MachInst)
Definition: decoder.cc:4283
gem5::VegaISA::Inst_VOP3__V_CMP_T_I32
Definition: instructions.hh:22089
gem5::VegaISA::Inst_VOP3__V_CMP_F_I32
Definition: instructions.hh:21851
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9454
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U32(MachInst)
Definition: decoder.cc:12520
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst)
Definition: decoder.cc:9297
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst)
Definition: decoder.cc:11146
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B32(MachInst)
Definition: decoder.cc:7944
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_U16_F16(MachInst)
Definition: decoder.cc:7185
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32
Definition: instructions.hh:22259
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F32
GPUStaticInst * decode_OP_VOP2__V_MAC_F32(MachInst)
Definition: decoder.cc:3977
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:12052
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B16
Definition: instructions.hh:25375
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:4873
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16
Definition: instructions.hh:14371
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONSUME
GPUStaticInst * decode_OP_DS__DS_CONSUME(MachInst)
Definition: decoder.cc:8029
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SSHORT
Definition: instructions.hh:36449
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I32(MachInst)
Definition: decoder.cc:5479
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I32
Definition: instructions.hh:24607
gem5::VegaISA::Inst_VOP3__V_RCP_F64
Definition: instructions.hh:26863
gem5::VegaISA::Inst_VOP3__V_FFBL_B32
Definition: instructions.hh:27151
gem5::VegaISA::Inst_VOP3__V_LOG_F16
Definition: instructions.hh:27627
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U32(MachInst)
Definition: decoder.cc:7932
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:5875
gem5::VegaISA::Inst_VOP3__V_RNDNE_F32
Definition: instructions.hh:26639
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U32
GPUStaticInst * decode_OP_DS__DS_INC_U32(MachInst)
Definition: decoder.cc:7245
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:12118
gem5::VegaISA::Inst_VOP3__V_MBCNT_LO_U32_B32
Definition: instructions.hh:30639
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_BR
Definition: instructions.hh:34943
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32
Definition: instructions.hh:19607
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:12640
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U16(MachInst)
Definition: decoder.cc:12370
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_U32(MachInst)
Definition: decoder.cc:4566
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:11992
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN_I32(MachInst)
Definition: decoder.cc:5893
gem5::VegaISA::InFmt_DS::OP
unsigned int OP
Definition: gpu_decoder.hh:1604
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:12586
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_O
Definition: instructions.hh:41147
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX
GPUStaticInst * decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst)
Definition: decoder.cc:10829
gem5::VegaISA::Inst_VOP3__V_MUL_F64
Definition: instructions.hh:30265
gem5::VegaISA::Inst_SOP2__S_BFE_U64
Definition: instructions.hh:1371
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F16
Definition: instructions.hh:11719
gem5::VegaISA::Inst_SOP2__S_MUL_HI_U32
Definition: instructions.hh:1541
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32
Definition: instructions.hh:22837
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10387
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U64(MachInst)
Definition: decoder.cc:8053
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_U16(MachInst)
Definition: decoder.cc:6805
gem5::VegaISA::Inst_VOP1__V_CEIL_F16
Definition: instructions.hh:10205
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B64
GPUStaticInst * decode_OP_DS__DS_READ_B64(MachInst)
Definition: decoder.cc:7866
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F64
Definition: instructions.hh:26351
gem5::VegaISA::Inst_DS__DS_SWIZZLE_B32
Definition: instructions.hh:32809
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:5323
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_U16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U16(MachInst)
Definition: decoder.cc:6037
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F32
Definition: instructions.hh:34761
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32
Definition: instructions.hh:18961
gem5::VegaISA::InFmt_MIMG
Definition: gpu_decoder.hh:1656
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F32
Definition: instructions.hh:8353
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8570
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:5503
gem5::VegaISA::Decoder::tableSubDecode_OP_SMEM
static IsaDecodeMethod tableSubDecode_OP_SMEM[256]
Definition: gpu_decoder.hh:70
gem5::VegaISA::Inst_VOP1__V_SQRT_F32
Definition: instructions.hh:9345
gem5::VegaISA::Inst_SOP2__S_SUB_U32
Definition: instructions.hh:79
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_U32(MachInst)
Definition: decoder.cc:4548
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst)
Definition: decoder.cc:7836
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2
Definition: instructions.hh:5787
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I32
Definition: instructions.hh:34521
gem5::VegaISA::Inst_VOP3__V_CMP_T_I64
Definition: instructions.hh:23177
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC
Definition: instructions.hh:42656
gem5::VegaISA::Inst_VOP2__V_MADMK_F16
Definition: instructions.hh:7451
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16_HI(MachInst)
Definition: decoder.cc:7711
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F32
GPUStaticInst * decode_OPU_VOP3__V_ADD_F32(MachInst)
Definition: decoder.cc:5827
gem5::VegaISA::Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64
GPUStaticInst * decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst)
Definition: decoder.cc:4433
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:11980
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B64(MachInst)
Definition: decoder.cc:8119
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B32
GPUStaticInst * decode_OP_SOP2__S_XNOR_B32(MachInst)
Definition: decoder.cc:4331
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:4097
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16
Definition: instructions.hh:14847
gem5::VegaISA::InFmt_SOP1::ENCODING
unsigned int ENCODING
Definition: gpu_decoder.hh:1745
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10464
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMTIME
GPUStaticInst * decode_OP_SMEM__S_MEMTIME(MachInst)
Definition: decoder.cc:10139
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64
Definition: instructions.hh:13215
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F32
Definition: instructions.hh:25935
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:12046
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC0
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC0(MachInst)
Definition: decoder.cc:11014
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U32(MachInst)
Definition: decoder.cc:7384
gem5::VegaISA::Inst_VOP1__V_FFBH_U32
Definition: instructions.hh:9537
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16
Definition: instructions.hh:20831
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64
Definition: instructions.hh:2729
gem5::VegaISA::InstFormat::iFmt_MTBUF
InFmt_MTBUF iFmt_MTBUF
Definition: gpu_decoder.hh:1911
gem5::VegaISA::InFmt_FLAT::OP
unsigned int OP
Definition: gpu_decoder.hh:1639
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8670
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL
Definition: instructions.hh:40643
gem5::VegaISA::Inst_DS__DS_READ2_B64
Definition: instructions.hh:34269
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:9744
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_F32(MachInst)
Definition: decoder.cc:5851
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F64(MachInst)
Definition: decoder.cc:12136
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F16
GPUStaticInst * decode_OP_VOP2__V_MAX_F16(MachInst)
Definition: decoder.cc:4115
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B64
Definition: instructions.hh:34031
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F16
Definition: instructions.hh:17567
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8215
gem5::VegaISA::InFmt_DS
Definition: gpu_decoder.hh:1600
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst)
Definition: decoder.cc:11038
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT
Definition: instructions.hh:41799
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U16(MachInst)
Definition: decoder.cc:12328
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:5653
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32
Definition: instructions.hh:3591
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I32
Definition: instructions.hh:6787
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F16
Definition: instructions.hh:17805
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U32
GPUStaticInst * decode_OPU_VOP3__V_SAD_U32(MachInst)
Definition: decoder.cc:6715
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst)
Definition: decoder.cc:8952
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B64
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B64(MachInst)
Definition: decoder.cc:7800
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst)
Definition: decoder.cc:8940
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64
Definition: instructions.hh:23143
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK
GPUStaticInst * decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst)
Definition: decoder.cc:4596
gem5::VegaISA::Inst_VOP1__V_READFIRSTLANE_B32
Definition: instructions.hh:8161
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F32
GPUStaticInst * decode_OP_VOP2__V_MAX_F32(MachInst)
Definition: decoder.cc:3911
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_U32
Definition: instructions.hh:2025
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B32
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B32(MachInst)
Definition: decoder.cc:7432
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:4987
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_U16(MachInst)
Definition: decoder.cc:12919
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64
Definition: instructions.hh:23721
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64
Definition: instructions.hh:13419
gem5::VegaISA::Inst_VOPC__V_CMP_F_U64
Definition: instructions.hh:16377
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:12478
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F16
GPUStaticInst * decode_OP_VOP1__V_RCP_F16(MachInst)
Definition: decoder.cc:11544
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:11692
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64
Definition: instructions.hh:19879
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_ADDTID_B32(MachInst)
Definition: decoder.cc:7359
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B32
Definition: instructions.hh:34731
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:12832
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32
Definition: instructions.hh:22565
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B32(MachInst)
Definition: decoder.cc:10697
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F32
Definition: instructions.hh:29195
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:5311
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64
Definition: instructions.hh:16683
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B64
Definition: instructions.hh:34065
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:5071
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst)
Definition: decoder.cc:8173
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETPRIO
GPUStaticInst * decode_OP_SOPP__S_SETPRIO(MachInst)
Definition: decoder.cc:11080
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst)
Definition: decoder.cc:8910
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U16
GPUStaticInst * decode_OP_VOP2__V_SUB_U16(MachInst)
Definition: decoder.cc:4079
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U64
Definition: instructions.hh:4423
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B32
Definition: instructions.hh:34701
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64
Definition: instructions.hh:16887
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL2_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL2_ADD_U32(MachInst)
Definition: decoder.cc:4458
gem5::VegaISA::Inst_VOP2__V_MAX_I32
Definition: instructions.hh:6651
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10177
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32
Definition: instructions.hh:15187
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV_VOL
Definition: instructions.hh:6023
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F16
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F16(MachInst)
Definition: decoder.cc:6457
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F16
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F16(MachInst)
Definition: decoder.cc:11598
gem5::VegaISA::Inst_DS__DS_READ_U16
Definition: instructions.hh:32775
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst)
Definition: decoder.cc:6751
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE2
Definition: instructions.hh:8705
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:11532
gem5::VegaISA::Inst_SOPP__S_SLEEP
Definition: instructions.hh:4911
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F16
GPUStaticInst * decode_OP_VOP1__V_FRACT_F16(MachInst)
Definition: decoder.cc:11610
gem5::VegaISA::Inst_VOP1__V_CVT_OFF_F32_I4
Definition: instructions.hh:8545
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32
Definition: instructions.hh:15493
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9582
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:5593
gem5::VegaISA::Inst_SOP2__S_OR_B32
Definition: instructions.hh:521
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2
Definition: instructions.hh:42730
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:61
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:9702
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10191
gem5::VegaISA::Inst_SMEM__S_MEMTIME
Definition: instructions.hh:6079
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16
Definition: instructions.hh:21103
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
Definition: instructions.hh:40319
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9472
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B64
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B64(MachInst)
Definition: decoder.cc:4241
gem5::VegaISA::Inst_VOP2__V_MAX_F32
Definition: instructions.hh:6583
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10769
gem5::VegaISA::InstFormat::iFmt_VOP1
InFmt_VOP1 iFmt_VOP1
Definition: gpu_decoder.hh:1923
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CBRANCH_JOIN
GPUStaticInst * decode_OP_SOP1__S_CBRANCH_JOIN(MachInst)
Definition: decoder.cc:10817
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:5167
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
Definition: instructions.hh:38691
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_I32(MachInst)
Definition: decoder.cc:4542
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD
Definition: instructions.hh:38511
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F64
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F64(MachInst)
Definition: decoder.cc:6247
gem5::VegaISA::Decoder::decode_OP_EXP
GPUStaticInst * decode_OP_EXP(MachInst)
Definition: decoder.cc:4627
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAKEUP
GPUStaticInst * decode_OP_SOPP__S_WAKEUP(MachInst)
Definition: decoder.cc:11008
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst)
Definition: decoder.cc:7148
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F32
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F32(MachInst)
Definition: decoder.cc:11375
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:36251
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L
Definition: instructions.hh:39779
gem5::VegaISA::Inst_VOP2__V_MAC_F16
Definition: instructions.hh:7417
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64
Definition: instructions.hh:17125
gem5::VegaISA::Inst_VOP1__V_TRUNC_F16
Definition: instructions.hh:10237
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR(MachInst)
Definition: decoder.cc:8652
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10366
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2
Definition: instructions.hh:5895
gem5::VegaISA::Inst_VOP2__V_MUL_LO_U16
Definition: instructions.hh:7625
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:5623
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK
Definition: instructions.hh:38583
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:12670
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:11920
gem5::VegaISA::Inst_VOP3__V_CEIL_F32
Definition: instructions.hh:26607
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F16
Definition: instructions.hh:10631
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_WRITELANE_B32
GPUStaticInst * decode_OPU_VOP3__V_WRITELANE_B32(MachInst)
Definition: decoder.cc:7094
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64
Definition: instructions.hh:23857
gem5::VegaISA::Inst_VOP1__V_CVT_RPI_I32_F32
Definition: instructions.hh:8481
gem5::VegaISA::Inst_SOPK__S_MULK_I32
Definition: instructions.hh:2089
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64
Definition: instructions.hh:23415
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9795
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B64
GPUStaticInst * decode_OP_SOP2__S_NOR_B64(MachInst)
Definition: decoder.cc:4325
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:5395
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:5383
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_I16_F16(MachInst)
Definition: decoder.cc:11640
gem5::VegaISA::InstFormat::iFmt_VOPC
InFmt_VOPC iFmt_VOPC
Definition: gpu_decoder.hh:1928
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_F32(MachInst)
Definition: decoder.cc:7329
gem5::VegaISA::Inst_VOP1__V_CVT_U16_F16
Definition: instructions.hh:9885
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B32
GPUStaticInst * decode_OP_SOP2__S_OR_B32(MachInst)
Definition: decoder.cc:4259
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_I32
Definition: instructions.hh:1673
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:37979
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_I32
Definition: instructions.hh:1705
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U16(MachInst)
Definition: decoder.cc:5335
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORD(MachInst)
Definition: decoder.cc:8531
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2
Definition: instructions.hh:43030
gem5::VegaISA::Inst_VOP2__V_SUBREV_F32
Definition: instructions.hh:6311
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B32
GPUStaticInst * decode_OP_DS__DS_OR_B32(MachInst)
Definition: decoder.cc:7287
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F32
Definition: instructions.hh:34791
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32
Definition: instructions.hh:18893
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8373
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8361
gem5::VegaISA::Inst_SOP2__S_ABSDIFF_I32
Definition: instructions.hh:1473
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9436
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_U32(MachInst)
Definition: decoder.cc:10918
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F32
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F32(MachInst)
Definition: decoder.cc:11357
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_LSHL_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_LSHL_U32(MachInst)
Definition: decoder.cc:6931
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8640
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F64(MachInst)
Definition: decoder.cc:7848
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:12406
gem5::VegaISA::Decoder::subDecode_OP_VOP3P
GPUStaticInst * subDecode_OP_VOP3P(MachInst)
Definition: decoder.cc:3728
gem5::VegaISA::Inst_DS__DS_WRITE_B96
Definition: instructions.hh:35583
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I32
Definition: instructions.hh:34551
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_U16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:11520
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16_HI(MachInst)
Definition: decoder.cc:7725
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8445
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:5131
gem5::VegaISA::Inst_SOPP__S_TRAP
Definition: instructions.hh:5031
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F16
Definition: instructions.hh:11345
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC
Definition: instructions.hh:42693
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8
Definition: instructions.hh:5679
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:5023
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B64(MachInst)
Definition: decoder.cc:10643
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F64
GPUStaticInst * decode_OPU_VOP3__V_MAX_F64(MachInst)
Definition: decoder.cc:7052
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B32
GPUStaticInst * decode_OP_SOP2__S_LSHR_B32(MachInst)
Definition: decoder.cc:4355
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9809
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10198
gem5::VegaISA::Inst_VOP2__V_ADD_U32
Definition: instructions.hh:7999
gem5::VegaISA::Inst_VOP1__V_LOG_F32
Definition: instructions.hh:9153
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:4789
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_LDS_DWORD
Definition: instructions.hh:36875
gem5::VegaISA::Inst_VOP3__V_CVT_U16_F16
Definition: instructions.hh:27467
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16
Definition: instructions.hh:14609
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:6145
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_MODE
Definition: instructions.hh:5361
gem5::VegaISA::Inst_SOP2__S_XOR_B32
Definition: instructions.hh:589
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F16
Definition: instructions.hh:11651
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F32
GPUStaticInst * decode_OPU_VOP3__V_SIN_F32(MachInst)
Definition: decoder.cc:6349
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32
Definition: instructions.hh:22803
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F32
GPUStaticInst * decode_OP_VOP1__V_FRACT_F32(MachInst)
Definition: decoder.cc:11351
gem5::VegaISA::Inst_VOP3__V_SAD_U16
Definition: instructions.hh:29015
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I64
Definition: instructions.hh:33725
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I32
GPUStaticInst * decode_OPU_VOP3__V_SUB_I32(MachInst)
Definition: decoder.cc:7199
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8850
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L
Definition: instructions.hh:40787
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_AND
Definition: instructions.hh:39177
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64
Definition: instructions.hh:20321
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst)
Definition: decoder.cc:9213
gem5::VegaISA::Inst_SOP2__S_XNOR_B64
Definition: instructions.hh:963
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:5563
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:12622
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I8
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I8(MachInst)
Definition: decoder.cc:10673
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10485
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B32(MachInst)
Definition: decoder.cc:7317
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16
Definition: instructions.hh:5715
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U64
GPUStaticInst * decode_OP_DS__DS_ADD_U64(MachInst)
Definition: decoder.cc:7570
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U64
Definition: instructions.hh:35193
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F64
Definition: instructions.hh:34167
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32
Definition: instructions.hh:15425
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U32(MachInst)
Definition: decoder.cc:7402
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
Definition: instructions.hh:37687
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F32
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F32(MachInst)
Definition: decoder.cc:7082
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F64
GPUStaticInst * decode_OPU_VOP3__V_MIN_F64(MachInst)
Definition: decoder.cc:7046
gem5::VegaISA::Inst_VOP1__V_FFBH_I32
Definition: instructions.hh:9601
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUBB_U32
GPUStaticInst * decode_OP_SOP2__S_SUBB_U32(MachInst)
Definition: decoder.cc:4205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:4801
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:11680
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64
Definition: instructions.hh:23585
gem5::VegaISA::Inst_VOP3__V_CMP_T_U16
Definition: instructions.hh:21273
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:5263
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8421
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst)
Definition: decoder.cc:9127
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_U32(MachInst)
Definition: decoder.cc:4554
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10499
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:11634
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4(MachInst)
Definition: decoder.cc:9090
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_USHORT
Definition: instructions.hh:36411
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F16
Definition: instructions.hh:11379
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_U16_F16(MachInst)
Definition: decoder.cc:11647
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT(MachInst)
Definition: decoder.cc:8222
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64
Definition: instructions.hh:13317
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SWAP
Definition: instructions.hh:38905
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_ADD_U32(MachInst)
Definition: decoder.cc:4175
gem5::VegaISA::Inst_VOP3__V_SUB_F32
Definition: instructions.hh:24097
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:12352
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:5605
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16
Definition: instructions.hh:21783
gem5::VegaISA::Inst_VOP3__V_CEIL_F16
Definition: instructions.hh:27787
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:9946
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:36061
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:5239
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F32(MachInst)
Definition: decoder.cc:4861
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst)
Definition: decoder.cc:9279
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32
Definition: instructions.hh:19437
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst)
Definition: decoder.cc:7160
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_B32(MachInst)
Definition: decoder.cc:7299
gem5::VegaISA::Inst_SOPP__S_WAITCNT
Definition: instructions.hh:4851
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16
Definition: instructions.hh:14983
gem5::VegaISA::Inst_VOP3__V_SQRT_F32
Definition: instructions.hh:26927
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B64
Definition: instructions.hh:33929
gem5::VegaISA::Inst_VOP3__V_CVT_PKACCUM_U8_F32
Definition: instructions.hh:29989
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F16
Definition: instructions.hh:17839
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I32(MachInst)
Definition: decoder.cc:7926
gem5::VegaISA::Decoder::decode_OP_DS__DS_NOP
GPUStaticInst * decode_OP_DS__DS_NOP(MachInst)
Definition: decoder.cc:7347
gem5::VegaISA::Inst_VOP2__V_SUB_U16
Definition: instructions.hh:7557
gem5::VegaISA::Decoder::subDecode_OP_VOP1
GPUStaticInst * subDecode_OP_VOP1(MachInst)
Definition: decoder.cc:3736
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE0
Definition: instructions.hh:26223
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMAX
Definition: instructions.hh:39109
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F16
GPUStaticInst * decode_OPU_VOP3__V_ADD_F16(MachInst)
Definition: decoder.cc:5995
gem5::VegaISA::Inst_SOP2__S_BFE_U32
Definition: instructions.hh:1303
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F32
Definition: instructions.hh:30057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F16
GPUStaticInst * decode_OPU_VOP3__V_RCP_F16(MachInst)
Definition: decoder.cc:6451
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32
Definition: instructions.hh:22021
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10324
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F32
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F32(MachInst)
Definition: decoder.cc:6283
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32
Definition: instructions.hh:19267
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:5317
gem5::VegaISA::Inst_SOP2__S_LSHR_B32
Definition: instructions.hh:1065
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8409
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX
Definition: instructions.hh:37219
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:4837
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:11321
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8457
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:10027
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_I32(MachInst)
Definition: decoder.cc:7257
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_F16(MachInst)
Definition: decoder.cc:12961
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I32
GPUStaticInst * decode_OPU_VOP3__V_ADD_I32(MachInst)
Definition: decoder.cc:7192
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16(MachInst)
Definition: decoder.cc:7732
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMIN
Definition: instructions.hh:39041
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:3995
gem5::VegaISA::Decoder::subDecode_OP_SOPP
GPUStaticInst * subDecode_OP_SOPP(MachInst)
Definition: decoder.cc:3760
gem5::VegaISA::Inst_VOP2__V_SUBB_CO_U32
Definition: instructions.hh:7205
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9442
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32
Definition: instructions.hh:22531
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:36213
gem5::VegaISA::Inst_VOP3__V_FFBH_U32
Definition: instructions.hh:27119
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE(MachInst)
Definition: decoder.cc:11170
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst)
Definition: decoder.cc:8994
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:5659
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U64(MachInst)
Definition: decoder.cc:8089
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64
Definition: instructions.hh:20457
gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64
Definition: instructions.hh:3303
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:5041
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst)
Definition: decoder.cc:6757
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U32(MachInst)
Definition: decoder.cc:7902
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV
Definition: instructions.hh:5967
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:9648
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:12202
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_U32(MachInst)
Definition: decoder.cc:4560
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR
Definition: instructions.hh:37327
gem5::VegaISA::Inst_VOP3__V_SUBB_CO_U32
Definition: instructions.hh:24993
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F16
Definition: instructions.hh:17465
gem5::VegaISA::Decoder::~Decoder
~Decoder()
Definition: decoder.cc:47
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_V
Definition: instructions.hh:34913
gem5::VegaISA::Decoder::tableSubDecode_OP_VINTRP
static IsaDecodeMethod tableSubDecode_OP_VINTRP[4]
Definition: gpu_decoder.hh:74
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10835
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8856
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B32(MachInst)
Definition: decoder.cc:7474
gem5::VegaISA::Inst_VOPC__V_CMP_T_U32
Definition: instructions.hh:15527
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B64(MachInst)
Definition: decoder.cc:10631
gem5::VegaISA::Inst_VOPC__V_CMP_F_U32
Definition: instructions.hh:15289
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8622
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:12568
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:11399
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:6997
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B64(MachInst)
Definition: decoder.cc:10655
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U8_F32
Definition: instructions.hh:29087
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64
Definition: instructions.hh:13623
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F64(MachInst)
Definition: decoder.cc:8125
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
Definition: instructions.hh:37003
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10184
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT
Definition: instructions.hh:41836
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B64(MachInst)
Definition: decoder.cc:10954
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_U32
GPUStaticInst * decode_OP_SOP2__S_SUB_U32(MachInst)
Definition: decoder.cc:4181
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2
Definition: instructions.hh:43104
gem5::VegaISA::Inst_SOP2__S_BFE_I64
Definition: instructions.hh:1405
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64
Definition: instructions.hh:20627
gem5::VegaISA::Inst_SOPP__S_SENDMSG
Definition: instructions.hh:4971
gem5::VegaISA::Inst_DS__DS_READ_B128
Definition: instructions.hh:35685
gem5::VegaISA::Inst_DS__DS_READ2_B32
Definition: instructions.hh:32609
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F16
Definition: instructions.hh:18247
gem5::VegaISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1680
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B32(MachInst)
Definition: decoder.cc:10942
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F16(MachInst)
Definition: decoder.cc:6007
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F32
Definition: instructions.hh:27343
gem5::VegaISA::Inst_VOP1__V_CVT_F16_F32
Definition: instructions.hh:8417
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B32(MachInst)
Definition: decoder.cc:10649
gem5::VegaISA::Decoder::decode_OP_SOP1__S_GETPC_B64
GPUStaticInst * decode_OP_SOP1__S_GETPC_B64(MachInst)
Definition: decoder.cc:10709
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:11860
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:9630
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:12598
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16
Definition: instructions.hh:21511
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10317
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:5257
gem5::VegaISA::Inst_VOP3__V_SAD_U8
Definition: instructions.hh:28943
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_READ_ADDTID_B32(MachInst)
Definition: decoder.cc:8022
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32
Definition: instructions.hh:16003
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_O
Definition: instructions.hh:40211
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:11495
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32
Definition: instructions.hh:12093
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:12154
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16
Definition: instructions.hh:14065
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:5761
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U32
GPUStaticInst * decode_OP_DS__DS_SUB_U32(MachInst)
Definition: decoder.cc:7233
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U16
GPUStaticInst * decode_OP_VOP2__V_MAX_U16(MachInst)
Definition: decoder.cc:4127
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L_O
Definition: instructions.hh:41219
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F64
Definition: instructions.hh:27247
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst)
Definition: decoder.cc:8958
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:9893
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:5863
gem5::VegaISA::Inst_VOP1__V_SQRT_F64
Definition: instructions.hh:9377
gem5::VegaISA::Inst_VOP3__V_CVT_F16_F32
Definition: instructions.hh:25999
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE
Definition: instructions.hh:39347
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F32(MachInst)
Definition: decoder.cc:6643
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32
Definition: instructions.hh:22293
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_OR_B32(MachInst)
Definition: decoder.cc:6949
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst)
Definition: decoder.cc:8766
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB(MachInst)
Definition: decoder.cc:10121
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I32
GPUStaticInst * decode_OP_SOP2__S_BFE_I32(MachInst)
Definition: decoder.cc:4403
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32
Definition: instructions.hh:22871
gem5::VegaISA::Inst_SOPC__S_CMP_LT_I32
Definition: instructions.hh:3975
gem5::VegaISA::Inst_SOP1__S_MOV_B64
Definition: instructions.hh:2281
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16
Definition: instructions.hh:21817
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst)
Definition: decoder.cc:9267
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F16
Definition: instructions.hh:10801
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U64(MachInst)
Definition: decoder.cc:7794
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32
Definition: instructions.hh:3527
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16
Definition: instructions.hh:14269
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst)
Definition: decoder.cc:9177
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8700
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B64
Definition: instructions.hh:4327
gem5::VegaISA::Inst_DS__DS_INC_RTN_U64
Definition: instructions.hh:33657
gem5::VegaISA::Inst_SOP2__S_SUB_I32
Definition: instructions.hh:147
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I32
GPUStaticInst * decode_OP_SOP2__S_ASHR_I32(MachInst)
Definition: decoder.cc:4367
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_U32
GPUStaticInst * decode_OP_SOP2__S_MIN_U32(MachInst)
Definition: decoder.cc:4217
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16
Definition: instructions.hh:13963
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1
Definition: instructions.hh:36907
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:5269
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:12028
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:11728
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:3869
gem5::VegaISA::InFmt_SOPP
Definition: gpu_decoder.hh:1770
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U24(MachInst)
Definition: decoder.cc:6565
gem5::VegaISA::Inst_DS__DS_NOP
Definition: instructions.hh:31697
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_U32(MachInst)
Definition: decoder.cc:7269
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_I16(MachInst)
Definition: decoder.cc:12905
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64
Definition: instructions.hh:3559
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F16
Definition: instructions.hh:10109
gem5::VegaISA::Inst_SOP2__S_ASHR_I32
Definition: instructions.hh:1133
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst)
Definition: decoder.cc:10133
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE(MachInst)
Definition: decoder.cc:9830
gem5::VegaISA::Inst_SOP1__S_BITSET0_B32
Definition: instructions.hh:3017
gem5::VegaISA::Inst_DS__DS_OR_RTN_B32
Definition: instructions.hh:32167
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:5125
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64
Definition: instructions.hh:16581
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:11902
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:12784
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR
Definition: instructions.hh:42619
gem5::VegaISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1701
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:35757
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F16
Definition: instructions.hh:10699
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB
Definition: instructions.hh:37075
gem5::VegaISA::Inst_VOP3__V_MAX_U32
Definition: instructions.hh:24539
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst)
Definition: decoder.cc:9072
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_X
Definition: instructions.hh:35871
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B32
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B32(MachInst)
Definition: decoder.cc:10781
gem5::VegaISA::InstFormat::iFmt_SOP1
InFmt_SOP1 iFmt_SOP1
Definition: gpu_decoder.hh:1917
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE
Definition: instructions.hh:6139
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:10003
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst)
Definition: decoder.cc:6739
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10060
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:3941
gem5::VegaISA::Inst_VOP3__V_FRACT_F32
Definition: instructions.hh:26543
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:11974
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9569
gem5::VegaISA::Inst_DS__DS_WRAP_RTN_B32
Definition: instructions.hh:32507
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64
Definition: instructions.hh:20661
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_I32(MachInst)
Definition: decoder.cc:4536
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F32(MachInst)
Definition: decoder.cc:4903
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F64
Definition: instructions.hh:9633
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32
Definition: instructions.hh:17329
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F16
GPUStaticInst * decode_OP_VOP2__V_SUB_F16(MachInst)
Definition: decoder.cc:4037
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U64(MachInst)
Definition: decoder.cc:8095
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_O
Definition: instructions.hh:40103
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F16(MachInst)
Definition: decoder.cc:6862
gem5::VegaISA::Inst_SOPC__S_CMP_LT_U32
Definition: instructions.hh:4167
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst)
Definition: decoder.cc:7462
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B32
GPUStaticInst * decode_OP_SOP1__S_CMOV_B32(MachInst)
Definition: decoder.cc:10553
gem5::VegaISA::Inst_VOPC__V_CMP_T_U16
Definition: instructions.hh:14439
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32
Definition: instructions.hh:12603
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_F64(MachInst)
Definition: decoder.cc:7672
gem5::VegaISA::Inst_VOPC__V_CMP_F_F64
Definition: instructions.hh:12841
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B64(MachInst)
Definition: decoder.cc:10811
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL
Definition: instructions.hh:40751
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64
Definition: instructions.hh:20525
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SLEEP
GPUStaticInst * decode_OP_SOPP__S_SLEEP(MachInst)
Definition: decoder.cc:11074
gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64
Definition: instructions.hh:3335
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
Definition: instructions.hh:37435
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:12526
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B64(MachInst)
Definition: decoder.cc:7842
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_I32
Definition: instructions.hh:1833
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F64(MachInst)
Definition: decoder.cc:12130
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B64
GPUStaticInst * decode_OP_SOP2__S_OR_B64(MachInst)
Definition: decoder.cc:4265
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U64
Definition: instructions.hh:33793
gem5::VegaISA::Inst_SOPP__S_SENDMSGHALT
Definition: instructions.hh:5001
gem5::VegaISA::Inst_VOP1__V_RSQ_F32
Definition: instructions.hh:9249
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_U32
Definition: instructions.hh:1929
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_U32(MachInst)
Definition: decoder.cc:4572
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_RELEASE_ALL
Definition: instructions.hh:34851
gem5::VegaISA::Inst_VOP1__V_RCP_F32
Definition: instructions.hh:9185
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:12010
gem5::VegaISA::Inst_VOPC__V_CMP_F_I64
Definition: instructions.hh:16105
gem5::VegaISA::Inst_SOP1__S_RFE_B64
Definition: instructions.hh:3239
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8628
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_U32
Definition: instructions.hh:1993
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32
Definition: instructions.hh:19335
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D
Definition: instructions.hh:39419
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADDC_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:4013
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_U32(MachInst)
Definition: decoder.cc:4578
gem5::VegaISA::Inst_DS__DS_READ_I8
Definition: instructions.hh:32677
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B64
GPUStaticInst * decode_OP_SOP1__S_NOT_B64(MachInst)
Definition: decoder.cc:10571
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_SAVED
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_SAVED(MachInst)
Definition: decoder.cc:11152
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U64(MachInst)
Definition: decoder.cc:12712
gem5::VegaISA::InFmt_MIMG::OP
unsigned int OP
Definition: gpu_decoder.hh:1666
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst)
Definition: decoder.cc:6835
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B64
GPUStaticInst * decode_OP_SOP1__S_CMOV_B64(MachInst)
Definition: decoder.cc:10559
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_B64(MachInst)
Definition: decoder.cc:7666
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32
Definition: instructions.hh:22599
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:5191
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:5407
gem5::VegaISA::Inst_SOP2__S_NOR_B32
Definition: instructions.hh:861
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_I16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:6433
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:12652
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:3881
gem5::VegaISA::Inst_MIMG__IMAGE_GET_LOD
Definition: instructions.hh:41363
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:6127
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:5083
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:4765
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3
Definition: instructions.hh:42169
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:6187
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64
Definition: instructions.hh:17159
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:9750
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX_F32(MachInst)
Definition: decoder.cc:5887
gem5::VegaISA::Inst_VOP1__V_RNDNE_F16
Definition: instructions.hh:10269
gem5::VegaISA::Inst_VOP3__V_LSHL_ADD_U32
Definition: instructions.hh:29565
gem5::VegaISA::Inst_VOP3__V_LDEXP_F32
Definition: instructions.hh:30503
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:12844
gem5::VegaISA::Inst_DS__DS_READ_I16
Definition: instructions.hh:32743
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:12286
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_U32(MachInst)
Definition: decoder.cc:10924
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:12808
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9508
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8
GPUStaticInst * decode_OP_DS__DS_READ_I8(MachInst)
Definition: decoder.cc:7528
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_U32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_U32(MachInst)
Definition: decoder.cc:6373
gem5::VegaISA::Inst_DS__DS_WRITE_B32
Definition: instructions.hh:31463
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F32(MachInst)
Definition: decoder.cc:11896
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U32
GPUStaticInst * decode_OP_DS__DS_ADD_U32(MachInst)
Definition: decoder.cc:7227
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst)
Definition: decoder.cc:9225
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F64
Definition: instructions.hh:29233
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B32
GPUStaticInst * decode_OP_SOP1__S_BREV_B32(MachInst)
Definition: decoder.cc:10589
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:9900
gem5::VegaISA::Inst_VOP3__V_FFBH_I32
Definition: instructions.hh:27183
gem5::VegaISA::Inst_VOP1__V_CVT_F32_U32
Definition: instructions.hh:8289
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:11225
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:5641
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B32(MachInst)
Definition: decoder.cc:10637
gem5::VegaISA::Inst_VOP3__V_READLANE_B32
Definition: instructions.hh:30537
gem5::VegaISA::Inst_SOP2__S_MIN_U32
Definition: instructions.hh:283
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN_U32(MachInst)
Definition: decoder.cc:5905
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64
Definition: instructions.hh:13793
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64
Definition: instructions.hh:17023
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9321
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:12556
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:5077
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:11776
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:38473
gem5::VegaISA::Inst_SOP2__S_MUL_HI_I32
Definition: instructions.hh:1575
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U32(MachInst)
Definition: decoder.cc:10906
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10282
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst)
Definition: decoder.cc:9219
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F16
Definition: instructions.hh:11311
gem5::VegaISA::Inst_VOP3__V_CVT_F32_U32
Definition: instructions.hh:25871
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L_O
Definition: instructions.hh:40355
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:12058
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_U32
GPUStaticInst * decode_OP_SOP2__S_MAX_U32(MachInst)
Definition: decoder.cc:4229
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F64
GPUStaticInst * decode_OP_VOP1__V_RCP_F64(MachInst)
Definition: decoder.cc:11411
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8616
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64
Definition: instructions.hh:3623
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16
Definition: instructions.hh:20899
gem5::VegaISA::Inst_VOP3__V_FRACT_F16
Definition: instructions.hh:27883
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32
Definition: instructions.hh:10461
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10261
gem5::VegaISA::Inst_SOPC__S_CMP_LG_I32
Definition: instructions.hh:3879
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10338
gem5::VegaISA::Inst_VOP3__V_CMP_O_F32
Definition: instructions.hh:18825
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:5389
gem5::VegaISA::Inst_DS__DS_DEC_U64
Definition: instructions.hh:33037
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F16
Definition: instructions.hh:17635
gem5::VegaISA::Inst_VOPC__V_CMP_U_F64
Definition: instructions.hh:13113
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F16
Definition: instructions.hh:17907
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16
Definition: instructions.hh:14575
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR3_B32
GPUStaticInst * decode_OPU_VOP3__V_OR3_B32(MachInst)
Definition: decoder.cc:6955
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8844
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8524
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:12634
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst)
Definition: decoder.cc:6721
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32
Definition: instructions.hh:19097
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:5047
gem5::VegaISA::Inst_VOP2__V_ADD_F32
Definition: instructions.hh:6243
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:11848
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SETVSKIP
GPUStaticInst * decode_OP_SOPC__S_SETVSKIP(MachInst)
Definition: decoder.cc:10966
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECZ
Definition: instructions.hh:4731
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ
Definition: instructions.hh:39887
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B64
GPUStaticInst * decode_OP_DS__DS_OR_B64(MachInst)
Definition: decoder.cc:7630
gem5::VegaISA::Inst_SOP2__S_LSHL_B32
Definition: instructions.hh:997
gem5::VegaISA::Inst_VOP3__V_QSAD_PK_U16_U8
Definition: instructions.hh:29381
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16
Definition: instructions.hh:20797
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_B64(MachInst)
Definition: decoder.cc:7648
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32
Definition: instructions.hh:15969
gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64
Definition: instructions.hh:3367
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U16
GPUStaticInst * decode_OP_VOP2__V_MIN_U16(MachInst)
Definition: decoder.cc:4139
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
Definition: instructions.hh:37903
gem5::VegaISA::Inst_VOP3__V_EXP_LEGACY_F32
Definition: instructions.hh:27979
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV(MachInst)
Definition: decoder.cc:10115
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F16
Definition: instructions.hh:17533
gem5::VegaISA::Inst_SOPP__S_INCPERFLEVEL
Definition: instructions.hh:5091
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:11231
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:12094
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4
Definition: instructions.hh:5643
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFI_B32
GPUStaticInst * decode_OPU_VOP3__V_BFI_B32(MachInst)
Definition: decoder.cc:6607
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN_F16(MachInst)
Definition: decoder.cc:6073
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:9732
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst)
Definition: decoder.cc:6745
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL
Definition: instructions.hh:40859
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U32(MachInst)
Definition: decoder.cc:7378
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:11932
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_I64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_I64(MachInst)
Definition: decoder.cc:10667
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:12304
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9412
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U32
Definition: instructions.hh:34431
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:11722
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LERP_U8
GPUStaticInst * decode_OPU_VOP3__V_LERP_U8(MachInst)
Definition: decoder.cc:6625
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64
Definition: instructions.hh:23993
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B32
GPUStaticInst * decode_OP_DS__DS_XOR_B32(MachInst)
Definition: decoder.cc:7293
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_WREXEC_B64(MachInst)
Definition: decoder.cc:10849
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I32
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:5923
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U32
Definition: instructions.hh:4071
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
Definition: instructions.hh:5241
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND(MachInst)
Definition: decoder.cc:10415
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst)
Definition: decoder.cc:9550
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F32
GPUStaticInst * decode_OP_VOP1__V_SQRT_F32(MachInst)
Definition: decoder.cc:11423
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_B32(MachInst)
Definition: decoder.cc:7323
gem5::VegaISA::Decoder::subDecode_OPU_VOP3
GPUStaticInst * subDecode_OPU_VOP3(MachInst)
Definition: decoder.cc:3776
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I16_F16
Definition: instructions.hh:10141
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_I16(MachInst)
Definition: decoder.cc:12856
gem5::VegaISA::Inst_VOP3__V_MAX_I32
Definition: instructions.hh:24471
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64
Definition: instructions.hh:20559
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:5755
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64
Definition: instructions.hh:13691
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U64
GPUStaticInst * decode_OP_DS__DS_SUB_U64(MachInst)
Definition: decoder.cc:7576
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:9526
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:11968
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_F16(MachInst)
Definition: decoder.cc:12982
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL
Definition: instructions.hh:39455
gem5::VegaISA::Inst_VOP3__V_CMP_T_I16
Definition: instructions.hh:21001
gem5::VegaISA::Inst_VOP3__V_RNDNE_F64
Definition: instructions.hh:26479
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16
Definition: instructions.hh:14949
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10021
gem5::VegaISA::Inst_VOP3__V_FMA_F64
Definition: instructions.hh:28475
gem5::VegaISA::Inst_VOP1__V_RCP_IFLAG_F32
Definition: instructions.hh:9217
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8706
gem5::VegaISA::Inst_SOP2__S_BFE_I32
Definition: instructions.hh:1337
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16
Definition: instructions.hh:21171
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst)
Definition: decoder.cc:8784
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8892
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U64(MachInst)
Definition: decoder.cc:7752
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16_HI(MachInst)
Definition: decoder.cc:7739
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32
Definition: instructions.hh:15459
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F16
Definition: instructions.hh:11039
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:11788
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F16
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F16(MachInst)
Definition: decoder.cc:6505
gem5::VegaISA::Inst_VOP3__V_MAX_F32
Definition: instructions.hh:24403
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:9726
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32
Definition: instructions.hh:12161
gem5::VegaISA::Inst_VOP3__V_LOG_F32
Definition: instructions.hh:26735
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B64
Definition: instructions.hh:33997
gem5::VegaISA::Inst_VOP3__V_SQRT_F64
Definition: instructions.hh:26959
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:10084
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8748
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U32
Definition: instructions.hh:31895
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U64(MachInst)
Definition: decoder.cc:10984
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F16
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F16(MachInst)
Definition: decoder.cc:6499
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst)
Definition: decoder.cc:7172
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_READLANE_B32
GPUStaticInst * decode_OPU_VOP3__V_READLANE_B32(MachInst)
Definition: decoder.cc:7088
gem5::VegaISA::Inst_VOP2__V_SUB_F16
Definition: instructions.hh:7315
gem5::VegaISA::Inst_VOP3__V_MAC_F16
Definition: instructions.hh:25205
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE
Definition: instructions.hh:42021
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8451
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2
Definition: instructions.hh:5427
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F16
Definition: instructions.hh:18485
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9418
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_SHORT
Definition: instructions.hh:36685
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10401
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64
Definition: instructions.hh:13589
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U64
GPUStaticInst * decode_OP_DS__DS_INC_U64(MachInst)
Definition: decoder.cc:7588
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:4651
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9851
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32
Definition: instructions.hh:2825
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:5581
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I64(MachInst)
Definition: decoder.cc:12706
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F16
Definition: instructions.hh:10597
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I16(MachInst)
Definition: decoder.cc:6973
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P2_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:11183
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B
Definition: instructions.hh:40823
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_U64(MachInst)
Definition: decoder.cc:7582
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16
Definition: instructions.hh:21069
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B32(MachInst)
Definition: decoder.cc:7450
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:35985
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F16
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F16(MachInst)
Definition: decoder.cc:6511
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32
Definition: instructions.hh:22701
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U16(MachInst)
Definition: decoder.cc:6897
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ICACHE_INV
GPUStaticInst * decode_OP_SOPP__S_ICACHE_INV(MachInst)
Definition: decoder.cc:11104
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:10066
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64
Definition: instructions.hh:16853
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:12850
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_UBYTE
Definition: instructions.hh:36327
gem5::VegaISA::Inst_VOP3__V_LDEXP_F64
Definition: instructions.hh:30367
gem5::VegaISA::Inst_DS__DS_SUB_U64
Definition: instructions.hh:32941
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND
Definition: instructions.hh:42545
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9823
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I64
Definition: instructions.hh:33759
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_OFF
Definition: instructions.hh:5331
gem5::VegaISA::Inst_VOP3__V_OR_B32
Definition: instructions.hh:24709
gem5::VegaISA::Inst_VOP2__V_MUL_LEGACY_F32
Definition: instructions.hh:6345
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16
Definition: instructions.hh:18009
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:36099
gem5::VegaISA::Decoder::tableSubDecode_OP_SCRATCH
static IsaDecodeMethod tableSubDecode_OP_SCRATCH[128]
Definition: gpu_decoder.hh:69
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:6193
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_F32(MachInst)
Definition: decoder.cc:3875
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F32
GPUStaticInst * decode_OP_VOP2__V_SUB_F32(MachInst)
Definition: decoder.cc:3857
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP(MachInst)
Definition: decoder.cc:8796
gem5::VegaISA::Inst_DS__DS_CONDXCHG32_RTN_B64
Definition: instructions.hh:34337
gem5::VegaISA::Inst_VOP3__V_CUBESC_F32
Definition: instructions.hh:28223
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:5227
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F16
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F16(MachInst)
Definition: decoder.cc:6517
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F64
Definition: instructions.hh:34201
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:4657
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:12610
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:11734
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10751
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F32(MachInst)
Definition: decoder.cc:3863
gem5::VegaISA::Inst_VOPC__V_CMP_F_F32
Definition: instructions.hh:11753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBETC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBETC_F32(MachInst)
Definition: decoder.cc:6583
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_U16(MachInst)
Definition: decoder.cc:12933
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:11824
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:11854
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32
Definition: instructions.hh:22395
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_HI_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_HI_U8(MachInst)
Definition: decoder.cc:6703
gem5::VegaISA::Inst_SOP2__S_ORN2_B32
Definition: instructions.hh:725
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:4867
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
Definition: instructions.hh:38093
gem5::VegaISA::Inst_VOP1__V_COS_F32
Definition: instructions.hh:9441
gem5::VegaISA::Inst_VOP1__V_FRACT_F32
Definition: instructions.hh:8961
gem5::VegaISA::Inst_VOPC__V_CMP_T_I32
Definition: instructions.hh:15255
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LL_F16
Definition: instructions.hh:30125
gem5::VegaISA::Inst_VOP2__V_OR_B32
Definition: instructions.hh:6889
gem5::VegaISA::Inst_VOPC__V_CMP_F_I32
Definition: instructions.hh:15017
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8694
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8415
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst)
Definition: decoder.cc:8976
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:11538
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10492
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:6397
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:5791
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32
Definition: instructions.hh:19131
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:4723
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F64
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F64(MachInst)
Definition: decoder.cc:6343
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:5251
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B64(MachInst)
Definition: decoder.cc:7818
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:4885
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:5521
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE1
Definition: instructions.hh:8673
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32
Definition: instructions.hh:15561
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst)
Definition: decoder.cc:8814
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32
Definition: instructions.hh:19165
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U32
Definition: instructions.hh:31861
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_U32(MachInst)
Definition: decoder.cc:4157
gem5::VegaISA::Inst_VOP1__V_CVT_I16_F16
Definition: instructions.hh:9917
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst)
Definition: decoder.cc:9285
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U64(MachInst)
Definition: decoder.cc:8065
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32
Definition: instructions.hh:12297
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64
Definition: instructions.hh:13555
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32
Definition: instructions.hh:16037
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:38017
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U64(MachInst)
Definition: decoder.cc:12754
gem5::VegaISA::Inst_VOP2__V_MUL_F16
Definition: instructions.hh:7383
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE(MachInst)
Definition: decoder.cc:8505
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:10233
gem5::VegaISA::Inst_SOP2__S_NAND_B64
Definition: instructions.hh:827
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:5779
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B32
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B32(MachInst)
Definition: decoder.cc:7522
gem5::VegaISA::IsaDecodeMethod
GPUStaticInst *(Decoder::*)(MachInst) IsaDecodeMethod
Definition: gpu_decoder.hh:50
gem5::VegaISA::Inst_VOP3__V_PERM_B32
Definition: instructions.hh:29853
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst)
Definition: decoder.cc:6733
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32
Definition: instructions.hh:22429
gem5::VegaISA::Inst_VOP2__V_AND_B32
Definition: instructions.hh:6855
gem5::VegaISA::Inst_VOP3__V_TRUNC_F32
Definition: instructions.hh:26575
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B128
GPUStaticInst * decode_OP_DS__DS_WRITE_B128(MachInst)
Definition: decoder.cc:8143
gem5::VegaISA::Inst_SOP1__S_BREV_B32
Definition: instructions.hh:2505
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:12460
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F16
GPUStaticInst * decode_OP_VOP1__V_LOG_F16(MachInst)
Definition: decoder.cc:11562
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B64(MachInst)
Definition: decoder.cc:10607
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL
Definition: instructions.hh:40535
gem5::VegaISA::Inst_VOP3__V_CVT_I16_F16
Definition: instructions.hh:27499
gem5::VegaISA::Inst_VOP3__V_ADD3_U32
Definition: instructions.hh:29637
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8563
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:6139
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9594
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B64
GPUStaticInst * decode_OP_DS__DS_AND_B64(MachInst)
Definition: decoder.cc:7624
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst)
Definition: decoder.cc:6727
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I16
GPUStaticInst * decode_OPU_VOP3__V_MED3_I16(MachInst)
Definition: decoder.cc:6911
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U16(MachInst)
Definition: decoder.cc:6841
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_I16(MachInst)
Definition: decoder.cc:12912
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_PCK
Definition: instructions.hh:38799
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:12190
gem5::VegaISA::Inst_VOP2__V_SUB_CO_U32
Definition: instructions.hh:7095
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:5533
gem5::VegaISA::Inst_VOP3__V_MIN_F64
Definition: instructions.hh:30299
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ASHRREV_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ASHRREV_I16(MachInst)
Definition: decoder.cc:12898
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:5515
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:12334
gem5::VegaISA::Inst_VOP3__V_CUBEID_F32
Definition: instructions.hh:28187
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst)
Definition: decoder.cc:7009
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10471
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8
GPUStaticInst * decode_OP_DS__DS_READ_U8(MachInst)
Definition: decoder.cc:7534
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U32(MachInst)
Definition: decoder.cc:7426
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U16
GPUStaticInst * decode_OPU_VOP3__V_MED3_U16(MachInst)
Definition: decoder.cc:6918
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:5425
gem5::VegaISA::InstFormat::iFmt_FLAT
InFmt_FLAT iFmt_FLAT
Definition: gpu_decoder.hh:1906
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2_B64(MachInst)
Definition: decoder.cc:7654
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS
Definition: instructions.hh:5181
gem5::VegaISA::Inst_VOP1__V_EXP_F32
Definition: instructions.hh:9121
gem5::VegaISA::InFmt_VOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1828
gem5::VegaISA::Inst_VOP3__V_AND_OR_B32
Definition: instructions.hh:29709
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B32
GPUStaticInst * decode_OP_SOP2__S_LSHL_B32(MachInst)
Definition: decoder.cc:4343
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F64
GPUStaticInst * decode_OPU_VOP3__V_ADD_F64(MachInst)
Definition: decoder.cc:7034
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F64
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F64(MachInst)
Definition: decoder.cc:6253
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10310
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I16
GPUStaticInst * decode_OP_VOP2__V_MAX_I16(MachInst)
Definition: decoder.cc:4133
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U64
Definition: instructions.hh:35163
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:5545
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10219
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:5737
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:35947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_U16
GPUStaticInst * decode_OPU_VOP3__V_SUB_U16(MachInst)
Definition: decoder.cc:6031
gem5::VegaISA::Inst_VOP3__V_CMP_F_U64
Definition: instructions.hh:23211
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F64
Definition: instructions.hh:34133
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8538
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MSAD_U8
GPUStaticInst * decode_OPU_VOP3__V_MSAD_U8(MachInst)
Definition: decoder.cc:6763
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:5599
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:7003
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I32
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:3947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:4663
gem5::VegaISA::InstFormat::iFmt_VOP3B
InFmt_VOP3B iFmt_VOP3B
Definition: gpu_decoder.hh:1927
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD_X2
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD_X2(MachInst)
Definition: decoder.cc:10170
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:5743
gem5::VegaISA::Inst_VOP1__V_FRACT_F16
Definition: instructions.hh:10301
gem5::VegaISA::Decoder::decode_OP_SOP1__S_RFE_B64
GPUStaticInst * decode_OP_SOP1__S_RFE_B64(MachInst)
Definition: decoder.cc:10727
gem5::VegaISA::Inst_VOPC__V_CMP_T_I16
Definition: instructions.hh:14167
gem5::VegaISA::Inst_DS__DS_XOR_B32
Definition: instructions.hh:31399
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B64
Definition: instructions.hh:30741
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8742
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F16
Definition: instructions.hh:11549
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F64
GPUStaticInst * decode_OPU_VOP3__V_FMA_F64(MachInst)
Definition: decoder.cc:6619
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER8H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER8H_PCK(MachInst)
Definition: decoder.cc:9152
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B32
Definition: instructions.hh:32235
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B64
Definition: instructions.hh:34099
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:5749
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B96
GPUStaticInst * decode_OP_DS__DS_READ_B96(MachInst)
Definition: decoder.cc:8149
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:11303
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_I32
Definition: instructions.hh:1737
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64
Definition: instructions.hh:23823
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B64
GPUStaticInst * decode_OP_SOP1__S_MOV_B64(MachInst)
Definition: decoder.cc:10547
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:5971
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:12736
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_I32
Definition: instructions.hh:1801
gem5::VegaISA::Inst_SOP2__S_SUBB_U32
Definition: instructions.hh:215
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_U32
Definition: instructions.hh:1961
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I64(MachInst)
Definition: decoder.cc:7782
gem5::VegaISA::Inst_VOP1__V_MOV_B32
Definition: instructions.hh:8129
gem5::VegaISA::Inst_SOP1__S_CMOV_B64
Definition: instructions.hh:2345
gem5::VegaISA::Inst_DS__DS_XOR_B64
Definition: instructions.hh:33261
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LO_U16
GPUStaticInst * decode_OP_VOP2__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:4091
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:11770
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:6991
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9339
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:12016
gem5::VegaISA::Inst_VOP2__V_XOR_B32
Definition: instructions.hh:6923
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B64
Definition: instructions.hh:30707
gem5::VegaISA::Decoder::decode_OP_VOP2__V_CNDMASK_B32
GPUStaticInst * decode_OP_VOP2__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:3845
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:6313
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX_F16(MachInst)
Definition: decoder.cc:6067
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B32
Definition: instructions.hh:32269
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX_U32(MachInst)
Definition: decoder.cc:5911
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_U32
GPUStaticInst * decode_OP_VOP1__V_FFBH_U32(MachInst)
Definition: decoder.cc:11459
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:6151
gem5::VegaISA::Inst_SOP2__S_MIN_I32
Definition: instructions.hh:249
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B64
GPUStaticInst * decode_OP_SOP2__S_XNOR_B64(MachInst)
Definition: decoder.cc:4337
gem5::VegaISA::Inst_VOP1__V_EXP_LEGACY_F32
Definition: instructions.hh:10397
gem5::VegaISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1776
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F32(MachInst)
Definition: decoder.cc:7974
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst)
Definition: decoder.cc:9042
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:12382
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:9958
gem5::VegaISA::Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10733
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:11580
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst)
Definition: decoder.cc:9600
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:11483
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L_O
Definition: instructions.hh:41003
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:4693
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CLREXCP
GPUStaticInst * decode_OP_VOP1__V_CLREXCP(MachInst)
Definition: decoder.cc:11507
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:4963
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32_U24
Definition: instructions.hh:24335
gem5::VegaISA::Inst_SOPK__S_SETREG_B32
Definition: instructions.hh:2185
gem5::VegaISA::Inst_SOPP__S_ENDPGM
Definition: instructions.hh:4517
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_I32
GPUStaticInst * decode_OP_SOP2__S_MAX_I32(MachInst)
Definition: decoder.cc:4223
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I32
GPUStaticInst * decode_OPU_VOP3__V_MED3_I32(MachInst)
Definition: decoder.cc:6685
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32
Definition: instructions.hh:15731
gem5::VegaISA::Inst_VOP3__V_RSQ_F32
Definition: instructions.hh:26831
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:5143
gem5::VegaISA::InFmt_FLAT::SEG
unsigned int SEG
Definition: gpu_decoder.hh:1636
gem5::VegaISA::Inst_VOP3__V_RCP_F32
Definition: instructions.hh:26767
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16
Definition: instructions.hh:14337
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:11956
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16
Definition: instructions.hh:21749
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:12838
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD(MachInst)
Definition: decoder.cc:8754
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:12772
gem5::VegaISA::Inst_VOP3__V_MAX_F64
Definition: instructions.hh:30333
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst)
Definition: decoder.cc:8760
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10842
gem5::VegaISA::Inst_SOP2__S_ANDN2_B32
Definition: instructions.hh:657
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32(MachInst)
Definition: decoder.cc:7076
gem5::VegaISA::Inst_SOP2__S_XNOR_B32
Definition: instructions.hh:929
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64
Definition: instructions.hh:20117
gem5::VegaISA::Inst_SOPP__S_ICACHE_INV
Definition: instructions.hh:5061
gem5::VegaISA::InstFormat::iFmt_VOP2
InFmt_VOP2 iFmt_VOP2
Definition: gpu_decoder.hh:1924
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst)
Definition: decoder.cc:9514
gem5::VegaISA::Decoder::decode_OP_DS__DS_APPEND
GPUStaticInst * decode_OP_DS__DS_APPEND(MachInst)
Definition: decoder.cc:8035
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U64
Definition: instructions.hh:33827
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F32
GPUStaticInst * decode_OP_VOP1__V_COS_F32(MachInst)
Definition: decoder.cc:11441
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64
Definition: instructions.hh:20287
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst)
Definition: decoder.cc:8922
gem5::VegaISA::Inst_VOP3__V_INTERP_MOV_F32
Definition: instructions.hh:30091
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10520
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:12250
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F32
GPUStaticInst * decode_OPU_VOP3__V_FMA_F32(MachInst)
Definition: decoder.cc:6613
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F32
GPUStaticInst * decode_OP_VOP2__V_MADAK_F32(MachInst)
Definition: decoder.cc:3989
gem5::VegaISA::Inst_VOP1__V_FLOOR_F16
Definition: instructions.hh:10173
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16
Definition: instructions.hh:14235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst)
Definition: decoder.cc:7166
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst)
Definition: decoder.cc:9012
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I16
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:6061
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADDC_U32
GPUStaticInst * decode_OP_SOP2__S_ADDC_U32(MachInst)
Definition: decoder.cc:4199
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B64
Definition: instructions.hh:33963
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
Definition: instructions.hh:41651
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64
Definition: instructions.hh:23551
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64
Definition: instructions.hh:13181
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PACK_B32_F16
GPUStaticInst * decode_OPU_VOP3__V_PACK_B32_F16(MachInst)
Definition: decoder.cc:7220
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:5635
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4
Definition: instructions.hh:36601
gem5::VegaISA::Inst_SOP2__S_CBRANCH_G_FORK
Definition: instructions.hh:1439
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX_U16(MachInst)
Definition: decoder.cc:6079
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B32(MachInst)
Definition: decoder.cc:7438
gem5::VegaISA::Inst_VOP3__V_SUB_U16
Definition: instructions.hh:25273
gem5::VegaISA::Inst_VOP2__V_MIN_U32
Definition: instructions.hh:6685
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:12796
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8273
gem5::VegaISA::Inst_SOP1__S_BITSET0_B64
Definition: instructions.hh:3049
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:12172
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32
Definition: instructions.hh:12637
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:5089
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6769
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8826
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_LEGACY_F16(MachInst)
Definition: decoder.cc:6823
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:9714
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:11219
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9991
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U16(MachInst)
Definition: decoder.cc:4085
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10359
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I16
Definition: instructions.hh:7727
gem5::VegaISA::Inst_VOP3__V_CVT_OFF_F32_I4
Definition: instructions.hh:26127
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1(MachInst)
Definition: decoder.cc:9606
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8838
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8253
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_OR_B32(MachInst)
Definition: decoder.cc:5941
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:5401
gem5::VegaISA::Inst_SMEM__S_STORE_DWORD
Definition: instructions.hh:5751
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBL_B32
GPUStaticInst * decode_OPU_VOP3__V_FFBL_B32(MachInst)
Definition: decoder.cc:6379
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:5275
gem5::VegaISA::Inst_VOP3__V_SUB_CO_U32
Definition: instructions.hh:24883
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_B32(MachInst)
Definition: decoder.cc:5935
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:5767
gem5::VegaISA::Inst_VOP1__V_CVT_FLR_I32_F32
Definition: instructions.hh:8513
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L
Definition: instructions.hh:40571
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND_X2
Definition: instructions.hh:37723
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:5695
gem5::VegaISA::Inst_DS__DS_AND_B32
Definition: instructions.hh:31335
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4
Definition: instructions.hh:5931
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I16
GPUStaticInst * decode_OPU_VOP3__V_ADD_I16(MachInst)
Definition: decoder.cc:7206
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8880
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16
Definition: instructions.hh:21477
gem5::VegaISA::Inst_SOPP__S_BARRIER
Definition: instructions.hh:4791
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64
Definition: instructions.hh:16275
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U32
GPUStaticInst * decode_OP_SOP2__S_BFE_U32(MachInst)
Definition: decoder.cc:4397
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B64(MachInst)
Definition: decoder.cc:8107
gem5::VegaISA::Decoder::decode_invalid
GPUStaticInst * decode_invalid(MachInst)
Definition: decoder.cc:13010
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_I32(MachInst)
Definition: decoder.cc:4512
gem5::VegaISA::InFmt_VOP3P
Definition: gpu_decoder.hh:1883
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B64
GPUStaticInst * decode_OP_SOP1__S_BREV_B64(MachInst)
Definition: decoder.cc:10595
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32
Definition: instructions.hh:2697
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C(MachInst)
Definition: decoder.cc:9133
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:12616
gem5::VegaISA::Inst_VOP1__V_CVT_F32_I32
Definition: instructions.hh:8257
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U16
GPUStaticInst * decode_OPU_VOP3__V_SAD_U16(MachInst)
Definition: decoder.cc:6709
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:11716
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_I32(MachInst)
Definition: decoder.cc:10894
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:12004
gem5::VegaISA::Inst_VOP3__V_MSAD_U8
Definition: instructions.hh:29345
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:12340
gem5::VegaISA::Inst_SOPP__S_ENDPGM_SAVED
Definition: instructions.hh:5301
gem5::VegaISA::Decoder::subDecode_OP_MTBUF
GPUStaticInst * subDecode_OP_MTBUF(MachInst)
Definition: decoder.cc:3829
gem5::VegaISA::Inst_VOP1__V_NOT_B32
Definition: instructions.hh:9473
gem5::VegaISA::Decoder::decode_OP_DS__DS_SWIZZLE_B32
GPUStaticInst * decode_OP_DS__DS_SWIZZLE_B32(MachInst)
Definition: decoder.cc:7552
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_B32(MachInst)
Definition: decoder.cc:7305
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2
Definition: instructions.hh:42806
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32
Definition: instructions.hh:19063
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMAX
Definition: instructions.hh:39143
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2
Definition: instructions.hh:42845
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:11698
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ_O
Definition: instructions.hh:41111
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_F32(MachInst)
Definition: decoder.cc:11393
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U32(MachInst)
Definition: decoder.cc:7064
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:12388
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F16
GPUStaticInst * decode_OPU_VOP3__V_SIN_F16(MachInst)
Definition: decoder.cc:6523
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXLO_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXLO_F16(MachInst)
Definition: decoder.cc:12996
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:12298
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ
Definition: instructions.hh:40679
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64
Definition: instructions.hh:13487
gem5::VegaISA::Inst_VOP3__V_CMP_F_U16
Definition: instructions.hh:21035
gem5::VegaISA::Inst_VOP3__V_CVT_F32_I32
Definition: instructions.hh:25839
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:9762
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F32(MachInst)
Definition: decoder.cc:7968
gem5::VegaISA::Inst_SOP1__S_MOV_B32
Definition: instructions.hh:2249
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMIN
Definition: instructions.hh:39075
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:10048
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32
Definition: instructions.hh:15867
gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64
Definition: instructions.hh:3271
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U64
Definition: instructions.hh:35133
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F16
GPUStaticInst * decode_OP_VOP2__V_MAC_F16(MachInst)
Definition: decoder.cc:4055
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_I32(MachInst)
Definition: decoder.cc:4445
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16
Definition: instructions.hh:14133
gem5::VegaISA::Inst_VOP1__V_TRUNC_F32
Definition: instructions.hh:8993
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:5035
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst)
Definition: decoder.cc:9084
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSG
GPUStaticInst * decode_OP_SOPP__S_SENDMSG(MachInst)
Definition: decoder.cc:11086
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:9979
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst)
Definition: decoder.cc:9030
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_ADD
Definition: instructions.hh:38973
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRAP_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRAP_RTN_B32(MachInst)
Definition: decoder.cc:7498
gem5::VegaISA::Inst_SOPC__S_SET_GPR_IDX_ON
Definition: instructions.hh:4391
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9369
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U64_U32
GPUStaticInst * decode_OPU_VOP3__V_MAD_U64_U32(MachInst)
Definition: decoder.cc:6787
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9940
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64
Definition: instructions.hh:16751
gem5::VegaISA::Decoder::tableSubDecode_OP_MUBUF
static IsaDecodeMethod tableSubDecode_OP_MUBUF[128]
Definition: gpu_decoder.hh:68
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst)
Definition: decoder.cc:9036
gem5::VegaISA::Inst_VOP3__V_CVT_PKRTZ_F16_F32
Definition: instructions.hh:30945
gem5::VegaISA::Inst_VOP2__V_MIN_U16
Definition: instructions.hh:7897
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:5431
gem5::VegaISA::Decoder::decode_OP_VOP1__V_BFREV_B32
GPUStaticInst * decode_OP_VOP1__V_BFREV_B32(MachInst)
Definition: decoder.cc:11453
gem5::VegaISA::Inst_VOP3__V_MAX3_U32
Definition: instructions.hh:28799
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F16
Definition: instructions.hh:10869
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B32
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B32(MachInst)
Definition: decoder.cc:4235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:6211
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32
Definition: instructions.hh:15051
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN_F32(MachInst)
Definition: decoder.cc:5881
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64
Definition: instructions.hh:13351
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8463
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8313
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16
Definition: instructions.hh:14031
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst)
Definition: decoder.cc:9066
gem5::VegaISA::Inst_DS__DS_OR_B64
Definition: instructions.hh:33229
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:11213
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst)
Definition: decoder.cc:8874
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B32(MachInst)
Definition: decoder.cc:7962
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:11806
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK
Definition: instructions.hh:38655
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:9997
gem5::VegaISA::Inst_VOP3__V_ADD_F32
Definition: instructions.hh:24063
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3
Definition: instructions.hh:41947
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2
Definition: instructions.hh:43141
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U32(MachInst)
Definition: decoder.cc:7890
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:11782
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F16
GPUStaticInst * decode_OP_VOP1__V_EXP_F16(MachInst)
Definition: decoder.cc:11568
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:12112
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:5065
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I64
GPUStaticInst * decode_OP_SOP2__S_ASHR_I64(MachInst)
Definition: decoder.cc:4373
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:9618
gem5::VegaISA::Decoder::subDecode_OP_FLAT
GPUStaticInst * subDecode_OP_FLAT(MachInst)
Definition: decoder.cc:3800
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:11243
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32
Definition: instructions.hh:11787
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F32
GPUStaticInst * decode_OP_VOP1__V_CEIL_F32(MachInst)
Definition: decoder.cc:11363
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:9768
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8544
gem5::VegaISA::Inst_VOP3__V_MAD_F32
Definition: instructions.hh:28079
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F16
Definition: instructions.hh:10767
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOT_B32
GPUStaticInst * decode_OP_VOP1__V_NOT_B32(MachInst)
Definition: decoder.cc:11447
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U64
Definition: instructions.hh:4455
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B64
GPUStaticInst * decode_OP_SOP2__S_ORN2_B64(MachInst)
Definition: decoder.cc:4301
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F32
Definition: instructions.hh:29271
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32
Definition: instructions.hh:12433
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:5929
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H(MachInst)
Definition: decoder.cc:9102
gem5::VegaISA::Inst_VOP3__V_MAD_LEGACY_F32
Definition: instructions.hh:28043
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst)
Definition: decoder.cc:9139
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL1_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL1_ADD_U32(MachInst)
Definition: decoder.cc:4451
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:4999
gem5::VegaISA::InstFormat::iFmt_DS
InFmt_DS iFmt_DS
Definition: gpu_decoder.hh:1902
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U32(MachInst)
Definition: decoder.cc:7390
gem5::VegaISA::Inst_VOP2__V_ADD_U16
Definition: instructions.hh:7523
gem5::VegaISA::Inst_VOP2__V_MUL_HI_U32_U24
Definition: instructions.hh:6515
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:6055
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B64
GPUStaticInst * decode_OP_SOP2__S_NAND_B64(MachInst)
Definition: decoder.cc:4313
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:12484
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32
Definition: instructions.hh:15697
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_U32(MachInst)
Definition: decoder.cc:4163
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B64
Definition: instructions.hh:35433
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F64
Definition: instructions.hh:29309
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9387
gem5::VegaISA::Inst_VOP3__V_SAD_U32
Definition: instructions.hh:29051
gem5::VegaISA::Inst_VOP3__V_MAX3_I32
Definition: instructions.hh:28763
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32
Definition: instructions.hh:15833
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10102
gem5::VegaISA::Decoder::subDecode_OP_MUBUF
GPUStaticInst * subDecode_OP_MUBUF(MachInst)
Definition: decoder.cc:3821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:5017
gem5::VegaISA::Inst_VOP3__V_SAD_HI_U8
Definition: instructions.hh:28979
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F16
Definition: instructions.hh:17941
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_O
Definition: instructions.hh:40283
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_U16
GPUStaticInst * decode_OPU_VOP3__V_ADD_U16(MachInst)
Definition: decoder.cc:6025
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U16
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:6043
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:12604
gem5::VegaISA::Inst_VOP2__V_ADDC_CO_U32
Definition: instructions.hh:7167
gem5::VegaISA::Inst_VOP3__V_MAX3_F32
Definition: instructions.hh:28727
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F16
Definition: instructions.hh:11141
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32(MachInst)
Definition: decoder.cc:10661
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B32(MachInst)
Definition: decoder.cc:7956
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16
GPUStaticInst * decode_OP_DS__DS_READ_U16(MachInst)
Definition: decoder.cc:7546
gem5::VegaISA::Inst_VOP3__V_COS_F32
Definition: instructions.hh:27023
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL
Definition: instructions.hh:39563
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:5233
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F16
Definition: instructions.hh:11413
gem5::VegaISA::Inst_VOP3__V_ADDC_CO_U32
Definition: instructions.hh:24955
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:11764
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_USHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_USHORT(MachInst)
Definition: decoder.cc:9788
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32
GPUStaticInst * decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32(MachInst)
Definition: decoder.cc:11513
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9309
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TTRACEDATA
GPUStaticInst * decode_OP_SOPP__S_TTRACEDATA(MachInst)
Definition: decoder.cc:11122
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:9684
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:6541
gem5::VegaISA::Inst_DS__DS_RSUB_U64
Definition: instructions.hh:32973
gem5::VegaISA::InFmt_VOP3A::OP
unsigned int OP
Definition: gpu_decoder.hh:1805
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:11261
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:12064
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16
Definition: instructions.hh:14677
gem5::VegaISA::Inst_VOP3__V_SUB_F16
Definition: instructions.hh:25103
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8604
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64
Definition: instructions.hh:23109
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_O
Definition: instructions.hh:39995
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B32(MachInst)
Definition: decoder.cc:10948
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F16
Definition: instructions.hh:18315
gem5::VegaISA::Inst_VOP3__V_WRITELANE_B32
Definition: instructions.hh:30571
gem5::VegaISA::Inst_VOP2__V_MAX_U16
Definition: instructions.hh:7829
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:5137
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:5209
gem5::VegaISA::Inst_VOP3__V_CMP_F_F64
Definition: instructions.hh:19675
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL4_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL4_ADD_U32(MachInst)
Definition: decoder.cc:4472
gem5::VegaISA::Inst_VOPC__V_CMP_O_F64
Definition: instructions.hh:13079
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst)
Definition: decoder.cc:8349
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE3
Definition: instructions.hh:8737
gem5::VegaISA::Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32
GPUStaticInst * decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst)
Definition: decoder.cc:11207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F64
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F64(MachInst)
Definition: decoder.cc:6241
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64
Definition: instructions.hh:13759
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst)
Definition: decoder.cc:9189
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:5377
gem5::VegaISA::InFmt_MTBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1685
gpu_decoder.hh
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_OR
Definition: instructions.hh:39211
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:11477
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F16
Definition: instructions.hh:11481
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:36137
gem5::VegaISA::Inst_VOP3__V_CMP_F_I64
Definition: instructions.hh:22939
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F16
GPUStaticInst * decode_OP_VOP2__V_MIN_F16(MachInst)
Definition: decoder.cc:4121
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8577
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:11986
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:6445
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:4819
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10443
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B64
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B64(MachInst)
Definition: decoder.cc:10787
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64
Definition: instructions.hh:16989
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
Definition: instructions.hh:37507
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:5803
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:10240
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F64
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F64(MachInst)
Definition: decoder.cc:11339
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64
Definition: instructions.hh:13249
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:11309
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBL_B32
GPUStaticInst * decode_OP_VOP1__V_FFBL_B32(MachInst)
Definition: decoder.cc:11465
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U64
Definition: instructions.hh:33623
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:4933
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16
Definition: instructions.hh:20967
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:4777
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8676
gem5::VegaISA::Decoder::tableSubDecode_OP_MTBUF
static IsaDecodeMethod tableSubDecode_OP_MTBUF[16]
Definition: gpu_decoder.hh:67
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I32
GPUStaticInst * decode_OP_VOP2__V_MIN_I32(MachInst)
Definition: decoder.cc:3917
gem5::VegaISA::Inst_VOPC__V_CMP_F_U16
Definition: instructions.hh:14201
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_I32(MachInst)
Definition: decoder.cc:10888
gem5::VegaISA::Inst_VOP3__V_CMP_U_F32
Definition: instructions.hh:18859
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32
Definition: instructions.hh:22667
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F16
Definition: instructions.hh:17703
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_I32
Definition: instructions.hh:1769
gem5::VegaISA::Inst_SOP1__S_CBRANCH_JOIN
Definition: instructions.hh:3719
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst)
Definition: decoder.cc:11158
gem5::VegaISA::Inst_VOP3__V_SUBREV_U16
Definition: instructions.hh:25307
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:11812
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U32(MachInst)
Definition: decoder.cc:7908
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:5161
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32
Definition: instructions.hh:19029
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32
Definition: instructions.hh:21885
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:9666
gem5::VegaISA::Inst_VOP3__V_EXP_F32
Definition: instructions.hh:26703
gem5::VegaISA::Inst_VOP1__V_CVT_F16_U16
Definition: instructions.hh:9821
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst)
Definition: decoder.cc:8185
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16
Definition: instructions.hh:20865
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F32
GPUStaticInst * decode_OPU_VOP3__V_MAC_F32(MachInst)
Definition: decoder.cc:5953
gem5::VegaISA::Inst_DS__DS_OR_B32
Definition: instructions.hh:31367
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F16
Definition: instructions.hh:27691
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECNZ
Definition: instructions.hh:4761
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32
Definition: instructions.hh:18621
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F16
GPUStaticInst * decode_OP_VOP1__V_COS_F16(MachInst)
Definition: decoder.cc:11622
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:5365
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U32
Definition: instructions.hh:34401
gem5::VegaISA::Inst_SOP1__S_CMOV_B32
Definition: instructions.hh:2313
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64
Definition: instructions.hh:23381
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B64
Definition: instructions.hh:35463
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F16
Definition: instructions.hh:17601
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16
Definition: instructions.hh:14915
gem5::VegaISA::Inst_VOP3__V_MUL_F16
Definition: instructions.hh:25171
gem5::VegaISA::Decoder::decode_OP_SOPK__S_ADDK_I32
GPUStaticInst * decode_OP_SOPK__S_ADDK_I32(MachInst)
Definition: decoder.cc:4584
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8832
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32
Definition: instructions.hh:12501
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9430
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst)
Definition: decoder.cc:9078
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16
Definition: instructions.hh:5535
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:36023
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:12256
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B64(MachInst)
Definition: decoder.cc:10619
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8511
gem5::VegaISA::Inst_VOP3__V_MAD_U32_U24
Definition: instructions.hh:28151
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_BR
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_BR(MachInst)
Definition: decoder.cc:8004
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32
Definition: instructions.hh:19641
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst)
Definition: decoder.cc:9231
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32
Definition: instructions.hh:15085
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:5857
gem5::VegaISA::Inst_SOP1__S_SET_GPR_IDX_IDX
Definition: instructions.hh:3815
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LV_F16
Definition: instructions.hh:30159
gem5::VegaISA::Inst_VOP3__V_CVT_F16_U16
Definition: instructions.hh:27403
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9879
gem5::VegaISA::Inst_VOP3__V_AND_B32
Definition: instructions.hh:24675
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10108
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U32(MachInst)
Definition: decoder.cc:4169
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32
Definition: instructions.hh:15765
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F64
Definition: instructions.hh:8577
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:4927
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F64(MachInst)
Definition: decoder.cc:7854
gem5::VegaISA::Inst_VOP3__V_MOV_B32
Definition: instructions.hh:25743
gem5::VegaISA::Inst_VOP3__V_CMP_U_F64
Definition: instructions.hh:19947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:5281
gem5::VegaISA::Inst_VOP2__V_MIN_I32
Definition: instructions.hh:6617
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64
Definition: instructions.hh:23891
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64
Definition: instructions.hh:20593
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:4813
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:12076
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32
Definition: instructions.hh:11821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:5551
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:11800
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_I32(MachInst)
Definition: decoder.cc:10876
gem5::VegaISA::Inst_VOP3__V_CUBEMA_F32
Definition: instructions.hh:28295
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16(MachInst)
Definition: decoder.cc:6829
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst)
Definition: decoder.cc:8988
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_U16(MachInst)
Definition: decoder.cc:12947
gem5::VegaISA::Decoder::subDecode_OP_VINTRP
GPUStaticInst * subDecode_OP_VINTRP(MachInst)
Definition: decoder.cc:3784
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32
Definition: instructions.hh:22633
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:11872
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16
Definition: instructions.hh:21239
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F64
Definition: instructions.hh:26159
gem5::VegaISA::Inst_VOP2__V_MIN_F32
Definition: instructions.hh:6549
gem5::VegaISA::Inst_VOPC__V_CMP_O_F32
Definition: instructions.hh:11991
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR
Definition: instructions.hh:42582
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:5989
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F16(MachInst)
Definition: decoder.cc:6883
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:4753
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32
Definition: instructions.hh:2633
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_F16(MachInst)
Definition: decoder.cc:6961
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:11962
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL_O
Definition: instructions.hh:41075
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2
Definition: instructions.hh:42882
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B64
GPUStaticInst * decode_OP_DS__DS_READ2_B64(MachInst)
Definition: decoder.cc:7872
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst)
Definition: decoder.cc:9303
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U64
Definition: instructions.hh:35373
instructions.hh
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:4019
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8343
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16
Definition: instructions.hh:21647
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:4945
gem5::VegaISA::Inst_VOP3__V_TRIG_PREOP_F64
Definition: instructions.hh:30809
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32
Definition: instructions.hh:22157
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32
Definition: instructions.hh:17295
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:11686
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORD
Definition: instructions.hh:36487
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:11794
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON
GPUStaticInst * decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst)
Definition: decoder.cc:10972
gem5::VegaISA::Inst_SOPC__S_CMP_LE_I32
Definition: instructions.hh:4007
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32
Definition: instructions.hh:15799
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F32(MachInst)
Definition: decoder.cc:11944
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16
Definition: instructions.hh:21137
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL_O
Definition: instructions.hh:40247
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10373
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITREPLICATE_B64_B32
GPUStaticInst * decode_OP_SOP1__S_BITREPLICATE_B64_B32(MachInst)
Definition: decoder.cc:10863
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:12748
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U64
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U64(MachInst)
Definition: decoder.cc:7746
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_X
Definition: instructions.hh:35719
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F16
GPUStaticInst * decode_OP_VOP1__V_RSQ_F16(MachInst)
Definition: decoder.cc:11556
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_I32(MachInst)
Definition: decoder.cc:10882
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F64(MachInst)
Definition: decoder.cc:5095
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B32
Definition: instructions.hh:24573
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ_O
Definition: instructions.hh:41327
gem5::VegaISA::Decoder::decode_OP_SOP2__S_HH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_HH_B32_B16(MachInst)
Definition: decoder.cc:4493
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst)
Definition: decoder.cc:7106
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F16
GPUStaticInst * decode_OP_VOP2__V_ADD_F16(MachInst)
Definition: decoder.cc:4031
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_I32(MachInst)
Definition: decoder.cc:4518
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64
Definition: instructions.hh:20049
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U32(MachInst)
Definition: decoder.cc:7914
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F16(MachInst)
Definition: decoder.cc:4717
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F64(MachInst)
Definition: decoder.cc:12088
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT
Definition: instructions.hh:42058
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32_I24
Definition: instructions.hh:24267
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:11291
gem5::VegaISA::Inst_VOP3__V_XOR_B32
Definition: instructions.hh:24779
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst)
Definition: decoder.cc:8772
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16
Definition: instructions.hh:21307
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64
Definition: instructions.hh:20355
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U64(MachInst)
Definition: decoder.cc:7770
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL_O
Definition: instructions.hh:39959
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC_X2
Definition: instructions.hh:37831
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:12148
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F16
Definition: instructions.hh:10835
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETKILL
GPUStaticInst * decode_OP_SOPP__S_SETKILL(MachInst)
Definition: decoder.cc:11056
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOT_B32
GPUStaticInst * decode_OPU_VOP3__V_NOT_B32(MachInst)
Definition: decoder.cc:6361
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:4795
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64
Definition: instructions.hh:13147
gem5::VegaISA::Inst_DS__DS_ADD_F32
Definition: instructions.hh:31727
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64
Definition: instructions.hh:23619
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B32
Definition: instructions.hh:24641
gem5::VegaISA::Inst_SOP1__S_WQM_B64
Definition: instructions.hh:2473
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64
Definition: instructions.hh:20491
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:12724
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB
Definition: instructions.hh:42360
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2
Definition: instructions.hh:36525
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U32
GPUStaticInst * decode_OPU_VOP3__V_MED3_U32(MachInst)
Definition: decoder.cc:6691
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8433
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B32
Definition: instructions.hh:4263
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16
Definition: instructions.hh:18043
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8280
gem5::VegaISA::Inst_VOP3__V_CMP_F_F16
Definition: instructions.hh:17499
gem5::VegaISA::InstFormat::iFmt_SOPC
InFmt_SOPC iFmt_SOPC
Definition: gpu_decoder.hh:1919
gem5::VegaISA::Inst_SOPC__S_CMP_LE_U32
Definition: instructions.hh:4199
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFM_B32
GPUStaticInst * decode_OPU_VOP3__V_BFM_B32(MachInst)
Definition: decoder.cc:7142
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:5029
gem5::VegaISA::Inst_DS__DS_INC_RTN_U32
Definition: instructions.hh:31929
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32
Definition: instructions.hh:12671
gem5::VegaISA::Inst_SOPP__S_SETPRIO
Definition: instructions.hh:4941
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_I32
GPUStaticInst * decode_OP_SOP2__S_ADD_I32(MachInst)
Definition: decoder.cc:4187
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16
Definition: instructions.hh:14473
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_I32(MachInst)
Definition: decoder.cc:4530
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBESC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBESC_F32(MachInst)
Definition: decoder.cc:6577
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:6439
gem5::VegaISA::Inst_VOP2__V_SUBREV_U16
Definition: instructions.hh:7591
gem5::VegaISA::Inst_VOP3__V_MBCNT_HI_U32_B32
Definition: instructions.hh:30673
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:5305
gem5::VegaISA::Inst_VOP2__V_MIN_I16
Definition: instructions.hh:7931
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8724
gem5::VegaISA::Inst_VOP3__V_BCNT_U32_B32
Definition: instructions.hh:30605
gem5::VegaISA::Decoder::decode_OP_SOPP__S_NOP
GPUStaticInst * decode_OP_SOPP__S_NOP(MachInst)
Definition: decoder.cc:10990
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64
Definition: instructions.hh:13657
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F16
Definition: instructions.hh:18111
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:12676
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32
Definition: instructions.hh:19301
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I16
GPUStaticInst * decode_OPU_VOP3__V_SUB_I16(MachInst)
Definition: decoder.cc:7213
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:5119
gem5::VegaISA::Decoder::tableSubDecode_OP_VOPC
static IsaDecodeMethod tableSubDecode_OP_VOPC[256]
Definition: gpu_decoder.hh:76
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F16
Definition: instructions.hh:11209
gem5::VegaISA::Inst_VOP3__V_CMP_F_I16
Definition: instructions.hh:20763
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
Definition: instructions.hh:37579
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:6223
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:12394
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_I32
GPUStaticInst * decode_OP_SOP2__S_SUB_I32(MachInst)
Definition: decoder.cc:4193
gem5::VegaISA::Inst_VOP1__V_FLOOR_F64
Definition: instructions.hh:8929
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:9858
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F32
Definition: instructions.hh:32405
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9448
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:5869
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9424
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16
Definition: instructions.hh:21375
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I16(MachInst)
Definition: decoder.cc:12280
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U16(MachInst)
Definition: decoder.cc:6876
gem5::VegaISA::Inst_VOP3__V_FRACT_F64
Definition: instructions.hh:27279
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:5341
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I16
Definition: instructions.hh:25443
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:12466
gem5::VegaISA::Inst_VOP2__V_MIN_F16
Definition: instructions.hh:7795
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst)
Definition: decoder.cc:9291
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B
Definition: instructions.hh:40607
gem5::VegaISA::Inst_SOP1__S_ABS_I32
Definition: instructions.hh:3751
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B32
Definition: instructions.hh:6753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:4735
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B32
Definition: instructions.hh:32371
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:12268
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:12454
gem5::VegaISA::Inst_DS__DS_READ_B32
Definition: instructions.hh:32575
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:35795
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst)
Definition: decoder.cc:7824
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:11926
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8730
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32
Definition: instructions.hh:12807
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:3899
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:5797
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32
Definition: instructions.hh:22735
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32
Definition: instructions.hh:21919
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_I16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:11526
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32
Definition: instructions.hh:2569
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F32
GPUStaticInst * decode_OP_VOP2__V_MIN_F32(MachInst)
Definition: decoder.cc:3905
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F16
Definition: instructions.hh:17431
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:12100
gem5::VegaISA::Inst_VOP3__V_NOT_B32
Definition: instructions.hh:27055
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64
Definition: instructions.hh:2665
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32
Definition: instructions.hh:2889
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:5647
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B64
GPUStaticInst * decode_OP_SOP2__S_AND_B64(MachInst)
Definition: decoder.cc:4253
gem5::VegaISA::Inst_VOP3__V_SUBREV_F16
Definition: instructions.hh:25137
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8167
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst)
Definition: decoder.cc:9261
gem5::VegaISA::Inst_DS__DS_ADD_U32
Definition: instructions.hh:31047
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6775
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F64
Definition: instructions.hh:27215
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC
Definition: instructions.hh:37399
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND(MachInst)
Definition: decoder.cc:8646
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32
Definition: instructions.hh:18655
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32
Definition: instructions.hh:6821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I24(MachInst)
Definition: decoder.cc:6559
gem5::VegaISA::Inst_SOP1__S_SETPC_B64
Definition: instructions.hh:3175
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMOVK_I32
GPUStaticInst * decode_OP_SOPK__S_CMOVK_I32(MachInst)
Definition: decoder.cc:4506
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_F32(MachInst)
Definition: decoder.cc:11387
gem5::VegaISA::Inst_VOP2__V_ADD_F16
Definition: instructions.hh:7281
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64
Definition: instructions.hh:13861
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8385
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_F32(MachInst)
Definition: decoder.cc:6295
gem5::VegaISA::Inst_VOP1__V_EXP_F16
Definition: instructions.hh:10077
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B32(MachInst)
Definition: decoder.cc:7950
gem5::VegaISA::Inst_VOP2__V_MADMK_F32
Definition: instructions.hh:6991
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP
Definition: instructions.hh:42282
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2
Definition: instructions.hh:42956
gem5::VegaISA::Inst_SOPP__S_NOP
Definition: instructions.hh:4487
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:6181
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:12628
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9774
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst)
Definition: decoder.cc:8946
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U64(MachInst)
Definition: decoder.cc:8047
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F16(MachInst)
Definition: decoder.cc:4711
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B32(MachInst)
Definition: decoder.cc:10685
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9496
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_PCK(MachInst)
Definition: decoder.cc:8802
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_F32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_F32(MachInst)
Definition: decoder.cc:7504
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB_VOL
Definition: instructions.hh:6051
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADDC_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:5977
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F16
Definition: instructions.hh:18451
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:12580
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8
Definition: instructions.hh:5499
gem5::VegaISA::Inst_VOP2__V_LDEXP_F16
Definition: instructions.hh:7965
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:12574
gem5::VegaISA::InstFormat::iFmt_SOP2
InFmt_SOP2 iFmt_SOP2
Definition: gpu_decoder.hh:1918
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:12442
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I64(MachInst)
Definition: decoder.cc:5629
gem5::VegaISA::Inst_DS__DS_AND_RTN_B32
Definition: instructions.hh:32133
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32
Definition: instructions.hh:19505
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10513
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B32
GPUStaticInst * decode_OP_SOP2__S_NOR_B32(MachInst)
Definition: decoder.cc:4319
gem5::VegaISA::Decoder::tableSubDecode_OP_FLAT
static IsaDecodeMethod tableSubDecode_OP_FLAT[128]
Definition: gpu_decoder.hh:64
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_I32(MachInst)
Definition: decoder.cc:10870
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:12178
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL
Definition: instructions.hh:39743
gem5::VegaISA::Decoder::Decoder
Decoder()
Definition: decoder.cc:43
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F32
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F32(MachInst)
Definition: decoder.cc:6277
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:5557
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F32
Definition: instructions.hh:9729
gem5::VegaISA::Inst_DS__DS_MIN_F64
Definition: instructions.hh:33491
gem5::VegaISA::Inst_VOP3__V_FMA_F16
Definition: instructions.hh:29917
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
Definition: instructions.hh:41291
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B64
Definition: instructions.hh:35493
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE2
Definition: instructions.hh:26287
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPP
static IsaDecodeMethod tableSubDecode_OP_SOPP[128]
Definition: gpu_decoder.hh:73
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PERM_B32
GPUStaticInst * decode_OPU_VOP3__V_PERM_B32(MachInst)
Definition: decoder.cc:6817
gem5::VegaISA::Inst_VOP2__V_MAX_I16
Definition: instructions.hh:7863
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64
Definition: instructions.hh:16547
gem5::VegaISA::Decoder::subDecode_OP_VOPC
GPUStaticInst * subDecode_OP_VOPC(MachInst)
Definition: decoder.cc:3720
gem5::VegaISA::Inst_SOPP__S_SETKILL
Definition: instructions.hh:4821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:5959
gem5::VegaISA::Inst_VINTRP__V_INTERP_P2_F32
Definition: instructions.hh:17227
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32
Definition: instructions.hh:19199
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LDEXP_F16
GPUStaticInst * decode_OP_VOP2__V_LDEXP_F16(MachInst)
Definition: decoder.cc:4151
gem5::VegaISA::Inst_VOP3__V_CVT_RPI_I32_F32
Definition: instructions.hh:26063
gem5::VegaISA::Inst_DS__DS_MIN_I64
Definition: instructions.hh:33069
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ_O
Definition: instructions.hh:40175
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:12742
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9837
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U64
Definition: instructions.hh:35253
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
Definition: instructions.hh:41579
gem5::VegaISA::Inst_EXP__EXP
Definition: instructions.hh:41687
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD
Definition: instructions.hh:41873
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD
Definition: instructions.hh:41471
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE(MachInst)
Definition: decoder.cc:8898
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD
Definition: instructions.hh:5391
gem5::VegaISA::Inst_DS__DS_WRITE2_B32
Definition: instructions.hh:31497
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F16
GPUStaticInst * decode_OPU_VOP3__V_EXP_F16(MachInst)
Definition: decoder.cc:6475
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32
Definition: instructions.hh:22463
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F16
GPUStaticInst * decode_OP_VOP2__V_MADAK_F16(MachInst)
Definition: decoder.cc:4067
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32
Definition: instructions.hh:22191
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32
Definition: instructions.hh:12331
gem5::VegaISA::Inst_VOP2__V_MAX_F16
Definition: instructions.hh:7761
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F16
Definition: instructions.hh:17669
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32
Definition: instructions.hh:12127
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_F16(MachInst)
Definition: decoder.cc:6979
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64
Definition: instructions.hh:10529
gem5::VegaISA::Inst_VOP3__V_BFE_U32
Definition: instructions.hh:28331
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:12346
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64
Definition: instructions.hh:16139
gem5::VegaISA::Inst_SOP2__S_ANDN2_B64
Definition: instructions.hh:691
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10054
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U32(MachInst)
Definition: decoder.cc:5527
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3
Definition: instructions.hh:36563
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:5107
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:12718
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR
Definition: instructions.hh:37291
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:5353
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst)
Definition: decoder.cc:8970
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst)
Definition: decoder.cc:9207
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32
Definition: instructions.hh:10495
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP1
static IsaDecodeMethod tableSubDecode_OP_VOP1[256]
Definition: gpu_decoder.hh:75
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9375
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32
Definition: instructions.hh:15595
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64
Definition: instructions.hh:16173
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:6217
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16
Definition: instructions.hh:14405
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16
Definition: instructions.hh:21613
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:5701
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP
Definition: instructions.hh:42243
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B32(MachInst)
Definition: decoder.cc:10793
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64
Definition: instructions.hh:12875
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10757
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:4939
gem5::VegaISA::Inst_VOP3__V_SUBREV_F32
Definition: instructions.hh:24131
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64
Definition: instructions.hh:20695
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_USHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_USHORT(MachInst)
Definition: decoder.cc:8469
gem5::VegaISA::Inst_DS__DS_MIN_U64
Definition: instructions.hh:33133
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U32(MachInst)
Definition: decoder.cc:7396
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64
Definition: instructions.hh:20151
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIX_F32
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIX_F32(MachInst)
Definition: decoder.cc:12989
gem5::VegaISA::Inst_VOP2__V_MUL_HI_I32_I24
Definition: instructions.hh:6447
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64
Definition: instructions.hh:2601
gem5::VegaISA::Inst_VOP2__V_MAC_F32
Definition: instructions.hh:6957
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64
Definition: instructions.hh:12909
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP_PCK
Definition: instructions.hh:38835
gem5::VegaISA::Inst_VOP1__V_FLOOR_F32
Definition: instructions.hh:9089
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32
Definition: instructions.hh:15323
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2
Definition: instructions.hh:42919
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F16
Definition: instructions.hh:10971
gem5::VegaISA::Decoder::decode_OP_VOP2__V_XOR_B32
GPUStaticInst * decode_OP_VOP2__V_XOR_B32(MachInst)
Definition: decoder.cc:3971
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:9756
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10775
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND
Definition: instructions.hh:37255
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:4915
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC1
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC1(MachInst)
Definition: decoder.cc:11020
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8610
gem5::VegaISA::Inst_VOPC__V_CMP_F_F16
Definition: instructions.hh:10665
gem5::VegaISA::Inst_VOP3__V_MIN_U32
Definition: instructions.hh:24505
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F32(MachInst)
Definition: decoder.cc:6661
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16
Definition: instructions.hh:14303
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16
GPUStaticInst * decode_OP_DS__DS_WRITE_B16(MachInst)
Definition: decoder.cc:7372
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F32
GPUStaticInst * decode_OPU_VOP3__V_COS_F32(MachInst)
Definition: decoder.cc:6355
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:4879
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:3887
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_O
Definition: instructions.hh:41039
gem5::VegaISA::Inst_MIMG__IMAGE_GET_RESINFO
Definition: instructions.hh:38871
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:5617
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN
Definition: instructions.hh:42397
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst)
Definition: decoder.cc:7468
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32
Definition: instructions.hh:19539
gem5::VegaISA::Inst_VOP2__V_MUL_U32_U24
Definition: instructions.hh:6481
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I32(MachInst)
Definition: decoder.cc:12514
gem5::VegaISA::Inst_VOPC__V_CMP_F_I16
Definition: instructions.hh:13929
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:5011
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LL_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LL_B32_B16(MachInst)
Definition: decoder.cc:4479
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst)
Definition: decoder.cc:9018
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_FMA_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_FMA_F16(MachInst)
Definition: decoder.cc:12954
gem5::VegaISA::Decoder::decode_OP_VOP2__V_AND_B32
GPUStaticInst * decode_OP_VOP2__V_AND_B32(MachInst)
Definition: decoder.cc:3959
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:12082
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8241
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32
Definition: instructions.hh:22769
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8634
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32
Definition: instructions.hh:12739
gem5::VegaISA::Inst_VOP2__V_SUBREV_F16
Definition: instructions.hh:7349
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC(MachInst)
Definition: decoder.cc:10436
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:11297
gem5::VegaISA::Inst_DS__DS_MSKOR_B64
Definition: instructions.hh:33293
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16(MachInst)
Definition: decoder.cc:7021
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:11267
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_U32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_U32(MachInst)
Definition: decoder.cc:4439
gem5::VegaISA::Inst_VOP1__V_SIN_F32
Definition: instructions.hh:9409
gem5::VegaISA::Inst_VOP3__V_FMA_F32
Definition: instructions.hh:28439
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10015
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_F32(MachInst)
Definition: decoder.cc:6307
gem5::VegaISA::Inst_SOPP__S_WAKEUP
Definition: instructions.hh:4577
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H_PCK(MachInst)
Definition: decoder.cc:9145
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:5419
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F16
Definition: instructions.hh:18077
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8493
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U32
GPUStaticInst * decode_OP_VOP2__V_MIN_U32(MachInst)
Definition: decoder.cc:3929
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I16_F16
Definition: instructions.hh:27723
gem5::VegaISA::Decoder::tableDecodePrimary
static IsaDecodeMethod tableDecodePrimary[512]
Definition: gpu_decoder.hh:61
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst)
Definition: decoder.cc:10127
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4
Definition: instructions.hh:5823
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10380
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:36289
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:12544
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst)
Definition: decoder.cc:10157
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10429
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9921
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:9660
gem5::VegaISA::InstFormat
Definition: gpu_decoder.hh:1901
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64
Definition: instructions.hh:17057
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9327
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst)
Definition: decoder.cc:9201
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst)
Definition: decoder.cc:9237
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16
Definition: instructions.hh:21341
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I64(MachInst)
Definition: decoder.cc:8077
gem5::VegaISA::Inst_VOP3__V_MUL_U32_U24
Definition: instructions.hh:24301
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst)
Definition: decoder.cc:8934
gem5::VegaISA::Inst_SOPP__S_BRANCH
Definition: instructions.hh:4547
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
Definition: instructions.hh:37795
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9484
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8
Definition: instructions.hh:2953
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9315
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LH_B32_B16(MachInst)
Definition: decoder.cc:4486
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_O(MachInst)
Definition: decoder.cc:9183
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F16
Definition: instructions.hh:11617
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8862
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U16
GPUStaticInst * decode_OP_VOP2__V_ADD_U16(MachInst)
Definition: decoder.cc:4073
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst)
Definition: decoder.cc:7456
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:11249
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ABS_I32
GPUStaticInst * decode_OP_SOP1__S_ABS_I32(MachInst)
Definition: decoder.cc:10823
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:10072
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B32
Definition: instructions.hh:32303
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:5917
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:6121
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64
Definition: instructions.hh:16241
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:12448
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B64
Definition: instructions.hh:4295
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32
Definition: instructions.hh:3655
gem5::VegaISA::InFmt_MUBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1709
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:5059
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8403
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U64(MachInst)
Definition: decoder.cc:5677
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_O
Definition: instructions.hh:41255
gem5::VegaISA::Decoder::decode_OP_SOPK__S_GETREG_B32
GPUStaticInst * decode_OP_SOPK__S_GETREG_B32(MachInst)
Definition: decoder.cc:4602
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32
Definition: instructions.hh:18927
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX_I16(MachInst)
Definition: decoder.cc:6085
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:12358
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32
Definition: instructions.hh:19233
gem5::VegaISA::Inst_DS__DS_RSUB_U32
Definition: instructions.hh:31111
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst)
Definition: decoder.cc:11026
gem5::VegaISA::Inst_VOP3__V_MOV_FED_B32
Definition: instructions.hh:25967
gem5::VegaISA::Inst_DS__DS_READ_B64
Definition: instructions.hh:34235
gem5::VegaISA::Decoder::subDecode_OP_DS
GPUStaticInst * subDecode_OP_DS(MachInst)
Definition: decoder.cc:3792
gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64
Definition: instructions.hh:3207
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4
Definition: instructions.hh:41984
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16
Definition: instructions.hh:14813
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_DEC
Definition: instructions.hh:39313
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:5683
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:12220
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64
Definition: instructions.hh:12977
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8337
gem5::VegaISA::Inst_VOP1__V_FRACT_F64
Definition: instructions.hh:9697
gem5::VegaISA::Inst_VOP2__V_MADAK_F16
Definition: instructions.hh:7487
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:11273
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F16
GPUStaticInst * decode_OPU_VOP3__V_MAC_F16(MachInst)
Definition: decoder.cc:6019
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:12790
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst)
Definition: decoder.cc:9563
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32
Definition: instructions.hh:12059
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32
Definition: instructions.hh:22497
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst)
Definition: decoder.cc:6631
gem5::VegaISA::Inst_VOP3__V_MIN_U16
Definition: instructions.hh:25613
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F16
Definition: instructions.hh:18349
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:12214
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:12184
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_V
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_V(MachInst)
Definition: decoder.cc:7998
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst)
Definition: decoder.cc:9000
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64
Definition: instructions.hh:13453
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32
Definition: instructions.hh:16071
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:5215
gem5::VegaISA::Inst_SOPP__S_TTRACEDATA
Definition: instructions.hh:5151
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHLREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHLREV_B16(MachInst)
Definition: decoder.cc:12884
gem5::VegaISA::Inst_SOP2__S_AND_B32
Definition: instructions.hh:453
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64
Definition: instructions.hh:22973
gem5::VegaISA::Decoder::decode_OP_SOPP__S_INCPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_INCPERFLEVEL(MachInst)
Definition: decoder.cc:11110
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:4741
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U64
Definition: instructions.hh:33589
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F32
GPUStaticInst * decode_OP_VOP1__V_SIN_F32(MachInst)
Definition: decoder.cc:11435
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:5491
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32
Definition: instructions.hh:15119
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64
Definition: instructions.hh:16717
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F16
Definition: instructions.hh:30195
gem5::VegaISA::Inst_VOP1__V_CVT_F16_I16
Definition: instructions.hh:9853
gem5::VegaISA::InstFormat::iFmt_SMEM
InFmt_SMEM iFmt_SMEM
Definition: gpu_decoder.hh:1915
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE0
Definition: instructions.hh:8641
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I16(MachInst)
Definition: decoder.cc:12322
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:4001
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I64_I32
GPUStaticInst * decode_OPU_VOP3__V_MAD_I64_I32(MachInst)
Definition: decoder.cc:6793
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64
Definition: instructions.hh:19709
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64
Definition: instructions.hh:23007
gem5::VegaISA::Inst_VOP3__V_BFE_I32
Definition: instructions.hh:28367
gem5::VegaISA::Inst_SOP2__S_NAND_B32
Definition: instructions.hh:793
gem5::VegaISA::InFmt_VOP1
Definition: gpu_decoder.hh:1785
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10268
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2
Definition: instructions.hh:42993
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD
Definition: instructions.hh:41399
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:4855
gem5::VegaISA::Inst_DS__DS_GWS_INIT
Definition: instructions.hh:34881
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9363
gem5::VegaISA::InstFormat::iFmt_EXP
InFmt_EXP iFmt_EXP
Definition: gpu_decoder.hh:1904
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2
Definition: instructions.hh:41910
gem5::VegaISA::Inst_VOP2__V_SUBREV_CO_U32
Definition: instructions.hh:7131
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN
Definition: instructions.hh:42434
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U16_U32
Definition: instructions.hh:30979
gem5::VegaISA::Inst_VOPC__V_CMP_T_U64
Definition: instructions.hh:16615
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32
Definition: instructions.hh:11855
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64
Definition: instructions.hh:19743
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP3P
static IsaDecodeMethod tableSubDecode_OP_VOP3P[128]
Definition: gpu_decoder.hh:77
gem5::VegaISA::Inst_DS__DS_INC_U32
Definition: instructions.hh:31143
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:12208
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I32
GPUStaticInst * decode_OP_DS__DS_MAX_I32(MachInst)
Definition: decoder.cc:7263
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16
Definition: instructions.hh:2985
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8331
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ
Definition: instructions.hh:39599
gem5::VegaISA::Inst_SOP1__S_NOT_B64
Definition: instructions.hh:2409
gem5::VegaISA::Inst_VOP3__V_ADD_U16
Definition: instructions.hh:25239
gem5::VegaISA::Inst_VOP3__V_MAD_U64_U32
Definition: instructions.hh:29489
gem5::VegaISA::Inst_VOP3__V_CVT_F16_I16
Definition: instructions.hh:27435
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10289
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:4897
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:12490
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I16(MachInst)
Definition: decoder.cc:5245
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:5611
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:6235
gem5::VegaISA::Inst_DS__DS_ORDERED_COUNT
Definition: instructions.hh:35101
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL
Definition: instructions.hh:39851
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F16
Definition: instructions.hh:18383
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:4675
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:9802
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64
Definition: instructions.hh:23925
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORD
Definition: instructions.hh:36723
gem5::VegaISA::Inst_DS__DS_ADD_RTN_F32
Definition: instructions.hh:32541
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:38245
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16
Definition: instructions.hh:14745
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_I32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_I32(MachInst)
Definition: decoder.cc:6385
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:5203
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32
Definition: instructions.hh:12705
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9478
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8591
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16
Definition: instructions.hh:14643
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_I32
GPUStaticInst * decode_OP_SOP2__S_MIN_I32(MachInst)
Definition: decoder.cc:4211
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:12412
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U64(MachInst)
Definition: decoder.cc:7758
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64
Definition: instructions.hh:20729
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F64
GPUStaticInst * decode_OPU_VOP3__V_MUL_F64(MachInst)
Definition: decoder.cc:7040
gem5::VegaISA::Inst_VOP3__V_MIN_I32
Definition: instructions.hh:24437
gem5::VegaISA::Decoder::decode_OP_VOP1__V_MOV_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_B32(MachInst)
Definition: decoder.cc:11201
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F16
GPUStaticInst * decode_OP_VOP2__V_MADMK_F16(MachInst)
Definition: decoder.cc:4061
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32
Definition: instructions.hh:15357
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64
Definition: instructions.hh:13827
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_LO_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_LO_U16(MachInst)
Definition: decoder.cc:12863
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I64(MachInst)
Definition: decoder.cc:5671
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:12538
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_O
Definition: instructions.hh:39923
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B32
Definition: instructions.hh:32337
gem5::VegaISA::Inst_VOP3__V_CVT_FLR_I32_F32
Definition: instructions.hh:26095
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst)
Definition: decoder.cc:9165
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:5815
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst)
Definition: decoder.cc:8916
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL_O
Definition: instructions.hh:40031
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst)
Definition: decoder.cc:6547
gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64
Definition: instructions.hh:3431
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:36175
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:6205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_B32(MachInst)
Definition: decoder.cc:6115
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst)
Definition: decoder.cc:11134
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32
Definition: instructions.hh:15901
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F16
Definition: instructions.hh:11005
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_I16(MachInst)
Definition: decoder.cc:6811
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:11710
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:38435
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64
Definition: instructions.hh:23245
gem5::VegaISA::InFmt_SOP1
Definition: gpu_decoder.hh:1741
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE
Definition: instructions.hh:41725
gem5::VegaISA::Inst_VOP3__V_MIN_F32
Definition: instructions.hh:24369
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst)
Definition: decoder.cc:9096
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I64(MachInst)
Definition: decoder.cc:7776
gem5::VegaISA::Inst_VOP3__V_FLOOR_F16
Definition: instructions.hh:27755
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U32(MachInst)
Definition: decoder.cc:12562
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8712
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F32
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F32(MachInst)
Definition: decoder.cc:11369
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U64(MachInst)
Definition: decoder.cc:8071
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_U32(MachInst)
Definition: decoder.cc:10930
gem5::VegaISA::Inst_VOP3__V_MAX_U16
Definition: instructions.hh:25545
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U64(MachInst)
Definition: decoder.cc:7788
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:5965
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:4645
gem5::VegaISA::Inst_SOPK__S_CBRANCH_I_FORK
Definition: instructions.hh:2121
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:4747
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B64(MachInst)
Definition: decoder.cc:7118
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX4
Definition: instructions.hh:36837
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64
Definition: instructions.hh:23279
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32
Definition: instructions.hh:22905
gem5::VegaISA::Inst_DS__DS_PERMUTE_B32
Definition: instructions.hh:32841
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F64
Definition: instructions.hh:35553
gem5::VegaISA::Inst_VINTRP__V_INTERP_MOV_F32
Definition: instructions.hh:17261
gem5::VegaISA::Decoder::decode_OP_VOP2__V_OR_B32
GPUStaticInst * decode_OP_VOP2__V_OR_B32(MachInst)
Definition: decoder.cc:3965
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I32
Definition: instructions.hh:31997
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B64(MachInst)
Definition: decoder.cc:10691
gem5::VegaISA::Inst_VOP3__V_TRUNC_F64
Definition: instructions.hh:26415
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1_VOL
Definition: instructions.hh:36937
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:9654
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F32
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F32(MachInst)
Definition: decoder.cc:6319
gem5::VegaISA::Decoder::tableSubDecode_OP_GLOBAL
static IsaDecodeMethod tableSubDecode_OP_GLOBAL[128]
Definition: gpu_decoder.hh:65
gem5::VegaISA::Inst_SOPP__S_SETHALT
Definition: instructions.hh:4881
gem5::VegaISA::Inst_DS__DS_MIN_F32
Definition: instructions.hh:31633
gem5::VegaISA::InFmt_VOPC
Definition: gpu_decoder.hh:1825
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U32
Definition: instructions.hh:31963
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:35833
gem5::VegaISA::Inst_DS__DS_MAX_F32
Definition: instructions.hh:31665
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10763
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:4951
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U32
GPUStaticInst * decode_OP_DS__DS_DEC_U32(MachInst)
Definition: decoder.cc:7251
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_F16(MachInst)
Definition: decoder.cc:12975
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I64
Definition: instructions.hh:35313
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F32
Definition: instructions.hh:32439
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_O
Definition: instructions.hh:40391
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst)
Definition: decoder.cc:8868
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64
Definition: instructions.hh:23483
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64
Definition: instructions.hh:23075
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_WREXEC_B64(MachInst)
Definition: decoder.cc:10856
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst)
Definition: decoder.cc:9273
gem5::VegaISA::Inst_DS__DS_MIN_I32
Definition: instructions.hh:31207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:5665
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:4633
gem5::VegaISA::Inst_DS__DS_MAX_I32
Definition: instructions.hh:31239
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B128
GPUStaticInst * decode_OP_DS__DS_READ_B128(MachInst)
Definition: decoder.cc:8155
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:12700
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:9952
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:11674
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXHI_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXHI_F16(MachInst)
Definition: decoder.cc:13003
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst)
Definition: decoder.cc:6985
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9351
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I16(MachInst)
Definition: decoder.cc:6848
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L(MachInst)
Definition: decoder.cc:9109
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64
Definition: instructions.hh:23653
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:4007
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64
Definition: instructions.hh:19811
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
Definition: instructions.hh:40463
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORD(MachInst)
Definition: decoder.cc:8481
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:4103
gem5::VegaISA::InFmt_VOP3P::OP
unsigned int OP
Definition: gpu_decoder.hh:1889
gem5::VegaISA::Inst_DS__DS_READ2ST64_B32
Definition: instructions.hh:32643
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:12658
gem5::VegaISA::Inst_DS__DS_CMPST_B64
Definition: instructions.hh:33427
gem5::VegaISA::Inst_SOPC__S_CMP_GT_I32
Definition: instructions.hh:3911
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64
Definition: instructions.hh:20219
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I16(MachInst)
Definition: decoder.cc:6890
gem5::VegaISA::Decoder::subDecode_OP_SOPC
GPUStaticInst * subDecode_OP_SOPC(MachInst)
Definition: decoder.cc:3752
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4
Definition: instructions.hh:5463
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64
Definition: instructions.hh:16649
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:6133
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32
Definition: instructions.hh:19471
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F32(MachInst)
Definition: decoder.cc:5839
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B96
GPUStaticInst * decode_OP_DS__DS_WRITE_B96(MachInst)
Definition: decoder.cc:8137
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F16
Definition: instructions.hh:11515
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX2
Definition: instructions.hh:36761
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:11628
gem5::VegaISA::Inst_VOP3__V_CMP_U_F16
Definition: instructions.hh:17771
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B64(MachInst)
Definition: decoder.cc:10703
gem5::VegaISA::Inst_DS__DS_CMPST_F64
Definition: instructions.hh:33459
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16
Definition: instructions.hh:21579
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U32(MachInst)
Definition: decoder.cc:5485
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_U16_F32
Definition: instructions.hh:30911
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:12766
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64
Definition: instructions.hh:13385
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:4687
gem5::VegaISA::Inst_VOP1__V_RSQ_F16
Definition: instructions.hh:10013
gem5::VegaISA::Inst_SOP2__S_ORN2_B64
Definition: instructions.hh:759
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:38169
gem5::VegaISA::Inst_VOP3__V_CMP_O_F64
Definition: instructions.hh:19913
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_I64(MachInst)
Definition: decoder.cc:7600
gem5::VegaISA::Inst_VOP1__V_RCP_F16
Definition: instructions.hh:9949
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_B32(MachInst)
Definition: decoder.cc:10541
gem5::VegaISA::Inst_VOP3__V_EXP_F16
Definition: instructions.hh:27659
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:11878
gem5::VegaISA::Inst_VOP1__V_CVT_F64_U32
Definition: instructions.hh:8801
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F16
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F16(MachInst)
Definition: decoder.cc:6493
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32
Definition: instructions.hh:21953
gem5::VegaISA::Inst_DS__DS_MIN_U32
Definition: instructions.hh:31271
gem5::VegaISA::Inst_DS__DS_MAX_U32
Definition: instructions.hh:31303
gem5::VegaISA::Inst_VOP3__V_MIN_I16
Definition: instructions.hh:25647
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_I16(MachInst)
Definition: decoder.cc:12870
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:12022
gem5::VegaISA::Inst_DS__DS_MSKOR_B32
Definition: instructions.hh:31431
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2
Definition: instructions.hh:43178
gem5::VegaISA::InFmt_SOPC
Definition: gpu_decoder.hh:1756
gem5::VegaISA::Inst_VOP1__V_BFREV_B32
Definition: instructions.hh:9505
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst)
Definition: decoder.cc:9121
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F16
GPUStaticInst * decode_OP_VOP1__V_SQRT_F16(MachInst)
Definition: decoder.cc:11550
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9381
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:12730
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I16
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:4109
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U32
GPUStaticInst * decode_OP_VOP2__V_MAX_U32(MachInst)
Definition: decoder.cc:3935
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_O
Definition: instructions.hh:41615
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32
Definition: instructions.hh:18689
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:12238
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:6415
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I16(MachInst)
Definition: decoder.cc:5287
gem5::VegaISA::Inst_SOPC__S_CMP_GT_U32
Definition: instructions.hh:4103
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16
Definition: instructions.hh:14779
gem5::VegaISA::Inst_VOP3__V_RCP_IFLAG_F32
Definition: instructions.hh:26799
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:6199
gem5::VegaISA::Inst_VOP3__V_CVT_F64_U32
Definition: instructions.hh:26383
gem5::VegaISA::Inst_VOP3__V_MIN_F16
Definition: instructions.hh:25511
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8688
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:37471
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F16(MachInst)
Definition: decoder.cc:4043
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F16(MachInst)
Definition: decoder.cc:11746
gem5::VegaISA::Inst_VOP1__V_RNDNE_F32
Definition: instructions.hh:9057
gem5::VegaISA::Inst_VOP3__V_LDEXP_F16
Definition: instructions.hh:25681
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:5773
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:4681
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:12232
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:4891
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64
Definition: instructions.hh:23347
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst)
Definition: decoder.cc:11044
gem5::VegaISA::Inst_DS__DS_WRITE_B16
Definition: instructions.hh:31793
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD3_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD3_U32(MachInst)
Definition: decoder.cc:6937
gem5::VegaISA::Decoder::decode
GPUStaticInst * decode(MachInst mach_inst)
Definition: decoder.cc:3712
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8584
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_O
Definition: instructions.hh:41543
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B32
Definition: instructions.hh:34641
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB
Definition: instructions.hh:5995
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:11836
gem5::VegaISA::Inst_SOP1__S_GETPC_B64
Definition: instructions.hh:3145
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst)
Definition: decoder.cc:9243
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN_I16(MachInst)
Definition: decoder.cc:6097
gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64
Definition: instructions.hh:3463
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F16
Definition: instructions.hh:17873
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32
Definition: instructions.hh:18995
gem5::VegaISA::Inst_VOP1__V_SQRT_F16
Definition: instructions.hh:9981
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD
Definition: instructions.hh:42095
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9985
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst)
Definition: decoder.cc:9048
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64
Definition: instructions.hh:13895
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:4759
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:38321
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK_SGN
Definition: instructions.hh:38619
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F64
GPUStaticInst * decode_OP_VOP1__V_SQRT_F64(MachInst)
Definition: decoder.cc:11429
gem5::VegaISA::Inst_VOP3__V_ADD_F16
Definition: instructions.hh:25069
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F64
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F64(MachInst)
Definition: decoder.cc:6259
gem5::VegaISA::Inst_VOP1__V_CEIL_F64
Definition: instructions.hh:8865
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U32
Definition: instructions.hh:34491
gem5::VegaISA::Inst_SOP1__S_BITSET1_B32
Definition: instructions.hh:3081
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_F32(MachInst)
Definition: decoder.cc:7980
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst)
Definition: decoder.cc:7015
gem5::VegaISA::Inst_VOPC__V_CMP_U_F32
Definition: instructions.hh:12025
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U16
Definition: instructions.hh:25341
gem5::VegaISA::Decoder::subDecode_OP_MIMG
GPUStaticInst * subDecode_OP_MIMG(MachInst)
Definition: decoder.cc:3837
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32
Definition: instructions.hh:15935
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:9678
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:12124
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_I32(MachInst)
Definition: decoder.cc:4524
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MULK_I32
GPUStaticInst * decode_OP_SOPK__S_MULK_I32(MachInst)
Definition: decoder.cc:4590
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_U32
GPUStaticInst * decode_OPU_VOP3__V_BFE_U32(MachInst)
Definition: decoder.cc:6595
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_O
Definition: instructions.hh:40931
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8228
gem5::VegaISA::Inst_DS__DS_WRITE_B128
Definition: instructions.hh:35617
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F16(MachInst)
Definition: decoder.cc:6799
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8682
gem5::VegaISA::InstFormat::iFmt_VOP3A
InFmt_VOP3A iFmt_VOP3A
Definition: gpu_decoder.hh:1925
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:4025
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:11501
gem5::VegaISA::Inst_VOP3__V_MQSAD_U32_U8
Definition: instructions.hh:29453
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U32(MachInst)
Definition: decoder.cc:6655
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_I32
GPUStaticInst * decode_OP_VOP1__V_FFBH_I32(MachInst)
Definition: decoder.cc:11471
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U32
Definition: instructions.hh:31827
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B64(MachInst)
Definition: decoder.cc:7660
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32
Definition: instructions.hh:22225
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:11740
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:4807
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:12826
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B64(MachInst)
Definition: decoder.cc:7812
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP
Definition: instructions.hh:38763
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32
Definition: instructions.hh:19369
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:12316
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:4981
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:5173
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I64(MachInst)
Definition: decoder.cc:8083
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_XOR
Definition: instructions.hh:39245
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst)
Definition: decoder.cc:11128
gem5::VegaISA::Inst_VOP3__V_ADD_LSHL_U32
Definition: instructions.hh:29601
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:5149
gem5::VegaISA::InFmt_SOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1759
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:5443
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8197
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst)
Definition: decoder.cc:8964
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:5179
gem5::VegaISA::Inst_SOP1__S_BREV_B64
Definition: instructions.hh:2537
gem5::VegaISA::Inst_VOP3__V_MAX_I16
Definition: instructions.hh:25579
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10303
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4
Definition: instructions.hh:40499
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32
Definition: instructions.hh:12535
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B64(MachInst)
Definition: decoder.cc:7806
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL
Definition: instructions.hh:41435
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8179
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:4783
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:4771
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32
Definition: instructions.hh:11923
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_BYTE
Definition: instructions.hh:36639
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:12424
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_BARRIER
GPUStaticInst * decode_OP_DS__DS_GWS_BARRIER(MachInst)
Definition: decoder.cc:8016
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:12820
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BRANCH
GPUStaticInst * decode_OP_SOPP__S_BRANCH(MachInst)
Definition: decoder.cc:11002
gem5::VegaISA::Inst_SOP2__S_RFE_RESTORE_B64
Definition: instructions.hh:1507
gem5::VegaISA::Inst_SOPC__S_CMP_GE_I32
Definition: instructions.hh:3943
gem5::VegaISA::Inst_VOP3__V_ALIGNBIT_B32
Definition: instructions.hh:28547
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F32(MachInst)
Definition: decoder.cc:7480
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
Definition: instructions.hh:5271
gem5::VegaISA::Inst_SMEM__S_MEMREALTIME
Definition: instructions.hh:6109
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F32
GPUStaticInst * decode_OPU_VOP3__V_MED3_F32(MachInst)
Definition: decoder.cc:6679
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10212
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U64
Definition: instructions.hh:35343
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst)
Definition: decoder.cc:7986
gem5::VegaISA::Inst_VOP3__V_MAX_F16
Definition: instructions.hh:25477
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFREV_B32
GPUStaticInst * decode_OPU_VOP3__V_BFREV_B32(MachInst)
Definition: decoder.cc:6367
gem5::VegaISA::InstFormat::iFmt_SOPK
InFmt_SOPK iFmt_SOPK
Definition: gpu_decoder.hh:1920
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F32
Definition: instructions.hh:29123
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64
Definition: instructions.hh:23789
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:11574
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8658
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:12430
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F16
Definition: instructions.hh:11583
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32
Definition: instructions.hh:19573
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B64(MachInst)
Definition: decoder.cc:10960
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B32
GPUStaticInst * decode_OP_SOP2__S_ORN2_B32(MachInst)
Definition: decoder.cc:4295
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F32
GPUStaticInst * decode_OP_VOP2__V_MADMK_F32(MachInst)
Definition: decoder.cc:3983
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F32
GPUStaticInst * decode_OP_VOP2__V_ADD_F32(MachInst)
Definition: decoder.cc:3851
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN
Definition: instructions.hh:37111
gem5::VegaISA::Inst_DS__DS_AND_RTN_B64
Definition: instructions.hh:33861
gem5::VegaISA::Inst_VOP3__V_SIN_F32
Definition: instructions.hh:26991
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst)
Definition: decoder.cc:9249
gem5::VegaISA::Inst_SOP1__S_WQM_B32
Definition: instructions.hh:2441
gem5::VegaISA::Inst_DS__DS_APPEND
Definition: instructions.hh:35069
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I16
GPUStaticInst * decode_OP_VOP2__V_MIN_I16(MachInst)
Definition: decoder.cc:4145
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U32
Definition: instructions.hh:32065
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64
Definition: instructions.hh:16411
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CALL_B64
GPUStaticInst * decode_OP_SOPK__S_CALL_B64(MachInst)
Definition: decoder.cc:4620
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SUB
Definition: instructions.hh:39007
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9357
gem5::VegaISA::Inst_VOP3__V_CUBETC_F32
Definition: instructions.hh:28259
gem5::VegaISA::Inst_SOPK__S_GETREG_B32
Definition: instructions.hh:2153
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B
Definition: instructions.hh:39527
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOP
GPUStaticInst * decode_OPU_VOP3__V_NOP(MachInst)
Definition: decoder.cc:6109
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I16
GPUStaticInst * decode_OP_DS__DS_READ_I16(MachInst)
Definition: decoder.cc:7540
gem5::VegaISA::Inst_VOP3__V_CVT_PK_I16_I32
Definition: instructions.hh:31013
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16(MachInst)
Definition: decoder.cc:7718
gem5::VegaISA::Decoder::tableSubDecode_OP_DS
static IsaDecodeMethod tableSubDecode_OP_DS[256]
Definition: gpu_decoder.hh:63
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F16
Definition: instructions.hh:11073
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8325
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:5359
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64
Definition: instructions.hh:16445
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32
Definition: instructions.hh:12263
gem5::VegaISA::Inst_SOPK__S_MOVK_I32
Definition: instructions.hh:1609
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9816
gem5::VegaISA::Decoder::decode_OP_DS__DS_BPERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_BPERMUTE_B32(MachInst)
Definition: decoder.cc:7564
gem5::VegaISA::Inst_VOP3__V_MAC_F32
Definition: instructions.hh:24813
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:9576
gem5::VegaISA::Inst_VOPC__V_CMP_U_F16
Definition: instructions.hh:10937
gem5::VegaISA::Inst_DS__DS_ADD_U64
Definition: instructions.hh:32909
gem5::VegaISA::Inst_SOPC__S_CMP_GE_U32
Definition: instructions.hh:4135
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:5845
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9872
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B32(MachInst)
Definition: decoder.cc:7444
gem5::VegaISA::InFmt_FLAT
Definition: gpu_decoder.hh:1633
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP
Definition: instructions.hh:38547
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C
Definition: instructions.hh:40715
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:9720
gem5::VegaISA::Inst_SOP2__S_BFM_B64
Definition: instructions.hh:1235
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:12418
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:12376
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B32
Definition: instructions.hh:34671
gem5::VegaISA::InstFormat::iFmt_MUBUF
InFmt_MUBUF iFmt_MUBUF
Definition: gpu_decoder.hh:1913
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8439
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:9690
gem5::VegaISA::Inst_VOP1__V_COS_F16
Definition: instructions.hh:10365
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:6229
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B32
GPUStaticInst * decode_OP_SOP2__S_AND_B32(MachInst)
Definition: decoder.cc:4247
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F64
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F64(MachInst)
Definition: decoder.cc:7058
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:12814
gem5::VegaISA::Inst_VOP1__V_RSQ_F64
Definition: instructions.hh:9313
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U32(MachInst)
Definition: decoder.cc:7420
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B32
GPUStaticInst * decode_OP_SOP2__S_NAND_B32(MachInst)
Definition: decoder.cc:4307
gem5::VegaISA::Inst_VOP1__V_TRUNC_F64
Definition: instructions.hh:8833
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE(MachInst)
Definition: decoder.cc:10151
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F16
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F16(MachInst)
Definition: decoder.cc:11604
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_INIT
GPUStaticInst * decode_OP_DS__DS_GWS_INIT(MachInst)
Definition: decoder.cc:7992
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SAT_PK_U8_I16
GPUStaticInst * decode_OP_VOP1__V_SAT_PK_U8_I16(MachInst)
Definition: decoder.cc:11654
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_I32(MachInst)
Definition: decoder.cc:4391
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:12646
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8499
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64
Definition: instructions.hh:20253
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F32(MachInst)
Definition: decoder.cc:11938
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32
Definition: instructions.hh:30435
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F16
GPUStaticInst * decode_OPU_VOP3__V_SUB_F16(MachInst)
Definition: decoder.cc:6001
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCNZ
Definition: instructions.hh:4699
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX_I32(MachInst)
Definition: decoder.cc:5899
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE1
Definition: instructions.hh:26255
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I64
GPUStaticInst * decode_OP_DS__DS_MAX_I64(MachInst)
Definition: decoder.cc:7606
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst)
Definition: decoder.cc:8928
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:9914
gem5::VegaISA::Inst_VOP3__V_INTERP_P1_F32
Definition: instructions.hh:30023
gem5::VegaISA::Inst_VOP1__V_NOP
Definition: instructions.hh:8101
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_I16(MachInst)
Definition: decoder.cc:12877
gem5::VegaISA::Inst_VOPC__V_CMP_T_I64
Definition: instructions.hh:16343
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ
Definition: instructions.hh:40895
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:4843
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64
Definition: instructions.hh:17091
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8
GPUStaticInst * decode_OP_DS__DS_WRITE_B8(MachInst)
Definition: decoder.cc:7366
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F16
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F16(MachInst)
Definition: decoder.cc:6103
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8598
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B32
GPUStaticInst * decode_OP_DS__DS_READ_B32(MachInst)
Definition: decoder.cc:7510
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U32
GPUStaticInst * decode_OP_DS__DS_MAX_U32(MachInst)
Definition: decoder.cc:7275
gem5::VegaISA::Inst_VOP3__V_LOG_LEGACY_F32
Definition: instructions.hh:28011
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst)
Definition: decoder.cc:9195
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64
Definition: instructions.hh:23517
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_F64(MachInst)
Definition: decoder.cc:7678
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SWAPPC_B64
GPUStaticInst * decode_OP_SOP1__S_SWAPPC_B64(MachInst)
Definition: decoder.cc:10721
gem5::VegaISA::Inst_VOP3__V_MED3_U32
Definition: instructions.hh:28907
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_U32(MachInst)
Definition: decoder.cc:10936
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F32(MachInst)
Definition: decoder.cc:7486
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
Definition: instructions.hh:37867
gem5::VegaISA::Inst_VOP2__V_MUL_F32
Definition: instructions.hh:6379
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
Definition: instructions.hh:40427
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F64
GPUStaticInst * decode_OP_VOP1__V_RSQ_F64(MachInst)
Definition: decoder.cc:11417
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD
Definition: instructions.hh:42321
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F16
Definition: instructions.hh:18417
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64
Definition: instructions.hh:3687
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:4969
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:10096
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64
Definition: instructions.hh:13521
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16
Definition: instructions.hh:21715
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst)
Definition: decoder.cc:8367
gem5::VegaISA::Inst_VOP3__V_RNDNE_F16
Definition: instructions.hh:27851
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64
Definition: instructions.hh:2793
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC
Definition: instructions.hh:37363
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:5689
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U64
Definition: instructions.hh:33555

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