cpu.hh

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#ifndef __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
 
#include "cpu/base.hh"
#include "iris/detail/IrisInterface.h"
#include "params/IrisBaseCPU.hh"
#include "systemc/ext/core/sc_attr.hh"
#include "systemc/ext/core/sc_event.hh"
#include "systemc/ext/core/sc_module.hh"
 
namespace gem5
{
 
namespace Iris
{
 
class ThreadContext;
 
// The base interface of the EVS used by gem5 BaseCPU below.
class BaseCpuEvs
{
  public:
    virtual void sendFunc(PacketPtr pkt) = 0;
    virtual void setClkPeriod(Tick clk_period) = 0;
    virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
    virtual void setCluster(SimObject *cluster) = 0;
    virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
};
 
// This CPU class adds some mechanisms which help attach the gem5 and fast
// model CPUs to each other. It acts as a base class for the gem5 CPU, and
// holds a pointer to the EVS. It also has some methods for setting up some
// attributes in the fast model CPU to control its clock rate.
class BaseCPU : public gem5::BaseCPU
{
  public:
    BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs);
    virtual ~BaseCPU();
 
    Port &
    getDataPort() override
    {
        panic("%s not implemented.", __FUNCTION__);
    }
 
    Port &
    getInstPort() override
    {
        panic("%s not implemented.", __FUNCTION__);
    }
 
    void
    wakeup(ThreadID tid) override
    {
        auto *tc = threadContexts.at(tid);
        if (tc->status() == gem5::ThreadContext::Suspended)
            tc->activate();
    }
 
    Counter totalInsts() const override;
    Counter totalOps() const override { return totalInsts(); }
 
    virtual void
    setResetAddr(Addr addr, bool secure = false)
    {
        panic("%s not implemented.", __FUNCTION__);
    }
 
  protected:
    sc_core::sc_module *evs;
    // Hold casted pointer to *evs.
    Iris::BaseCpuEvs *evs_base_cpu;
 
  protected:
    friend ThreadContext;
 
    void
    clockPeriodUpdated() override
    {
        evs_base_cpu->setClkPeriod(clockPeriod());
    }
 
    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
};
 
// This class specializes the one above and sets up ThreadContexts based on
// its template parameters. These ThreadContexts provide the standard gem5
// interface and translate those accesses to use the Iris API to access that
// state in the target context.
template <class TC>
class CPU : public Iris::BaseCPU
{
  public:
    CPU(const IrisBaseCPUParams &params,
            iris::IrisConnectionInterface *iris_if) :
        BaseCPU(params, params.evs)
    {
        const std::string parent_path = evs->name();
        System *sys = params.system;
 
        int thread_id = 0;
        for (const std::string &sub_path: params.thread_paths) {
            std::string path = parent_path + "." + sub_path;
            auto id = thread_id++;
            auto *tc = new TC(this, id, sys, params.mmu,
                    params.isa[id], iris_if, path);
            threadContexts.push_back(tc);
        }
    }
};
 
} // namespace Iris
} // namespace gem5
 
#endif // __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__