gem5  v22.0.0.2
remote_gdb.cc
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1 /*
2  * Copyright (c) 2021 Huawei International
3  * Copyright 2015 LabWare
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5  * Copyright (c) 2010 ARM Limited
6  * Copyright (c) 2020 Barkhausen Institut
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45 
46 /*
47  * Copyright (c) 1990, 1993 The Regents of the University of California
48  * All rights reserved
49  *
50  * This software was developed by the Computer Systems Engineering group
51  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
52  * contributed to Berkeley.
53  *
54  * All advertising materials mentioning features or use of this software
55  * must display the following acknowledgement:
56  * This product includes software developed by the University of
57  * California, Lawrence Berkeley Laboratories.
58  *
59  * Redistribution and use in source and binary forms, with or without
60  * modification, are permitted provided that the following conditions
61  * are met:
62  * 1. Redistributions of source code must retain the above copyright
63  * notice, this list of conditions and the following disclaimer.
64  * 2. Redistributions in binary form must reproduce the above copyright
65  * notice, this list of conditions and the following disclaimer in the
66  * documentation and/or other materials provided with the distribution.
67  * 3. All advertising materials mentioning features or use of this software
68  * must display the following acknowledgement:
69  * This product includes software developed by the University of
70  * California, Berkeley and its contributors.
71  * 4. Neither the name of the University nor the names of its contributors
72  * may be used to endorse or promote products derived from this software
73  * without specific prior written permission.
74  *
75  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
76  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
77  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
78  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
79  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
80  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
81  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
82  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
83  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
84  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85  * SUCH DAMAGE.
86  *
87  * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
88  */
89 
90 /*-
91  * Copyright (c) 2001 The NetBSD Foundation, Inc.
92  * All rights reserved.
93  *
94  * This code is derived from software contributed to The NetBSD Foundation
95  * by Jason R. Thorpe.
96  *
97  * Redistribution and use in source and binary forms, with or without
98  * modification, are permitted provided that the following conditions
99  * are met:
100  * 1. Redistributions of source code must retain the above copyright
101  * notice, this list of conditions and the following disclaimer.
102  * 2. Redistributions in binary form must reproduce the above copyright
103  * notice, this list of conditions and the following disclaimer in the
104  * documentation and/or other materials provided with the distribution.
105  * 3. All advertising materials mentioning features or use of this software
106  * must display the following acknowledgement:
107  * This product includes software developed by the NetBSD
108  * Foundation, Inc. and its contributors.
109  * 4. Neither the name of The NetBSD Foundation nor the names of its
110  * contributors may be used to endorse or promote products derived
111  * from this software without specific prior written permission.
112  *
113  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
114  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
115  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
116  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
117  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
118  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
119  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
120  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
121  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
122  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
123  * POSSIBILITY OF SUCH DAMAGE.
124  */
125 
126 /*
127  * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
128  *
129  * Taken from NetBSD
130  *
131  * "Stub" to allow remote cpu to debug over a serial line using gdb.
132  */
133 
134 #include "arch/riscv/remote_gdb.hh"
135 
136 #include <string>
137 
138 #include "arch/riscv/gdb-xml/gdb_xml_riscv_cpu.hh"
139 #include "arch/riscv/gdb-xml/gdb_xml_riscv_csr.hh"
140 #include "arch/riscv/gdb-xml/gdb_xml_riscv_fpu.hh"
141 #include "arch/riscv/gdb-xml/gdb_xml_riscv_target.hh"
142 #include "arch/riscv/mmu.hh"
143 #include "arch/riscv/pagetable_walker.hh"
144 #include "arch/riscv/regs/float.hh"
145 #include "arch/riscv/regs/int.hh"
146 #include "arch/riscv/regs/misc.hh"
147 #include "arch/riscv/tlb.hh"
148 #include "cpu/thread_state.hh"
149 #include "debug/GDBAcc.hh"
150 #include "mem/page_table.hh"
151 #include "sim/full_system.hh"
152 
153 namespace gem5
154 {
155 
156 using namespace RiscvISA;
157 
158 RemoteGDB::RemoteGDB(System *_system, int _port)
159  : BaseRemoteGDB(_system, _port), regCache(this)
160 {
161 }
162 
163 bool
164 RemoteGDB::acc(Addr va, size_t len)
165 {
166  if (FullSystem)
167  {
168  MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
169  unsigned logBytes;
170  Addr paddr = va;
171 
172  PrivilegeMode pmode = mmu->getMemPriv(context(), BaseMMU::Read);
173  SATP satp = context()->readMiscReg(MISCREG_SATP);
174  if (pmode != PrivilegeMode::PRV_M &&
175  satp.mode != AddrXlateMode::BARE) {
176  Walker *walker = mmu->getDataWalker();
177  Fault fault = walker->startFunctional(
178  context(), paddr, logBytes, BaseMMU::Read);
179  if (fault != NoFault)
180  return false;
181  }
182  return true;
183  }
184 
185  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
186 }
187 
188 void
189 RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
190 {
191  DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
192 
193  // General registers
194  for (int i = 0; i < NumIntArchRegs; i++)
195  {
196  r.gpr[i] = context->readIntReg(i);
197  }
198  r.pc = context->pcState().instAddr();
199 
200  // Floating point registers
201  for (int i = 0; i < NumFloatRegs; i++)
202  r.fpu[i] = context->readFloatReg(i);
203  r.fflags = context->readMiscRegNoEffect(
204  CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
205  r.frm = context->readMiscRegNoEffect(
206  CSRData.at(CSR_FRM).physIndex) & CSRMasks.at(CSR_FRM);
207  r.fcsr = context->readMiscRegNoEffect(
208  CSRData.at(CSR_FCSR).physIndex) & CSRMasks.at(CSR_FCSR);
209 
210  // CSR registers
211  r.cycle = context->readMiscRegNoEffect(
212  CSRData.at(CSR_CYCLE).physIndex);
213  r.time = context->readMiscRegNoEffect(
214  CSRData.at(CSR_TIME).physIndex);
215 
216  // U mode CSR
217  r.ustatus = context->readMiscRegNoEffect(
218  CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS);
219  r.uie = context->readMiscReg(
220  CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE);
221  r.utvec = context->readMiscRegNoEffect(
222  CSRData.at(CSR_UTVEC).physIndex);
223  r.uscratch = context->readMiscRegNoEffect(
224  CSRData.at(CSR_USCRATCH).physIndex);
225  r.uepc = context->readMiscRegNoEffect(
226  CSRData.at(CSR_UEPC).physIndex);
227  r.ucause = context->readMiscRegNoEffect(
228  CSRData.at(CSR_UCAUSE).physIndex);
229  r.utval = context->readMiscRegNoEffect(
230  CSRData.at(CSR_UTVAL).physIndex);
231  r.uip = context->readMiscReg(
232  CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP);
233 
234  // S mode CSR
235  r.sstatus = context->readMiscRegNoEffect(
236  CSRData.at(CSR_SSTATUS).physIndex) & CSRMasks.at(CSR_SSTATUS);
237  r.sedeleg = context->readMiscRegNoEffect(
238  CSRData.at(CSR_SEDELEG).physIndex);
239  r.sideleg = context->readMiscRegNoEffect(
240  CSRData.at(CSR_SIDELEG).physIndex);
241  r.sie = context->readMiscReg(
242  CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE);
243  r.stvec = context->readMiscRegNoEffect(
244  CSRData.at(CSR_STVEC).physIndex);
245  r.scounteren = context->readMiscRegNoEffect(
246  CSRData.at(CSR_SCOUNTEREN).physIndex);
247  r.sscratch = context->readMiscRegNoEffect(
248  CSRData.at(CSR_SSCRATCH).physIndex);
249  r.sepc = context->readMiscRegNoEffect(
250  CSRData.at(CSR_SEPC).physIndex);
251  r.scause = context->readMiscRegNoEffect(
252  CSRData.at(CSR_SCAUSE).physIndex);
253  r.stval = context->readMiscRegNoEffect(
254  CSRData.at(CSR_STVAL).physIndex);
255  r.sip = context->readMiscReg(
256  CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP);
257  r.satp = context->readMiscRegNoEffect(
258  CSRData.at(CSR_SATP).physIndex);
259 
260  // M mode CSR
261  r.mvendorid = context->readMiscRegNoEffect(
262  CSRData.at(CSR_MVENDORID).physIndex);
263  r.marchid = context->readMiscRegNoEffect(
264  CSRData.at(CSR_MARCHID).physIndex);
265  r.mimpid = context->readMiscRegNoEffect(
266  CSRData.at(CSR_MIMPID).physIndex);
267  r.mhartid = context->readMiscRegNoEffect(
268  CSRData.at(CSR_MHARTID).physIndex);
269  r.mstatus = context->readMiscRegNoEffect(
270  CSRData.at(CSR_MSTATUS).physIndex) & CSRMasks.at(CSR_MSTATUS);
271  r.misa = context->readMiscRegNoEffect(
272  CSRData.at(CSR_MISA).physIndex) & CSRMasks.at(CSR_MISA);
273  r.medeleg = context->readMiscRegNoEffect(
274  CSRData.at(CSR_MEDELEG).physIndex);
275  r.mideleg = context->readMiscRegNoEffect(
276  CSRData.at(CSR_MIDELEG).physIndex);
277  r.mie = context->readMiscReg(
278  CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE);
279  r.mtvec = context->readMiscRegNoEffect(
280  CSRData.at(CSR_MTVEC).physIndex);
281  r.mcounteren = context->readMiscRegNoEffect(
282  CSRData.at(CSR_MCOUNTEREN).physIndex);
283  r.mscratch = context->readMiscRegNoEffect(
284  CSRData.at(CSR_MSCRATCH).physIndex);
285  r.mepc = context->readMiscRegNoEffect(
286  CSRData.at(CSR_MEPC).physIndex);
287  r.mcause = context->readMiscRegNoEffect(
288  CSRData.at(CSR_MCAUSE).physIndex);
289  r.mtval = context->readMiscRegNoEffect(
290  CSRData.at(CSR_MTVAL).physIndex);
291  r.mip = context->readMiscReg(
292  CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP);
293 
294  // H mode CSR (to be implemented)
295 }
296 
297 void
298 RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
299 {
300  // NOTE: no error will be reported for attempting to set masked bits.
301  RegVal oldVal;
302  int mask;
303  RegVal newVal;
304 
305  DPRINTF(GDBAcc, "setregs in remotegdb \n");
306  for (int i = 0; i < NumIntArchRegs; i++)
307  context->setIntReg(i, r.gpr[i]);
308  context->pcState(r.pc);
309 
310  // Floating point registers
311  for (int i = 0; i < NumFloatRegs; i++)
312  context->setFloatReg(i, r.fpu[i]);
313 
314  oldVal = context->readMiscRegNoEffect(
315  CSRData.at(CSR_FFLAGS).physIndex);
316  mask = CSRMasks.at(CSR_FFLAGS);
317  newVal = (oldVal & ~mask) | (r.fflags & mask);
318  context->setMiscRegNoEffect(
319  CSRData.at(CSR_FFLAGS).physIndex, newVal);
320 
321  oldVal = context->readMiscRegNoEffect(
322  CSRData.at(CSR_FRM).physIndex);
323  mask = CSRMasks.at(CSR_FRM);
324  newVal = (oldVal & ~mask) | (r.frm & mask);
325  context->setMiscRegNoEffect(
326  CSRData.at(CSR_FRM).physIndex, newVal);
327 
328  oldVal = context->readMiscRegNoEffect(
329  CSRData.at(CSR_FCSR).physIndex);
330  mask = CSRMasks.at(CSR_FCSR);
331  newVal = (oldVal & ~mask) | (r.fcsr & mask);
332  context->setMiscRegNoEffect(
333  CSRData.at(CSR_FCSR).physIndex, newVal);
334 
335  // CSR registers
336  context->setMiscRegNoEffect(
337  CSRData.at(CSR_CYCLE).physIndex, r.cycle);
338  context->setMiscRegNoEffect(
339  CSRData.at(CSR_TIME).physIndex, r.time);
340 
341  // U mode CSR
342  oldVal = context->readMiscRegNoEffect(
343  CSRData.at(CSR_USTATUS).physIndex);
344  mask = CSRMasks.at(CSR_USTATUS);
345  newVal = (oldVal & ~mask) | (r.ustatus & mask);
346  context->setMiscRegNoEffect(
347  CSRData.at(CSR_USTATUS).physIndex, newVal);
348  oldVal = context->readMiscReg(
349  CSRData.at(CSR_UIE).physIndex);
350  mask = CSRMasks.at(CSR_UIE);
351  newVal = (oldVal & ~mask) | (r.uie & mask);
352  context->setMiscReg(
353  CSRData.at(CSR_UIE).physIndex, newVal);
354  context->setMiscRegNoEffect(
355  CSRData.at(CSR_UTVEC).physIndex, r.utvec);
356  context->setMiscRegNoEffect(
357  CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
358  context->setMiscRegNoEffect(
359  CSRData.at(CSR_UEPC).physIndex, r.uepc);
360  context->setMiscRegNoEffect(
361  CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
362  context->setMiscRegNoEffect(
363  CSRData.at(CSR_UTVAL).physIndex, r.utval);
364  oldVal = context->readMiscReg(
365  CSRData.at(CSR_UIP).physIndex);
366  mask = CSRMasks.at(CSR_UIP);
367  newVal = (oldVal & ~mask) | (r.uip & mask);
368  context->setMiscReg(
369  CSRData.at(CSR_UIP).physIndex, newVal);
370 
371  // S mode CSR
372  oldVal = context->readMiscRegNoEffect(
373  CSRData.at(CSR_SSTATUS).physIndex);
374  mask = CSRMasks.at(CSR_SSTATUS);
375  newVal = (oldVal & ~mask) | (r.sstatus & mask);
376  context->setMiscRegNoEffect(
377  CSRData.at(CSR_SSTATUS).physIndex, newVal);
378  context->setMiscRegNoEffect(
379  CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
380  context->setMiscRegNoEffect(
381  CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
382  oldVal = context->readMiscReg(
383  CSRData.at(CSR_SIE).physIndex);
384  mask = CSRMasks.at(CSR_SIE);
385  newVal = (oldVal & ~mask) | (r.sie & mask);
386  context->setMiscReg(
387  CSRData.at(CSR_SIE).physIndex, newVal);
388  context->setMiscRegNoEffect(
389  CSRData.at(CSR_STVEC).physIndex, r.stvec);
390  context->setMiscRegNoEffect(
391  CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
392  context->setMiscRegNoEffect(
393  CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
394  context->setMiscRegNoEffect(
395  CSRData.at(CSR_SEPC).physIndex, r.sepc);
396  context->setMiscRegNoEffect(
397  CSRData.at(CSR_SCAUSE).physIndex, r.scause);
398  context->setMiscRegNoEffect(
399  CSRData.at(CSR_STVAL).physIndex, r.stval);
400  oldVal = context->readMiscReg(
401  CSRData.at(CSR_SIP).physIndex);
402  mask = CSRMasks.at(CSR_SIP);
403  newVal = (oldVal & ~mask) | (r.sip & mask);
404  context->setMiscReg(
405  CSRData.at(CSR_SIP).physIndex, newVal);
406  context->setMiscRegNoEffect(
407  CSRData.at(CSR_SATP).physIndex, r.satp);
408 
409  // M mode CSR
410  context->setMiscRegNoEffect(
411  CSRData.at(CSR_MVENDORID).physIndex, r.mvendorid);
412  context->setMiscRegNoEffect(
413  CSRData.at(CSR_MARCHID).physIndex, r.marchid);
414  context->setMiscRegNoEffect(
415  CSRData.at(CSR_MIMPID).physIndex, r.mimpid);
416  context->setMiscRegNoEffect(
417  CSRData.at(CSR_MHARTID).physIndex, r.mhartid);
418  oldVal = context->readMiscRegNoEffect(
419  CSRData.at(CSR_MSTATUS).physIndex);
420  mask = CSRMasks.at(CSR_MSTATUS);
421  newVal = (oldVal & ~mask) | (r.mstatus & mask);
422  context->setMiscRegNoEffect(
423  CSRData.at(CSR_MSTATUS).physIndex, newVal);
424  oldVal = context->readMiscRegNoEffect(
425  CSRData.at(CSR_MISA).physIndex);
426  mask = CSRMasks.at(CSR_MISA);
427  newVal = (oldVal & ~mask) | (r.misa & mask);
428  context->setMiscRegNoEffect(
429  CSRData.at(CSR_MISA).physIndex, newVal);
430  context->setMiscRegNoEffect(
431  CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
432  context->setMiscRegNoEffect(
433  CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
434  oldVal = context->readMiscReg(
435  CSRData.at(CSR_MIE).physIndex);
436  mask = CSRMasks.at(CSR_MIE);
437  newVal = (oldVal & ~mask) | (r.mie & mask);
438  context->setMiscReg(
439  CSRData.at(CSR_MIE).physIndex, newVal);
440  context->setMiscRegNoEffect(
441  CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
442  context->setMiscRegNoEffect(
443  CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
444  context->setMiscRegNoEffect(
445  CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
446  context->setMiscRegNoEffect(
447  CSRData.at(CSR_MEPC).physIndex, r.mepc);
448  context->setMiscRegNoEffect(
449  CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
450  context->setMiscRegNoEffect(
451  CSRData.at(CSR_MTVAL).physIndex, r.mtval);
452  oldVal = context->readMiscReg(
453  CSRData.at(CSR_MIP).physIndex);
454  mask = CSRMasks.at(CSR_MIP);
455  newVal = (oldVal & ~mask) | (r.mip & mask);
456  context->setMiscReg(
457  CSRData.at(CSR_MIP).physIndex, newVal);
458 
459  // H mode CSR (to be implemented)
460 }
461 
462 bool
463 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
464 {
471 #define GDB_XML(x, s) \
472  { \
473  x, std::string(reinterpret_cast<const char *>(Blobs::s), \
474  Blobs::s##_len) \
475  }
476  static const std::map<std::string, std::string> annexMap{
477  GDB_XML("target.xml", gdb_xml_riscv_target),
478  GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_cpu),
479  GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_fpu),
480  GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_csr)};
481 #undef GDB_XML
482  auto it = annexMap.find(annex);
483  if (it == annexMap.end())
484  return false;
485  output = it->second;
486  return true;
487 }
488 
489 BaseGdbRegCache *
490 RemoteGDB::gdbRegs()
491 {
492  return &regCache;
493 }
494 
495 } // namespace gem5
gem5::RiscvISA::CSR_MSCRATCH
@ CSR_MSCRATCH
Definition: misc.hh:274
gem5::RiscvISA::CSR_MIDELEG
@ CSR_MIDELEG
Definition: misc.hh:270
gem5::RiscvISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, int _port)
gem5::RiscvISA::CSR_UTVAL
@ CSR_UTVAL
Definition: misc.hh:211
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
thread_state.hh
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::RiscvISA::CSR_SIDELEG
@ CSR_SIDELEG
Definition: misc.hh:252
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:57
gem5::RiscvISA::CSR_UIP
@ CSR_UIP
Definition: misc.hh:212
gem5::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const
Definition: thread_context.hh:210
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: misc.hh:376
gem5::MipsISA::NumIntArchRegs
const int NumIntArchRegs
Definition: int.hh:40
gem5::RiscvISA::CSR_SIP
@ CSR_SIP
Definition: misc.hh:260
gem5::RiscvISA::CSR_USCRATCH
@ CSR_USCRATCH
Definition: misc.hh:208
gem5::PowerISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs()
gem5::output
static void output(const char *filename)
Definition: debug.cc:60
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::RiscvISA::CSR_MARCHID
@ CSR_MARCHID
Definition: misc.hh:264
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:53
gem5::RiscvISA::CSR_UCAUSE
@ CSR_UCAUSE
Definition: misc.hh:210
gem5::MipsISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:45
gem5::EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:133
float.hh
gem5::RiscvISA::CSR_MCOUNTEREN
@ CSR_MCOUNTEREN
Definition: misc.hh:273
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::RiscvISA::CSR_SCOUNTEREN
@ CSR_SCOUNTEREN
Definition: misc.hh:255
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
GDB_XML
#define GDB_XML(x, s)
gem5::BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition: remote_gdb.hh:85
gem5::RiscvISA::CSR_SEDELEG
@ CSR_SEDELEG
Definition: misc.hh:251
gem5::RiscvISA::CSR_FFLAGS
@ CSR_FFLAGS
Definition: misc.hh:213
misc.hh
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::RiscvISA::CSR_MIMPID
@ CSR_MIMPID
Definition: misc.hh:265
gem5::RiscvISA::CSR_UTVEC
@ CSR_UTVEC
Definition: misc.hh:207
gem5::RiscvISA::CSR_FCSR
@ CSR_FCSR
Definition: misc.hh:215
gem5::RiscvISA::CSR_MCAUSE
@ CSR_MCAUSE
Definition: misc.hh:276
gem5::RiscvISA::CSR_SEPC
@ CSR_SEPC
Definition: misc.hh:257
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::RiscvISA::CSR_USTATUS
@ CSR_USTATUS
Definition: misc.hh:205
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
tlb.hh
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
gem5::RiscvISA::CSR_MTVAL
@ CSR_MTVAL
Definition: misc.hh:277
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::RiscvISA::CSR_MIE
@ CSR_MIE
Definition: misc.hh:271
gem5::RiscvISA::CSR_SCAUSE
@ CSR_SCAUSE
Definition: misc.hh:258
gem5::RiscvISA::CSR_SSCRATCH
@ CSR_SSCRATCH
Definition: misc.hh:256
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:185
gem5::RiscvISA::CSR_MSTATUS
@ CSR_MSTATUS
Definition: misc.hh:267
gem5::RiscvISA::CSR_FRM
@ CSR_FRM
Definition: misc.hh:214
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:180
len
uint16_t len
Definition: helpers.cc:62
gem5::RiscvISA::CSR_SIE
@ CSR_SIE
Definition: misc.hh:253
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::RiscvISA::CSR_UIE
@ CSR_UIE
Definition: misc.hh:206
gem5::RiscvISA::CSR_SATP
@ CSR_SATP
Definition: misc.hh:261
gem5::RiscvISA::CSR_STVAL
@ CSR_STVAL
Definition: misc.hh:259
gem5::PowerISA::RemoteGDB::acc
bool acc(Addr addr, size_t len)
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::RemoteGDB::getXferFeaturesRead
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
gem5::RiscvISA::CSR_TIME
@ CSR_TIME
Definition: misc.hh:217
gem5::RiscvISA::CSR_MTVEC
@ CSR_MTVEC
Definition: misc.hh:272
gem5::RiscvISA::CSR_STVEC
@ CSR_STVEC
Definition: misc.hh:254
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
full_system.hh
gem5::RiscvISA::CSR_CYCLE
@ CSR_CYCLE
Definition: misc.hh:216
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::RiscvISA::CSR_MEDELEG
@ CSR_MEDELEG
Definition: misc.hh:269
remote_gdb.hh
mmu.hh
gem5::RiscvISA::CSR_SSTATUS
@ CSR_SSTATUS
Definition: misc.hh:250
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::RiscvISA::CSR_MVENDORID
@ CSR_MVENDORID
Definition: misc.hh:263
gem5::BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:395
gem5::RiscvISA::CSR_MISA
@ CSR_MISA
Definition: misc.hh:268
gem5::RiscvISA::CSRMasks
const std::map< int, RegVal > CSRMasks
Definition: misc.hh:657
gem5::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:247
gem5::RiscvISA::CSR_MEPC
@ CSR_MEPC
Definition: misc.hh:275
gem5::RiscvISA::CSR_MHARTID
@ CSR_MHARTID
Definition: misc.hh:266
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::CSR_UEPC
@ CSR_UEPC
Definition: misc.hh:209
int.hh
gem5::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:241
gem5::RiscvISA::CSR_MIP
@ CSR_MIP
Definition: misc.hh:278
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
pagetable_walker.hh
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