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gem5
v22.0.0.2
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#include <tlbi_op.hh>
Public Member Functions | |
| TLBIMVA (ExceptionLevel _targetEL, bool _secure, Addr _addr, uint16_t _asid) | |
| void | operator() (ThreadContext *tc) override |
Public Member Functions inherited from gem5::ArmISA::TLBIOp | |
| TLBIOp (ExceptionLevel _targetEL, bool _secure) | |
| virtual | ~TLBIOp () |
| void | broadcast (ThreadContext *tc) |
| Broadcast the TLB Invalidate operation to all TLBs in the Arm system. More... | |
| virtual bool | stage1Flush () const |
| Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. More... | |
| virtual bool | stage2Flush () const |
| Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. More... | |
Public Attributes | |
| Addr | addr |
| uint16_t | asid |
| bool | inHost |
Public Attributes inherited from gem5::ArmISA::TLBIOp | |
| bool | secureLookup |
| ExceptionLevel | targetEL |
TLB Invalidate by VA.
Definition at line 296 of file tlbi_op.hh.
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inline |
Definition at line 299 of file tlbi_op.hh.
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overridevirtual |
Reimplemented from gem5::ArmISA::TLBIOp.
Reimplemented in gem5::ArmISA::DTLBIMVA, and gem5::ArmISA::ITLBIMVA.
Definition at line 162 of file tlbi_op.cc.
References gem5::ArmISA::MMU::flushStage1(), gem5::ThreadContext::getCheckerCpuPtr(), gem5::ArmISA::getMMUPtr(), inHost, gem5::ArmISA::MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().
| Addr gem5::ArmISA::TLBIMVA::addr |
Definition at line 307 of file tlbi_op.hh.
Referenced by gem5::ArmISA::TLB::flush().
| uint16_t gem5::ArmISA::TLBIMVA::asid |
Definition at line 308 of file tlbi_op.hh.
Referenced by gem5::ArmISA::TLB::flush().
| bool gem5::ArmISA::TLBIMVA::inHost |
Definition at line 309 of file tlbi_op.hh.
Referenced by gem5::ArmISA::TLB::flush(), and operator()().