TLB Invalidate by VA, All ASID. More...
#include <tlbi_op.hh>
Inheritance diagram for gem5::ArmISA::TLBIMVAA:
Public Member Functions | |
| TLBIMVAA (ExceptionLevel _targetEL, bool _secure, Addr _addr) | |
| void | operator() (ThreadContext *tc) override |
 Public Member Functions inherited from gem5::ArmISA::TLBIOp | |
| TLBIOp (ExceptionLevel _targetEL, bool _secure) | |
| virtual | ~TLBIOp () |
| void | broadcast (ThreadContext *tc) |
| Broadcast the TLB Invalidate operation to all TLBs in the Arm system. More... | |
| virtual bool | stage1Flush () const |
| Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. More... | |
| virtual bool | stage2Flush () const |
| Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. More... | |
Public Attributes | |
| Addr | addr |
| bool | inHost |
| Public Attributes inherited from gem5::ArmISA::TLBIOp | |
| bool | secureLookup |
| ExceptionLevel | targetEL |
Detailed Description
TLB Invalidate by VA, All ASID.
Definition at line 281 of file tlbi_op.hh.
Constructor & Destructor Documentation
◆ TLBIMVAA()
|
inline |
Definition at line 284 of file tlbi_op.hh.
Member Function Documentation
◆ operator()()
|
overridevirtual |
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 149 of file tlbi_op.cc.
References gem5::ArmISA::MMU::flushStage1(), gem5::ThreadContext::getCheckerCpuPtr(), gem5::ArmISA::getMMUPtr(), inHost, gem5::ArmISA::MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().
Member Data Documentation
◆ addr
| Addr gem5::ArmISA::TLBIMVAA::addr |
Definition at line 291 of file tlbi_op.hh.
Referenced by gem5::ArmISA::TLB::flush().
◆ inHost
| bool gem5::ArmISA::TLBIMVAA::inHost |
Definition at line 292 of file tlbi_op.hh.
Referenced by gem5::ArmISA::TLB::flush(), and operator()().
The documentation for this class was generated from the following files:
- arch/arm/tlbi_op.hh
- arch/arm/tlbi_op.cc