gem5::ArmISA::WatchPoint Class Reference

#include <self_debug.hh>

Public Member Functions
	WatchPoint (MiscRegIndex ctrl_index, MiscRegIndex val_index, SelfDebug *_conf, bool lva, bool aarch32)
bool	compareAddress (ThreadContext *tc, Addr in_addr, uint8_t bas, uint8_t mask, unsigned size)
Addr	getAddrfromReg (ThreadContext *tc)
bool	isDoubleAligned (Addr addr)
void	updateControl (DBGWCR val)
bool	isEnabled (ThreadContext *tc, ExceptionLevel el, bool hmc, uint8_t ssc, uint8_t pac)
bool	test (ThreadContext *tc, Addr addr, ExceptionLevel el, bool &wrt, bool atomic, unsigned size)

Private Attributes
MiscRegIndex	ctrlRegIndex
MiscRegIndex	valRegIndex
SelfDebug *	conf
bool	enable
int	maxAddrSize

Friends
class	SelfDebug

Detailed Description

Definition at line 147 of file self_debug.hh.

Constructor & Destructor Documentation

WatchPoint()

gem5::ArmISA::WatchPoint::WatchPoint ( MiscRegIndex  ctrl_index, MiscRegIndex  val_index, SelfDebug *  _conf, bool  lva, bool  aarch32  )

inline

Definition at line 159 of file self_debug.hh.

References maxAddrSize.

Member Function Documentation

compareAddress()

bool gem5::WatchPoint::compareAddress	(	ThreadContext *	tc,
		Addr	in_addr,
		uint8_t	bas,
		uint8_t	mask,
		unsigned	size
	)

Definition at line 605 of file self_debug.cc.

References gem5::X86ISA::addr, gem5::ArmISA::bas, gem5::bits(), getAddrfromReg(), gem5::ArmISA::i, isDoubleAligned(), gem5::ArmISA::j, gem5::ArmISA::mask, maxAddrSize, and gem5::ArmISA::v.

Referenced by test().

  bool il (ThreadContext *tc) const override   uint32_t iss () const override    Public Member Functions inherited from gem5::ArmISA::ArmFault  ArmFault (ExtMachInst mach_inst=0, uint32_t _iss=0)   MiscRegIndex getSyndromeReg64 () const   MiscRegIndex getFaultAddrReg64 () const   void invoke32 (ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)   void invoke64 (ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)   void update (ThreadContext *tc)   bool isResetSPSR ()   bool vectorCatch (ThreadContext *tc, const StaticInstPtr &inst)   ArmStaticInst * instrAnnotate (const StaticInstPtr &inst)   virtual uint32_t vectorCatchFlag () const   virtual bool isStage2 () const   virtual FSR getFsr (ThreadContext *tc) const   virtual void setSyndrome (ThreadContext *tc, MiscRegIndex syndrome_reg)   virtual bool getFaultVAddr (Addr &va) const   OperatingMode getToMode () const    Public Member Functions inherited from gem5::FaultBase virtual FaultName name () const =0   virtual ~FaultBase ()  

Private Attributes
Addr	vAddr
bool	write
bool	cm

Additional Inherited Members
Public Types inherited from gem5::ArmISA::ArmFault
enum	FaultSource {   AlignmentFault = 0, InstructionCacheMaintenance, SynchExtAbtOnTranslTableWalkLL, SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,   TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, AccessFlagLL = TranslationLL + 4, DomainLL = AccessFlagLL + 4, PermissionLL = DomainLL + 4,   DebugEvent = PermissionLL + 4, SynchronousExternalAbort, TLBConflictAbort, SynchPtyErrOnMemoryAccess,   AsynchronousExternalAbort, AsynchPtyErrOnMemoryAccess, AddressSizeLL, PrefetchTLBMiss = AddressSizeLL + 4,   PrefetchUncacheable, NumFaultSources, FaultSourceInvalid = 0xff }
	Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actual encodings based on the current register width state and the translation table format in use. More...
enum	AnnotationIDs {   S1PTW, OVA, SAS, SSE,   SRT, CM, OFA, SF,   AR }
enum	TranMethod { LpaeTran, VmsaTran, UnknownTran }
enum	DebugType {   NODEBUG = 0, BRKPOINT, VECTORCATCH, WPOINT_CM,   WPOINT_NOCM }
Static Public Attributes inherited from gem5::ArmISA::ArmFault
static uint8_t	shortDescFaultSources [NumFaultSources]
	Encodings of the fault sources when the short-desc. More...
static uint8_t	longDescFaultSources [NumFaultSources]
	Encodings of the fault sources when the long-desc. More...
static uint8_t	aarch64FaultSources [NumFaultSources]
	Encodings of the fault sources in AArch64 state. More...
Protected Member Functions inherited from gem5::ArmISA::ArmFaultVals< Watchpoint >
ArmFault::FaultVals	vals ("Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN)
ArmFault::FaultVals	vals ("Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_UNKNOWN)
ArmFault::FaultVals	vals ("Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP)
ArmFault::FaultVals	vals ("Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP)
ArmFault::FaultVals	vals ("Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 4, 4, 4, 4, true, false, false, EC_HVC)
ArmFault::FaultVals	vals ("Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP)
ArmFault::FaultVals	vals ("Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP)
ArmFault::FaultVals	vals ("Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_INVALID)
ArmFault::FaultVals	vals ("Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 0, 0, 0, 0, false, false, false, EC_UNKNOWN)
ArmFault::FaultVals	vals ("Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 2, 0, 0, false, false, false, EC_UNKNOWN)
ArmFault::FaultVals	vals ("IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_UNKNOWN)
ArmFault::FaultVals	vals ("Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_INVALID)
ArmFault::FaultVals	vals ("FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_UNKNOWN)
ArmFault::FaultVals	vals ("Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_INVALID)
ArmFault::FaultVals	vals ("Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST)
ArmFault::FaultVals	vals ("Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, false, false, false, EC_UNKNOWN)
ArmFault::FaultVals	vals ("PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT)
ArmFault::FaultVals	vals ("SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT)
ArmFault::FaultVals	vals ("SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_SERROR)
ArmFault::FaultVals	vals ("Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT)
ArmFault::FaultVals	vals ("Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT)
ArmFault::FaultVals	vals ("Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_WATCHPOINT)
ArmFault::FaultVals	vals ("SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP)
ArmFault::FaultVals	vals ("ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN)
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
ArmFault::FaultVals	vals
Protected Member Functions inherited from gem5::ArmISA::ArmFault
virtual Addr	getVector (ThreadContext *tc)
Addr	getVector64 (ThreadContext *tc)
Protected Attributes inherited from gem5::ArmISA::ArmFault
ExtMachInst	machInst
uint32_t	issRaw
bool	bStep
bool	from64
bool	to64
ExceptionLevel	fromEL
ExceptionLevel	toEL
OperatingMode	fromMode
OperatingMode	toMode
bool	faultUpdated
bool	hypRouted
bool	span
Static Protected Attributes inherited from gem5::ArmISA::ArmFaultVals< Watchpoint >
static FaultVals	vals

Detailed Description

Definition at line 693 of file faults.hh.

Constructor & Destructor Documentation

Watchpoint()

gem5::ArmISA::Watchpoint::Watchpoint	(	ExtMachInst	mach_inst,
		Addr	vaddr,
		bool	_write,
		bool	_cm
	)

Definition at line 1681 of file faults.cc.

Member Function Documentation

annotate()

void gem5::ArmISA::Watchpoint::annotate ( AnnotationIDs  id, uint64_t  val  )

overridevirtual

Reimplemented from gem5::ArmISA::ArmFault.

Definition at line 1718 of file faults.cc.

References gem5::ArmISA::ArmFault::annotate(), gem5::ArmISA::ArmFault::OFA, vAddr, and gem5::X86ISA::val.

ec()

ExceptionClass gem5::ArmISA::Watchpoint::ec ( ThreadContext *  tc ) const

overridevirtual

Syndrome methods.

Implements gem5::ArmISA::ArmFault.

Definition at line 1733 of file faults.cc.

References gem5::ArmISA::EC_WATCHPOINT_CURR_EL, gem5::ArmISA::EC_WATCHPOINT_LOWER_EL, gem5::ArmISA::ArmFault::fromEL, and gem5::ArmISA::ArmFault::toEL.

il()

bool gem5::ArmISA::Watchpoint::il ( ThreadContext *  tc ) const

inlineoverridevirtual

Implements gem5::ArmISA::ArmFault.

Definition at line 709 of file faults.hh.

invoke()

void gem5::ArmISA::Watchpoint::invoke ( ThreadContext *  tc, const StaticInstPtr &  inst = nullStaticInstPtr  )

overridevirtual

Reimplemented from gem5::ArmISA::ArmFault.

Definition at line 1699 of file faults.cc.

References gem5::ArmISA::ArmFault::getFaultAddrReg64(), gem5::ArmISA::ArmFault::invoke(), gem5::ThreadContext::setMiscReg(), and vAddr.

iss()

uint32_t gem5::ArmISA::Watchpoint::iss ( ) const

overridevirtual

Implements gem5::ArmISA::ArmFault.

Definition at line 1688 of file faults.cc.

References cm, and write.

routeToHyp()

bool gem5::ArmISA::Watchpoint::routeToHyp ( ThreadContext *  tc ) const

overridevirtual

Reimplemented from gem5::ArmISA::ArmFault.

Definition at line 1708 of file faults.cc.

References gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::ArmFault::fromEL, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_MDCR_EL2, and gem5::ThreadContext::readMiscRegNoEffect().

Member Data Documentation

cm

bool gem5::ArmISA::Watchpoint::cm

private

Definition at line 698 of file faults.hh.

Referenced by iss().

vAddr

Addr gem5::ArmISA::Watchpoint::vAddr

private

Definition at line 696 of file faults.hh.

Referenced by annotate(), and invoke().

write

bool gem5::ArmISA::Watchpoint::write

private

Definition at line 697 of file faults.hh.

Referenced by iss().

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The documentation for this class was generated from the following files:

• arch/arm/faults.hh
• arch/arm/faults.cc