|
gem5
v22.0.0.2
|
#include <isa.hh>
Public Types | |
| using | Params = RiscvISAParams |
Public Types inherited from gem5::BaseISA | |
| typedef std::vector< RegClass > | RegClasses |
Public Types inherited from gem5::SimObject | |
| typedef SimObjectParams | Params |
Public Member Functions | |
| void | clear () |
| PCStateBase * | newPCState (Addr new_inst_addr=0) const override |
| RegVal | readMiscRegNoEffect (int misc_reg) const |
| RegVal | readMiscReg (int misc_reg) |
| void | setMiscRegNoEffect (int misc_reg, RegVal val) |
| void | setMiscReg (int misc_reg, RegVal val) |
| RegId | flattenRegId (const RegId ®Id) const |
| int | flattenIntIndex (int reg) const |
| int | flattenFloatIndex (int reg) const |
| int | flattenVecIndex (int reg) const |
| int | flattenVecElemIndex (int reg) const |
| int | flattenVecPredIndex (int reg) const |
| int | flattenCCIndex (int reg) const |
| int | flattenMiscIndex (int reg) const |
| bool | inUserMode () const override |
| void | copyRegsFrom (ThreadContext *src) override |
| void | serialize (CheckpointOut &cp) const override |
| Serialize an object. More... | |
| void | unserialize (CheckpointIn &cp) override |
| Unserialize an object. More... | |
| ISA (const Params &p) | |
| void | handleLockedRead (const RequestPtr &req) override |
| bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) override |
| void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) override |
| void | globalClearExclusive () override |
Public Member Functions inherited from gem5::BaseISA | |
| virtual void | takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) |
| virtual void | setThreadContext (ThreadContext *_tc) |
| virtual uint64_t | getExecutingAsid () const |
| const RegClasses & | regClasses () const |
| virtual void | handleLockedRead (ExecContext *xc, const RequestPtr &req) |
| virtual bool | handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) |
| virtual void | handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) |
| virtual void | handleLockedSnoopHit () |
| virtual void | handleLockedSnoopHit (ExecContext *xc) |
| virtual void | globalClearExclusive (ExecContext *xc) |
Public Member Functions inherited from gem5::SimObject | |
| const Params & | params () const |
| SimObject (const Params &p) | |
| virtual | ~SimObject () |
| virtual void | init () |
| init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
| virtual void | loadState (CheckpointIn &cp) |
| loadState() is called on each SimObject when restoring from a checkpoint. More... | |
| virtual void | initState () |
| initState() is called on each SimObject when not restoring from a checkpoint. More... | |
| virtual void | regProbePoints () |
| Register probe points for this object. More... | |
| virtual void | regProbeListeners () |
| Register probe listeners for this object. More... | |
| ProbeManager * | getProbeManager () |
| Get the probe manager for this object. More... | |
| virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
| Get a port with a given name and index. More... | |
| virtual void | startup () |
| startup() is the final initialization call before simulation. More... | |
| DrainState | drain () override |
| Provide a default implementation of the drain interface for objects that don't need draining. More... | |
| virtual void | memWriteback () |
| Write back dirty buffers to memory using functional writes. More... | |
| virtual void | memInvalidate () |
| Invalidate the contents of memory buffers. More... | |
| void | serialize (CheckpointOut &cp) const override |
| Serialize an object. More... | |
| void | unserialize (CheckpointIn &cp) override |
| Unserialize an object. More... | |
Public Member Functions inherited from gem5::EventManager | |
| EventQueue * | eventQueue () const |
| void | schedule (Event &event, Tick when) |
| void | deschedule (Event &event) |
| void | reschedule (Event &event, Tick when, bool always=false) |
| void | schedule (Event *event, Tick when) |
| void | deschedule (Event *event) |
| void | reschedule (Event *event, Tick when, bool always=false) |
| void | wakeupEventQueue (Tick when=(Tick) -1) |
| This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More... | |
| void | setCurTick (Tick newVal) |
| EventManager (EventManager &em) | |
| Event manger manages events in the event queue. More... | |
| EventManager (EventManager *em) | |
| EventManager (EventQueue *eq) | |
Public Member Functions inherited from gem5::Serializable | |
| Serializable () | |
| virtual | ~Serializable () |
| void | serializeSection (CheckpointOut &cp, const char *name) const |
| Serialize an object into a new section. More... | |
| void | serializeSection (CheckpointOut &cp, const std::string &name) const |
| void | unserializeSection (CheckpointIn &cp, const char *name) |
| Unserialize an a child object. More... | |
| void | unserializeSection (CheckpointIn &cp, const std::string &name) |
Public Member Functions inherited from gem5::Drainable | |
| DrainState | drainState () const |
| Return the current drain state of an object. More... | |
| virtual void | notifyFork () |
| Notify a child process of a fork. More... | |
Public Member Functions inherited from gem5::statistics::Group | |
| Group (Group *parent, const char *name=nullptr) | |
| Construct a new statistics group. More... | |
| virtual | ~Group () |
| virtual void | regStats () |
| Callback to set stat parameters. More... | |
| virtual void | resetStats () |
| Callback to reset stats. More... | |
| virtual void | preDumpStats () |
| Callback before stats are dumped. More... | |
| void | addStat (statistics::Info *info) |
| Register a stat with this group. More... | |
| const std::map< std::string, Group * > & | getStatGroups () const |
| Get all child groups associated with this object. More... | |
| const std::vector< Info * > & | getStats () const |
| Get all stats associated with this object. More... | |
| void | addStatGroup (const char *name, Group *block) |
| Add a stat block as a child of this block. More... | |
| const Info * | resolveStat (std::string name) const |
| Resolve a stat by its name within this group. More... | |
| void | mergeStatGroup (Group *block) |
| Merge the contents (stats & children) of a block to this block. More... | |
| Group ()=delete | |
| Group (const Group &)=delete | |
| Group & | operator= (const Group &)=delete |
Public Member Functions inherited from gem5::Named | |
| Named (const std::string &name_) | |
| virtual | ~Named ()=default |
| virtual std::string | name () const |
Protected Member Functions | |
| bool | hpmCounterEnabled (int counter) const |
Protected Member Functions inherited from gem5::BaseISA | |
| SimObject (const Params &p) | |
Protected Member Functions inherited from gem5::Drainable | |
| Drainable () | |
| virtual | ~Drainable () |
| virtual void | drainResume () |
| Resume execution after a successful drain. More... | |
| void | signalDrainDone () const |
| Signal that an object is drained. More... | |
Protected Attributes | |
| std::vector< RegVal > | miscRegFile |
Protected Attributes inherited from gem5::BaseISA | |
| ThreadContext * | tc = nullptr |
| RegClasses | _regClasses |
Protected Attributes inherited from gem5::SimObject | |
| const SimObjectParams & | _params |
| Cached copy of the object parameters. More... | |
Protected Attributes inherited from gem5::EventManager | |
| EventQueue * | eventq |
| A pointer to this object's event queue. More... | |
Additional Inherited Members | |
Static Public Member Functions inherited from gem5::SimObject | |
| static void | serializeAll (const std::string &cpt_dir) |
| Create a checkpoint by serializing all SimObjects in the system. More... | |
| static SimObject * | find (const char *name) |
| Find the SimObject with the given name and return a pointer to it. More... | |
| static void | setSimObjectResolver (SimObjectResolver *resolver) |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
| static SimObjectResolver * | getSimObjectResolver () |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
Static Public Member Functions inherited from gem5::Serializable | |
| static const std::string & | currentSection () |
| Gets the fully-qualified name of the active section. More... | |
| static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
| Generate a checkpoint file so that the serialization can be routed to it. More... | |
| using gem5::RiscvISA::ISA::Params = RiscvISAParams |
| gem5::RiscvISA::ISA::ISA | ( | const Params & | p | ) |
Definition at line 197 of file isa.cc.
References gem5::BaseISA::_regClasses, clear(), miscRegFile, gem5::RiscvISA::NUM_MISCREGS, gem5::RiscvISA::NumFloatRegs, and gem5::RiscvISA::NumIntRegs.
| void gem5::RiscvISA::ISA::clear | ( | ) |
Definition at line 231 of file isa.cc.
References gem5::MipsISA::fill, gem5::RiscvISA::FS_OFFSET, gem5::RiscvISA::MISCREG_ARCHID, gem5::RiscvISA::MISCREG_IMPID, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_NMIE, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::RiscvISA::MISCREG_VENDORID, miscRegFile, gem5::RiscvISA::PRV_M, gem5::RiscvISA::SXL_OFFSET, and gem5::RiscvISA::UXL_OFFSET.
Referenced by ISA().
|
overridevirtual |
Implements gem5::BaseISA.
Definition at line 217 of file isa.cc.
References gem5::RiscvISA::i, gem5::RiscvISA::NumFloatRegs, gem5::RiscvISA::NumIntRegs, gem5::ThreadContext::pcState(), gem5::ThreadContext::readFloatReg(), gem5::ThreadContext::readIntReg(), gem5::ThreadContext::setFloatReg(), gem5::ThreadContext::setIntReg(), and gem5::BaseISA::tc.
|
inline |
Definition at line 98 of file isa.hh.
References gem5::X86ISA::reg.
|
inline |
Definition at line 94 of file isa.hh.
References gem5::X86ISA::reg.
|
inline |
Definition at line 93 of file isa.hh.
References gem5::X86ISA::reg.
|
inline |
Definition at line 99 of file isa.hh.
References gem5::X86ISA::reg.
|
inline |
Definition at line 96 of file isa.hh.
References gem5::X86ISA::reg.
|
inline |
Definition at line 95 of file isa.hh.
References gem5::X86ISA::reg.
|
inline |
Definition at line 97 of file isa.hh.
References gem5::X86ISA::reg.
|
overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 576 of file isa.cc.
References gem5::ThreadContext::getCpuPtr(), gem5::BaseISA::tc, and gem5::ThreadContext::threadId().
|
overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 528 of file isa.cc.
References gem5::ThreadContext::contextId(), DPRINTF, gem5::RiscvISA::load_reservation_addrs, and gem5::BaseISA::tc.
Reimplemented from gem5::BaseISA.
Definition at line 514 of file isa.cc.
References gem5::ThreadContext::contextId(), DPRINTF, gem5::Packet::getAddr(), gem5::RiscvISA::INVALID_RESERVATION_ADDR, gem5::RiscvISA::load_reservation_addrs, and gem5::BaseISA::tc.
|
overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 538 of file isa.cc.
References gem5::ThreadContext::contextId(), gem5::curTick(), DPRINTF, gem5::RiscvISA::INVALID_RESERVATION_ADDR, gem5::RiscvISA::load_reservation_addrs, gem5::ThreadContext::readStCondFailures(), gem5::ThreadContext::setStCondFailures(), gem5::BaseISA::tc, warn, and gem5::RiscvISA::WARN_FAILURE.
|
protected |
Definition at line 252 of file isa.cc.
References gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, miscRegFile, panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, gem5::RiscvISA::PRV_U, and readMiscRegNoEffect().
Referenced by readMiscReg().
|
overridevirtual |
Implements gem5::BaseISA.
Definition at line 211 of file isa.cc.
References gem5::RiscvISA::MISCREG_PRV, miscRegFile, and gem5::RiscvISA::PRV_U.
|
inlineoverridevirtual |
Implements gem5::BaseISA.
| RegVal gem5::RiscvISA::ISA::readMiscReg | ( | int | misc_reg | ) |
Definition at line 288 of file isa.cc.
References gem5::ThreadContext::contextId(), DPRINTF, gem5::ThreadContext::getCpuPtr(), hpmCounterEnabled(), gem5::igbreg::txd_op::ic(), gem5::RiscvISA::ISA_EXT_C_MASK, gem5::mbits(), gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_HARTID, gem5::RiscvISA::MISCREG_HPMCOUNTER03, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_INSTRET, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MEPC, gem5::RiscvISA::MISCREG_SEPC, gem5::RiscvISA::MISCREG_TIME, readMiscRegNoEffect(), gem5::BaseISA::tc, gem5::ThreadContext::threadId(), gem5::X86ISA::val, and warn.
| RegVal gem5::RiscvISA::ISA::readMiscRegNoEffect | ( | int | misc_reg | ) | const |
Definition at line 275 of file isa.cc.
References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_MISCREGS, and panic.
Referenced by hpmCounterEnabled(), readMiscReg(), and setMiscReg().
|
overridevirtual |
Serialize an object.
Output an object's state into the current checkpoint section.
| cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 495 of file isa.cc.
References DPRINTF, miscRegFile, and SERIALIZE_CONTAINER.
| void gem5::RiscvISA::ISA::setMiscReg | ( | int | misc_reg, |
| RegVal | val | ||
| ) |
Definition at line 375 of file isa.cc.
References gem5::PCStateBase::as(), gem5::bits(), gem5::RiscvISA::CSRData, gem5::ThreadContext::getCpuPtr(), gem5::ThreadContext::getMMUPtr(), gem5::RiscvISA::i, gem5::igbreg::txd_op::ic(), gem5::RiscvISA::ISA_EXT_C_MASK, gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_PMPADDR00, gem5::RiscvISA::MISCREG_PMPADDR15, gem5::RiscvISA::MISCREG_PMPCFG0, gem5::RiscvISA::MISCREG_PMPCFG2, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SATP, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::GenericISA::PCStateWithNext::npc(), gem5::ThreadContext::pcState(), gem5::RiscvISA::PRV_M, readMiscRegNoEffect(), setMiscRegNoEffect(), gem5::RiscvISA::STATUS_SXL_MASK, gem5::RiscvISA::STATUS_UXL_MASK, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), gem5::X86ISA::val, and warn.
| void gem5::RiscvISA::ISA::setMiscRegNoEffect | ( | int | misc_reg, |
| RegVal | val | ||
| ) |
Definition at line 363 of file isa.cc.
References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_MISCREGS, panic, and gem5::X86ISA::val.
Referenced by setMiscReg().
|
overridevirtual |
Unserialize an object.
Read an object's state from the current checkpoint section.
| cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 502 of file isa.cc.
References DPRINTF, miscRegFile, and UNSERIALIZE_CONTAINER.
|
protected |
Definition at line 71 of file isa.hh.
Referenced by clear(), hpmCounterEnabled(), inUserMode(), ISA(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().