thread_context.hh

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 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
#define __CPU_CHECKER_THREAD_CONTEXT_HH__
 
#include "arch/generic/pcstate.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Checker.hh"
 
namespace gem5
{
 
namespace TheISA
{
    class Decoder;
} // namespace TheISA
 
template <class TC>
class CheckerThreadContext : public ThreadContext
{
  public:
    CheckerThreadContext(TC *actual_tc,
                         CheckerCPU *checker_cpu)
        : actualTC(actual_tc), checkerTC(checker_cpu->thread),
          checkerCPU(checker_cpu)
    { }
 
  private:
    TC *actualTC;
    SimpleThread *checkerTC;
    CheckerCPU *checkerCPU;
 
  public:
    bool
    schedule(PCEvent *e) override
    {
        [[maybe_unused]] bool check_ret = checkerTC->schedule(e);
        bool actual_ret = actualTC->schedule(e);
        assert(actual_ret == check_ret);
        return actual_ret;
    }
 
    bool
    remove(PCEvent *e) override
    {
        [[maybe_unused]] bool check_ret = checkerTC->remove(e);
        bool actual_ret = actualTC->remove(e);
        assert(actual_ret == check_ret);
        return actual_ret;
    }
 
    void
    scheduleInstCountEvent(Event *event, Tick count) override
    {
        actualTC->scheduleInstCountEvent(event, count);
    }
    void
    descheduleInstCountEvent(Event *event) override
    {
        actualTC->descheduleInstCountEvent(event);
    }
    Tick
    getCurrentInstCount() override
    {
        return actualTC->getCurrentInstCount();
    }
 
    BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
 
    uint32_t socketId() const override { return actualTC->socketId(); }
 
    int cpuId() const override { return actualTC->cpuId(); }
 
    ContextID contextId() const override { return actualTC->contextId(); }
 
    void
    setContextId(ContextID id) override
    {
       actualTC->setContextId(id);
       checkerTC->setContextId(id);
    }
 
    int threadId() const override { return actualTC->threadId(); }
    void
    setThreadId(int id) override
    {
        checkerTC->setThreadId(id);
        actualTC->setThreadId(id);
    }
 
    BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
 
    CheckerCPU *
    getCheckerCpuPtr() override
    {
        return checkerCPU;
    }
 
    BaseISA *getIsaPtr() const override { return actualTC->getIsaPtr(); }
 
    InstDecoder *
    getDecoderPtr() override
    {
        return actualTC->getDecoderPtr();
    }
 
    System *getSystemPtr() override { return actualTC->getSystemPtr(); }
 
    Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
 
    void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
 
    void
    connectMemPorts(ThreadContext *tc)
    {
        actualTC->connectMemPorts(tc);
    }
 
    Status status() const override { return actualTC->status(); }
 
    void
    setStatus(Status new_status) override
    {
        actualTC->setStatus(new_status);
        checkerTC->setStatus(new_status);
    }
 
    void activate() override { actualTC->activate(); }
 
    void suspend() override { actualTC->suspend(); }
 
    void halt() override { actualTC->halt(); }
 
    void
    takeOverFrom(ThreadContext *oldContext) override
    {
        actualTC->takeOverFrom(oldContext);
        checkerTC->copyState(oldContext);
    }
 
    void
    regStats(const std::string &name) override
    {
        actualTC->regStats(name);
        checkerTC->regStats(name);
    }
 
    Tick readLastActivate() override { return actualTC->readLastActivate(); }
    Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
 
    // @todo: Do I need this?
    void
    copyArchRegs(ThreadContext *tc) override
    {
        actualTC->copyArchRegs(tc);
        checkerTC->copyArchRegs(tc);
    }
 
    void
    clearArchRegs() override
    {
        actualTC->clearArchRegs();
        checkerTC->clearArchRegs();
    }
 
    //
    // New accessors for new decoder.
    //
    RegVal
    getReg(const RegId &reg) const override
    {
        return actualTC->getReg(reg);
    }
 
    void
    getReg(const RegId &reg, void *val) const override
    {
        actualTC->getReg(reg, val);
    }
 
    void *
    getWritableReg(const RegId &reg) override
    {
        return actualTC->getWritableReg(reg);
    }
 
    void
    setReg(const RegId &reg, RegVal val) override
    {
        actualTC->setReg(reg, val);
        checkerTC->setReg(reg, val);
    }
 
    void
    setReg(const RegId &reg, const void *val) override
    {
        actualTC->setReg(reg, val);
        checkerTC->setReg(reg, val);
    }
 
    const PCStateBase &pcState() const override { return actualTC->pcState(); }
 
    void
    pcState(const PCStateBase &val) override
    {
        DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
                         val, checkerTC->pcState());
        checkerTC->pcState(val);
        checkerCPU->recordPCChange(val);
        return actualTC->pcState(val);
    }
 
    void
    pcStateNoRecord(const PCStateBase &val) override
    {
        return actualTC->pcState(val);
    }
 
    RegVal
    readMiscRegNoEffect(RegIndex misc_reg) const override
    {
        return actualTC->readMiscRegNoEffect(misc_reg);
    }
 
    RegVal
    readMiscReg(RegIndex misc_reg) override
    {
        return actualTC->readMiscReg(misc_reg);
    }
 
    void
    setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
    {
        DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                         " and O3..\n", misc_reg);
        checkerTC->setMiscRegNoEffect(misc_reg, val);
        actualTC->setMiscRegNoEffect(misc_reg, val);
    }
 
    void
    setMiscReg(RegIndex misc_reg, RegVal val) override
    {
        DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                         " and O3..\n", misc_reg);
        checkerTC->setMiscReg(misc_reg, val);
        actualTC->setMiscReg(misc_reg, val);
    }
 
    RegId
    flattenRegId(const RegId& regId) const override
    {
        return actualTC->flattenRegId(regId);
    }
 
    unsigned
    readStCondFailures() const override
    {
        return actualTC->readStCondFailures();
    }
 
    void
    setStCondFailures(unsigned sc_failures) override
    {
        actualTC->setStCondFailures(sc_failures);
    }
 
    RegVal
    getRegFlat(const RegId &reg) const override
    {
        return actualTC->getRegFlat(reg);
    }
 
    void
    getRegFlat(const RegId &reg, void *val) const override
    {
        actualTC->getRegFlat(reg, val);
    }
 
    void *
    getWritableRegFlat(const RegId &reg) override
    {
        return actualTC->getWritableRegFlat(reg);
    }
 
    void
    setRegFlat(const RegId &reg, RegVal val) override
    {
        actualTC->setRegFlat(reg, val);
        checkerTC->setRegFlat(reg, val);
    }
 
    void
    setRegFlat(const RegId &reg, const void *val) override
    {
        actualTC->setRegFlat(reg, val);
        checkerTC->setRegFlat(reg, val);
    }
 
    // hardware transactional memory
    void
    htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
    {
        panic("function not implemented");
    }
 
    BaseHTMCheckpointPtr&
    getHtmCheckpointPtr() override
    {
        return actualTC->getHtmCheckpointPtr();
    }
 
    void
    setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
    {
        panic("function not implemented");
    }
 
};
 
} // namespace gem5
 
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__