gem5  v22.0.0.2
gic_v3_cpu_interface.cc
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1 /*
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40 
41 #include "dev/arm/gic_v3_cpu_interface.hh"
42 
43 #include "arch/arm/faults.hh"
44 #include "arch/arm/isa.hh"
45 #include "debug/GIC.hh"
46 #include "dev/arm/gic_v3.hh"
47 #include "dev/arm/gic_v3_distributor.hh"
48 #include "dev/arm/gic_v3_redistributor.hh"
49 
50 namespace gem5
51 {
52 
53 using namespace ArmISA;
54 
55 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
56 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
57 
58 Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
59  : BaseISADevice(),
60  gic(gic),
61  redistributor(nullptr),
62  distributor(nullptr),
63  cpuId(cpu_id)
64 {
65  hppi.prio = 0xff;
66  hppi.intid = Gicv3::INTID_SPURIOUS;
67 }
68 
69 void
70 Gicv3CPUInterface::init()
71 {
72  redistributor = gic->getRedistributor(cpuId);
73  distributor = gic->getDistributor();
74 }
75 
76 void
77 Gicv3CPUInterface::resetHppi(uint32_t intid)
78 {
79  if (intid == hppi.intid)
80  hppi.prio = 0xff;
81 }
82 
83 void
84 Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
85 {
86  maintenanceInterrupt = gic->params().maint_int->get(tc);
87  fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(),
88  "Invalid maintenance interrupt number\n");
89 }
90 
91 bool
92 Gicv3CPUInterface::getHCREL2FMO() const
93 {
94  HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
95 
96  if (hcr.tge && hcr.e2h) {
97  return false;
98  } else if (hcr.tge) {
99  return true;
100  } else {
101  return hcr.fmo;
102  }
103 }
104 
105 bool
106 Gicv3CPUInterface::getHCREL2IMO() const
107 {
108  HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
109 
110  if (hcr.tge && hcr.e2h) {
111  return false;
112  } else if (hcr.tge) {
113  return true;
114  } else {
115  return hcr.imo;
116  }
117 }
118 
119 RegVal
120 Gicv3CPUInterface::readMiscReg(int misc_reg)
121 {
122  RegVal value = isa->readMiscRegNoEffect(misc_reg);
123  bool hcr_fmo = getHCREL2FMO();
124  bool hcr_imo = getHCREL2IMO();
125 
126  switch (misc_reg) {
127  // Active Priorities Group 1 Registers
128  case MISCREG_ICC_AP1R0:
129  case MISCREG_ICC_AP1R0_EL1: {
130  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
131  return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
132  }
133 
134  return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1);
135  }
136 
137  case MISCREG_ICC_AP1R1:
138  case MISCREG_ICC_AP1R1_EL1:
139 
140  // only implemented if supporting 6 or more bits of priority
141  case MISCREG_ICC_AP1R2:
142  case MISCREG_ICC_AP1R2_EL1:
143 
144  // only implemented if supporting 7 or more bits of priority
145  case MISCREG_ICC_AP1R3:
146  case MISCREG_ICC_AP1R3_EL1:
147  // only implemented if supporting 7 or more bits of priority
148  return 0;
149 
150  // Active Priorities Group 0 Registers
151  case MISCREG_ICC_AP0R0:
152  case MISCREG_ICC_AP0R0_EL1: {
153  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
154  return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
155  }
156 
157  break;
158  }
159 
160  case MISCREG_ICC_AP0R1:
161  case MISCREG_ICC_AP0R1_EL1:
162 
163  // only implemented if supporting 6 or more bits of priority
164  case MISCREG_ICC_AP0R2:
165  case MISCREG_ICC_AP0R2_EL1:
166 
167  // only implemented if supporting 7 or more bits of priority
168  case MISCREG_ICC_AP0R3:
169  case MISCREG_ICC_AP0R3_EL1:
170  // only implemented if supporting 7 or more bits of priority
171  return 0;
172 
173  // Interrupt Group 0 Enable register EL1
174  case MISCREG_ICC_IGRPEN0:
175  case MISCREG_ICC_IGRPEN0_EL1: {
176  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
177  return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
178  }
179 
180  break;
181  }
182 
183  case MISCREG_ICV_IGRPEN0_EL1: {
184  ICH_VMCR_EL2 ich_vmcr_el2 =
185  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
186  value = ich_vmcr_el2.VENG0;
187  break;
188  }
189 
190  // Interrupt Group 1 Enable register EL1
191  case MISCREG_ICC_IGRPEN1:
192  case MISCREG_ICC_IGRPEN1_EL1: {
193  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
194  return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
195  }
196 
197  value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
198  break;
199  }
200 
201  case MISCREG_ICV_IGRPEN1_EL1: {
202  ICH_VMCR_EL2 ich_vmcr_el2 =
203  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
204  value = ich_vmcr_el2.VENG1;
205  break;
206  }
207 
208  // Interrupt Group 1 Enable register EL3
209  case MISCREG_ICC_MGRPEN1:
210  case MISCREG_ICC_IGRPEN1_EL3: {
211  ICC_IGRPEN1_EL3 igrp_el3 = 0;
212  igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
213  MISCREG_ICC_IGRPEN1_EL1_S)).Enable;
214 
215  igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
216  MISCREG_ICC_IGRPEN1_EL1_NS)).Enable;
217 
218  value = igrp_el3;
219  break;
220  }
221 
222  // Running Priority Register
223  case MISCREG_ICC_RPR:
224  case MISCREG_ICC_RPR_EL1: {
225  if ((currEL() == EL1) && !inSecureState() &&
226  (hcr_imo || hcr_fmo)) {
227  return readMiscReg(MISCREG_ICV_RPR_EL1);
228  }
229 
230  uint8_t rprio = highestActivePriority();
231 
232  if (haveEL(EL3) && !inSecureState() &&
233  (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
234  // Spec section 4.8.1
235  // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
236  if ((rprio & 0x80) == 0) {
237  // If the current priority mask value is in the range of
238  // 0x00-0x7F a read access returns the value 0x0
239  rprio = 0;
240  } else if (rprio != 0xff) {
241  // If the current priority mask value is in the range of
242  // 0x80-0xFF a read access returns the Non-secure read of
243  // the current value
244  rprio = (rprio << 1) & 0xff;
245  }
246  }
247 
248  value = rprio;
249  break;
250  }
251 
252  // Virtual Running Priority Register
253  case MISCREG_ICV_RPR_EL1: {
254  value = virtualHighestActivePriority();
255  break;
256  }
257 
258  // Highest Priority Pending Interrupt Register 0
259  case MISCREG_ICC_HPPIR0:
260  case MISCREG_ICC_HPPIR0_EL1: {
261  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
262  return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
263  }
264 
265  value = getHPPIR0();
266  break;
267  }
268 
269  // Virtual Highest Priority Pending Interrupt Register 0
270  case MISCREG_ICV_HPPIR0_EL1: {
271  value = Gicv3::INTID_SPURIOUS;
272  int lr_idx = getHPPVILR();
273 
274  if (lr_idx >= 0) {
275  ICH_LR_EL2 ich_lr_el2 =
276  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
277  Gicv3::GroupId group =
278  ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
279 
280  if (group == Gicv3::G0S) {
281  value = ich_lr_el2.vINTID;
282  }
283  }
284 
285  break;
286  }
287 
288  // Highest Priority Pending Interrupt Register 1
289  case MISCREG_ICC_HPPIR1:
290  case MISCREG_ICC_HPPIR1_EL1: {
291  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
292  return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
293  }
294 
295  value = getHPPIR1();
296  break;
297  }
298 
299  // Virtual Highest Priority Pending Interrupt Register 1
300  case MISCREG_ICV_HPPIR1_EL1: {
301  value = Gicv3::INTID_SPURIOUS;
302  int lr_idx = getHPPVILR();
303 
304  if (lr_idx >= 0) {
305  ICH_LR_EL2 ich_lr_el2 =
306  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
307  Gicv3::GroupId group =
308  ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
309 
310  if (group == Gicv3::G1NS) {
311  value = ich_lr_el2.vINTID;
312  }
313  }
314 
315  break;
316  }
317 
318  // Binary Point Register 0
319  case MISCREG_ICC_BPR0:
320  case MISCREG_ICC_BPR0_EL1: {
321  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
322  return readMiscReg(MISCREG_ICV_BPR0_EL1);
323  }
324 
325  value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
326  break;
327  }
328 
329  // Binary Point Register 1
330  case MISCREG_ICC_BPR1:
331  case MISCREG_ICC_BPR1_EL1: {
332  value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS);
333  break;
334  }
335 
336  // Virtual Binary Point Register 0
337  case MISCREG_ICV_BPR0_EL1: {
338  ICH_VMCR_EL2 ich_vmcr_el2 =
339  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
340 
341  value = ich_vmcr_el2.VBPR0;
342  break;
343  }
344 
345  // Virtual Binary Point Register 1
346  case MISCREG_ICV_BPR1_EL1: {
347  ICH_VMCR_EL2 ich_vmcr_el2 =
348  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
349 
350  if (ich_vmcr_el2.VCBPR) {
351  // bpr0 + 1 saturated to 7, WI
352  value = ich_vmcr_el2.VBPR0 + 1;
353  value = value < 7 ? value : 7;
354  } else {
355  value = ich_vmcr_el2.VBPR1;
356  }
357 
358  break;
359  }
360 
361  // Interrupt Priority Mask Register
362  case MISCREG_ICC_PMR:
363  case MISCREG_ICC_PMR_EL1:
364  if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
365  return readMiscReg(MISCREG_ICV_PMR_EL1);
366  }
367 
368  if (haveEL(EL3) && !inSecureState() &&
369  (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
370  // Spec section 4.8.1
371  // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
372  if ((value & 0x80) == 0) {
373  // If the current priority mask value is in the range of
374  // 0x00-0x7F a read access returns the value 0x00.
375  value = 0;
376  } else if (value != 0xff) {
377  // If the current priority mask value is in the range of
378  // 0x80-0xFF a read access returns the Non-secure read of the
379  // current value.
380  value = (value << 1) & 0xff;
381  }
382  }
383 
384  break;
385 
386  case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
387  ICH_VMCR_EL2 ich_vmcr_el2 =
388  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
389 
390  value = ich_vmcr_el2.VPMR;
391  break;
392  }
393 
394  // Interrupt Acknowledge Register 0
395  case MISCREG_ICC_IAR0:
396  case MISCREG_ICC_IAR0_EL1: {
397  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
398  return readMiscReg(MISCREG_ICV_IAR0_EL1);
399  }
400 
401  uint32_t int_id;
402 
403  if (hppiCanPreempt()) {
404  int_id = getHPPIR0();
405 
406  // avoid activation for special interrupts
407  if (int_id < Gicv3::INTID_SECURE ||
408  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
409  activateIRQ(int_id, hppi.group);
410  }
411  } else {
412  int_id = Gicv3::INTID_SPURIOUS;
413  }
414 
415  value = int_id;
416  break;
417  }
418 
419  // Virtual Interrupt Acknowledge Register 0
420  case MISCREG_ICV_IAR0_EL1: {
421  int lr_idx = getHPPVILR();
422  uint32_t int_id = Gicv3::INTID_SPURIOUS;
423 
424  if (lr_idx >= 0) {
425  ICH_LR_EL2 ich_lr_el2 =
426  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
427 
428  if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
429  int_id = ich_lr_el2.vINTID;
430 
431  if (int_id < Gicv3::INTID_SECURE ||
432  int_id > Gicv3::INTID_SPURIOUS) {
433  virtualActivateIRQ(lr_idx);
434  } else {
435  // Bogus... Pseudocode says:
436  // - Move from pending to invalid...
437  // - Return de bogus id...
438  ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
439  isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
440  ich_lr_el2);
441  }
442  }
443  }
444 
445  value = int_id;
446  virtualUpdate();
447  break;
448  }
449 
450  // Interrupt Acknowledge Register 1
451  case MISCREG_ICC_IAR1:
452  case MISCREG_ICC_IAR1_EL1: {
453  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
454  return readMiscReg(MISCREG_ICV_IAR1_EL1);
455  }
456 
457  uint32_t int_id;
458 
459  if (hppiCanPreempt()) {
460  int_id = getHPPIR1();
461 
462  // avoid activation for special interrupts
463  if (int_id < Gicv3::INTID_SECURE ||
464  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
465  activateIRQ(int_id, hppi.group);
466  }
467  } else {
468  int_id = Gicv3::INTID_SPURIOUS;
469  }
470 
471  value = int_id;
472  break;
473  }
474 
475  // Virtual Interrupt Acknowledge Register 1
476  case MISCREG_ICV_IAR1_EL1: {
477  int lr_idx = getHPPVILR();
478  uint32_t int_id = Gicv3::INTID_SPURIOUS;
479 
480  if (lr_idx >= 0) {
481  ICH_LR_EL2 ich_lr_el2 =
482  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
483 
484  if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) {
485  int_id = ich_lr_el2.vINTID;
486 
487  if (int_id < Gicv3::INTID_SECURE ||
488  int_id > Gicv3::INTID_SPURIOUS) {
489  virtualActivateIRQ(lr_idx);
490  } else {
491  // Bogus... Pseudocode says:
492  // - Move from pending to invalid...
493  // - Return de bogus id...
494  ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
495  isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
496  ich_lr_el2);
497  }
498  }
499  }
500 
501  value = int_id;
502  virtualUpdate();
503  break;
504  }
505 
506  // System Register Enable Register EL1
507  case MISCREG_ICC_SRE:
508  case MISCREG_ICC_SRE_EL1: {
509  /*
510  * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
511  * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
512  * SRE [0] == 1 (Only system register interface supported, RAO/WI)
513  */
514  ICC_SRE_EL1 icc_sre_el1 = 0;
515  icc_sre_el1.SRE = 1;
516  icc_sre_el1.DIB = 1;
517  icc_sre_el1.DFB = 1;
518  value = icc_sre_el1;
519  break;
520  }
521 
522  // System Register Enable Register EL2
523  case MISCREG_ICC_HSRE:
524  case MISCREG_ICC_SRE_EL2: {
525  /*
526  * Enable [3] == 1
527  * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI)
528  * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
529  * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
530  * SRE [0] == 1 (Only system register interface supported, RAO/WI)
531  */
532  ICC_SRE_EL2 icc_sre_el2 = 0;
533  icc_sre_el2.SRE = 1;
534  icc_sre_el2.DIB = 1;
535  icc_sre_el2.DFB = 1;
536  icc_sre_el2.Enable = 1;
537  value = icc_sre_el2;
538  break;
539  }
540 
541  // System Register Enable Register EL3
542  case MISCREG_ICC_MSRE:
543  case MISCREG_ICC_SRE_EL3: {
544  /*
545  * Enable [3] == 1
546  * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
547  * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
548  * RAO/WI)
549  * DIB [2] == 1 (IRQ bypass not supported, RAO/WI)
550  * DFB [1] == 1 (FIQ bypass not supported, RAO/WI)
551  * SRE [0] == 1 (Only system register interface supported, RAO/WI)
552  */
553  ICC_SRE_EL3 icc_sre_el3 = 0;
554  icc_sre_el3.SRE = 1;
555  icc_sre_el3.DIB = 1;
556  icc_sre_el3.DFB = 1;
557  icc_sre_el3.Enable = 1;
558  value = icc_sre_el3;
559  break;
560  }
561 
562  // Control Register
563  case MISCREG_ICC_CTLR:
564  case MISCREG_ICC_CTLR_EL1: {
565  if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
566  return readMiscReg(MISCREG_ICV_CTLR_EL1);
567  }
568 
569  value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
570  // Enforce value for RO bits
571  // ExtRange [19], INTIDs in the range 1024..8191 not supported
572  // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
573  // A3V [15], supports non-zero values of the Aff3 field in SGI
574  // generation System registers
575  // SEIS [14], does not support generation of SEIs (deprecated)
576  // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
577  // PRIbits [10:8], number of priority bits implemented, minus one
578  ICC_CTLR_EL1 icc_ctlr_el1 = value;
579  icc_ctlr_el1.ExtRange = 0;
580  icc_ctlr_el1.RSS = 1;
581  icc_ctlr_el1.A3V = 1;
582  icc_ctlr_el1.SEIS = 0;
583  icc_ctlr_el1.IDbits = 1;
584  icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1;
585  value = icc_ctlr_el1;
586  break;
587  }
588 
589  // Virtual Control Register
590  case MISCREG_ICV_CTLR_EL1: {
591  ICV_CTLR_EL1 icv_ctlr_el1 = value;
592  icv_ctlr_el1.RSS = 0;
593  icv_ctlr_el1.A3V = 1;
594  icv_ctlr_el1.SEIS = 0;
595  icv_ctlr_el1.IDbits = 1;
596  icv_ctlr_el1.PRIbits = 7;
597  value = icv_ctlr_el1;
598  break;
599  }
600 
601  // Control Register
602  case MISCREG_ICC_MCTLR:
603  case MISCREG_ICC_CTLR_EL3: {
604  // Enforce value for RO bits
605  // ExtRange [19], INTIDs in the range 1024..8191 not supported
606  // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
607  // nDS [17], supports disabling of security
608  // A3V [15], supports non-zero values of the Aff3 field in SGI
609  // generation System registers
610  // SEIS [14], does not support generation of SEIs (deprecated)
611  // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
612  // PRIbits [10:8], number of priority bits implemented, minus one
613  ICC_CTLR_EL3 icc_ctlr_el3 = value;
614  icc_ctlr_el3.ExtRange = 0;
615  icc_ctlr_el3.RSS = 1;
616  icc_ctlr_el3.nDS = 0;
617  icc_ctlr_el3.A3V = 1;
618  icc_ctlr_el3.SEIS = 0;
619  icc_ctlr_el3.IDbits = 0;
620  icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1;
621  value = icc_ctlr_el3;
622  break;
623  }
624 
625  // Hyp Control Register
626  case MISCREG_ICH_HCR:
627  case MISCREG_ICH_HCR_EL2:
628  break;
629 
630  // Hyp Active Priorities Group 0 Registers
631  case MISCREG_ICH_AP0R0:
632  case MISCREG_ICH_AP0R0_EL2:
633  break;
634 
635  // only implemented if supporting 6 or more bits of priority
636  case MISCREG_ICH_AP0R1:
637  case MISCREG_ICH_AP0R1_EL2:
638  // only implemented if supporting 7 or more bits of priority
639  case MISCREG_ICH_AP0R2:
640  case MISCREG_ICH_AP0R2_EL2:
641  // only implemented if supporting 7 or more bits of priority
642  case MISCREG_ICH_AP0R3:
643  case MISCREG_ICH_AP0R3_EL2:
644  // Unimplemented registers are RAZ/WI
645  return 0;
646 
647  // Hyp Active Priorities Group 1 Registers
648  case MISCREG_ICH_AP1R0:
649  case MISCREG_ICH_AP1R0_EL2:
650  break;
651 
652  // only implemented if supporting 6 or more bits of priority
653  case MISCREG_ICH_AP1R1:
654  case MISCREG_ICH_AP1R1_EL2:
655  // only implemented if supporting 7 or more bits of priority
656  case MISCREG_ICH_AP1R2:
657  case MISCREG_ICH_AP1R2_EL2:
658  // only implemented if supporting 7 or more bits of priority
659  case MISCREG_ICH_AP1R3:
660  case MISCREG_ICH_AP1R3_EL2:
661  // Unimplemented registers are RAZ/WI
662  return 0;
663 
664  // Maintenance Interrupt State Register
665  case MISCREG_ICH_MISR:
666  case MISCREG_ICH_MISR_EL2:
667  value = maintenanceInterruptStatus();
668  break;
669 
670  // VGIC Type Register
671  case MISCREG_ICH_VTR:
672  case MISCREG_ICH_VTR_EL2: {
673  ICH_VTR_EL2 ich_vtr_el2 = value;
674 
675  ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1;
676  ich_vtr_el2.A3V = 1;
677  ich_vtr_el2.IDbits = 1;
678  ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1;
679  ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1;
680 
681  value = ich_vtr_el2;
682  break;
683  }
684 
685  // End of Interrupt Status Register
686  case MISCREG_ICH_EISR:
687  case MISCREG_ICH_EISR_EL2:
688  value = eoiMaintenanceInterruptStatus();
689  break;
690 
691  // Empty List Register Status Register
692  case MISCREG_ICH_ELRSR:
693  case MISCREG_ICH_ELRSR_EL2:
694  value = 0;
695 
696  for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
697  ICH_LR_EL2 ich_lr_el2 =
698  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
699 
700  if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
701  (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
702  value |= (1 << lr_idx);
703  }
704  }
705 
706  break;
707 
708  // List Registers
709  case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
710  // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
711  value = value >> 32;
712  break;
713 
714  // List Registers
715  case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
716  // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
717  value = value & 0xffffffff;
718  break;
719 
720  // List Registers
721  case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
722  break;
723 
724  // Virtual Machine Control Register
725  case MISCREG_ICH_VMCR:
726  case MISCREG_ICH_VMCR_EL2:
727  break;
728 
729  default:
730  panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
731  misc_reg, miscRegName[misc_reg]);
732  }
733 
734  DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n",
735  miscRegName[misc_reg], value);
736  return value;
737 }
738 
739 void
740 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
741 {
742  bool do_virtual_update = false;
743  DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n",
744  miscRegName[misc_reg], val);
745  bool hcr_fmo = getHCREL2FMO();
746  bool hcr_imo = getHCREL2IMO();
747 
748  switch (misc_reg) {
749  // Active Priorities Group 1 Registers
750  case MISCREG_ICC_AP1R0:
751  case MISCREG_ICC_AP1R0_EL1:
752  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
753  return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
754  }
755 
756  setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
757  return;
758 
759  case MISCREG_ICC_AP1R1:
760  case MISCREG_ICC_AP1R1_EL1:
761 
762  // only implemented if supporting 6 or more bits of priority
763  case MISCREG_ICC_AP1R2:
764  case MISCREG_ICC_AP1R2_EL1:
765 
766  // only implemented if supporting 7 or more bits of priority
767  case MISCREG_ICC_AP1R3:
768  case MISCREG_ICC_AP1R3_EL1:
769  // only implemented if supporting 7 or more bits of priority
770  break;
771 
772  // Active Priorities Group 0 Registers
773  case MISCREG_ICC_AP0R0:
774  case MISCREG_ICC_AP0R0_EL1:
775  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
776  return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
777  }
778 
779  break;
780 
781  case MISCREG_ICC_AP0R1:
782  case MISCREG_ICC_AP0R1_EL1:
783 
784  // only implemented if supporting 6 or more bits of priority
785  case MISCREG_ICC_AP0R2:
786  case MISCREG_ICC_AP0R2_EL1:
787 
788  // only implemented if supporting 7 or more bits of priority
789  case MISCREG_ICC_AP0R3:
790  case MISCREG_ICC_AP0R3_EL1:
791  // only implemented if supporting 7 or more bits of priority
792  break;
793 
794  // End Of Interrupt Register 0
795  case MISCREG_ICC_EOIR0:
796  case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
797  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
798  return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
799  }
800 
801  int int_id = val & 0xffffff;
802 
803  // avoid activation for special interrupts
804  if (int_id >= Gicv3::INTID_SECURE &&
805  int_id <= Gicv3::INTID_SPURIOUS) {
806  return;
807  }
808 
809  Gicv3::GroupId group = Gicv3::G0S;
810 
811  if (highestActiveGroup() != group) {
812  return;
813  }
814 
815  dropPriority(group);
816 
817  if (!isEOISplitMode()) {
818  deactivateIRQ(int_id, group);
819  }
820 
821  break;
822  }
823 
824  // Virtual End Of Interrupt Register 0
825  case MISCREG_ICV_EOIR0_EL1: {
826  int int_id = val & 0xffffff;
827 
828  // avoid deactivation for special interrupts
829  if (int_id >= Gicv3::INTID_SECURE &&
830  int_id <= Gicv3::INTID_SPURIOUS) {
831  return;
832  }
833 
834  uint8_t drop_prio = virtualDropPriority();
835 
836  if (drop_prio == 0xff) {
837  return;
838  }
839 
840  int lr_idx = virtualFindActive(int_id);
841 
842  if (lr_idx < 0) {
843  // No LR found matching
844  virtualIncrementEOICount();
845  } else {
846  ICH_LR_EL2 ich_lr_el2 =
847  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
848  Gicv3::GroupId lr_group =
849  ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
850  uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
851 
852  if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
853  //if (!virtualIsEOISplitMode())
854  {
855  virtualDeactivateIRQ(lr_idx);
856  }
857  }
858  }
859 
860  virtualUpdate();
861  break;
862  }
863 
864  // End Of Interrupt Register 1
865  case MISCREG_ICC_EOIR1:
866  case MISCREG_ICC_EOIR1_EL1: {
867  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
868  return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
869  }
870 
871  int int_id = val & 0xffffff;
872 
873  // avoid deactivation for special interrupts
874  if (int_id >= Gicv3::INTID_SECURE &&
875  int_id <= Gicv3::INTID_SPURIOUS) {
876  return;
877  }
878 
879  Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
880 
881  if (highestActiveGroup() == Gicv3::G0S) {
882  return;
883  }
884 
885  if (distributor->DS == 0) {
886  if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
887  return;
888  } else if (highestActiveGroup() == Gicv3::G1NS &&
889  !(!inSecureState() or (currEL() == EL3))) {
890  return;
891  }
892  }
893 
894  dropPriority(group);
895 
896  if (!isEOISplitMode()) {
897  deactivateIRQ(int_id, group);
898  }
899 
900  break;
901  }
902 
903  // Virtual End Of Interrupt Register 1
904  case MISCREG_ICV_EOIR1_EL1: {
905  int int_id = val & 0xffffff;
906 
907  // avoid deactivation for special interrupts
908  if (int_id >= Gicv3::INTID_SECURE &&
909  int_id <= Gicv3::INTID_SPURIOUS) {
910  return;
911  }
912 
913  uint8_t drop_prio = virtualDropPriority();
914 
915  if (drop_prio == 0xff) {
916  return;
917  }
918 
919  int lr_idx = virtualFindActive(int_id);
920 
921  if (lr_idx < 0) {
922  // No matching LR found
923  virtualIncrementEOICount();
924  } else {
925  ICH_LR_EL2 ich_lr_el2 =
926  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
927  Gicv3::GroupId lr_group =
928  ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
929  uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8;
930 
931  if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
932  if (!virtualIsEOISplitMode()) {
933  virtualDeactivateIRQ(lr_idx);
934  }
935  }
936  }
937 
938  virtualUpdate();
939  break;
940  }
941 
942  // Deactivate Interrupt Register
943  case MISCREG_ICC_DIR:
944  case MISCREG_ICC_DIR_EL1: {
945  if ((currEL() == EL1) && !inSecureState() &&
946  (hcr_imo || hcr_fmo)) {
947  return setMiscReg(MISCREG_ICV_DIR_EL1, val);
948  }
949 
950  int int_id = val & 0xffffff;
951 
952  // The following checks are as per spec pseudocode
953  // aarch64/support/ICC_DIR_EL1
954 
955  // Check for spurious ID
956  if (int_id >= Gicv3::INTID_SECURE) {
957  return;
958  }
959 
960  // EOI mode is not set, so don't deactivate
961  if (!isEOISplitMode()) {
962  return;
963  }
964 
965  Gicv3::GroupId group =
966  int_id >= 32 ? distributor->getIntGroup(int_id) :
967  redistributor->getIntGroup(int_id);
968  bool irq_is_grp0 = group == Gicv3::G0S;
969  bool single_sec_state = distributor->DS;
970  bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
971  SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
972  bool route_fiq_to_el3 = scr_el3.fiq;
973  bool route_irq_to_el3 = scr_el3.irq;
974  bool route_fiq_to_el2 = hcr_fmo;
975  bool route_irq_to_el2 = hcr_imo;
976 
977  switch (currEL()) {
978  case EL3:
979  break;
980 
981  case EL2:
982  if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
983  break;
984  }
985 
986  if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
987  break;
988  }
989 
990  return;
991 
992  case EL1:
993  if (!isSecureBelowEL3()) {
994  if (single_sec_state && irq_is_grp0 &&
995  !route_fiq_to_el3 && !route_fiq_to_el2) {
996  break;
997  }
998 
999  if (!irq_is_secure && !irq_is_grp0 &&
1000  !route_irq_to_el3 && !route_irq_to_el2) {
1001  break;
1002  }
1003  } else {
1004  if (irq_is_grp0 && !route_fiq_to_el3) {
1005  break;
1006  }
1007 
1008  if (!irq_is_grp0 &&
1009  (!irq_is_secure || !single_sec_state) &&
1010  !route_irq_to_el3) {
1011  break;
1012  }
1013  }
1014 
1015  return;
1016 
1017  default:
1018  break;
1019  }
1020 
1021  deactivateIRQ(int_id, group);
1022  break;
1023  }
1024 
1025  // Deactivate Virtual Interrupt Register
1026  case MISCREG_ICV_DIR_EL1: {
1027  int int_id = val & 0xffffff;
1028 
1029  // avoid deactivation for special interrupts
1030  if (int_id >= Gicv3::INTID_SECURE &&
1031  int_id <= Gicv3::INTID_SPURIOUS) {
1032  return;
1033  }
1034 
1035  if (!virtualIsEOISplitMode()) {
1036  return;
1037  }
1038 
1039  int lr_idx = virtualFindActive(int_id);
1040 
1041  if (lr_idx < 0) {
1042  // No matching LR found
1043  virtualIncrementEOICount();
1044  } else {
1045  virtualDeactivateIRQ(lr_idx);
1046  }
1047 
1048  virtualUpdate();
1049  break;
1050  }
1051 
1052  // Binary Point Register 0
1053  case MISCREG_ICC_BPR0:
1054  case MISCREG_ICC_BPR0_EL1: {
1055  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1056  return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1057  }
1058  break;
1059  }
1060  // Binary Point Register 1
1061  case MISCREG_ICC_BPR1:
1062  case MISCREG_ICC_BPR1_EL1: {
1063  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1064  return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1065  }
1066 
1067  val &= 0x7;
1068 
1069  if (isSecureBelowEL3()) {
1070  // group == Gicv3::G1S
1071  ICC_CTLR_EL1 icc_ctlr_el1_s =
1072  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1073 
1074  val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR;
1075  if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) {
1076  isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val);
1077  } else {
1078  isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val);
1079  }
1080  return;
1081  } else {
1082  // group == Gicv3::G1NS
1083  ICC_CTLR_EL1 icc_ctlr_el1_ns =
1084  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1085 
1086  val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS;
1087  if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) {
1088  // Non secure writes from EL1 and EL2 are ignored
1089  } else {
1090  isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val);
1091  }
1092  return;
1093  }
1094 
1095  break;
1096  }
1097 
1098  // Virtual Binary Point Register 0
1099  case MISCREG_ICV_BPR0_EL1:
1100  // Virtual Binary Point Register 1
1101  case MISCREG_ICV_BPR1_EL1: {
1102  Gicv3::GroupId group =
1103  misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1104  ICH_VMCR_EL2 ich_vmcr_el2 =
1105  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1106 
1107  if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1108  // BPR0 + 1 saturated to 7, WI
1109  return;
1110  }
1111 
1112  uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;
1113 
1114  if (group != Gicv3::G0S) {
1115  min_VPBR++;
1116  }
1117 
1118  if (val < min_VPBR) {
1119  val = min_VPBR;
1120  }
1121 
1122  if (group == Gicv3::G0S) {
1123  ich_vmcr_el2.VBPR0 = val;
1124  } else {
1125  ich_vmcr_el2.VBPR1 = val;
1126  }
1127 
1128  isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1129  do_virtual_update = true;
1130  break;
1131  }
1132 
1133  // Control Register EL1
1134  case MISCREG_ICC_CTLR:
1135  case MISCREG_ICC_CTLR_EL1: {
1136  if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1137  return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1138  }
1139 
1140  /*
1141  * ExtRange is RO.
1142  * RSS is RO.
1143  * A3V is RO.
1144  * SEIS is RO.
1145  * IDbits is RO.
1146  * PRIbits is RO.
1147  */
1148  ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1149  ICC_CTLR_EL1 icc_ctlr_el1 =
1150  readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
1151 
1152  ICC_CTLR_EL3 icc_ctlr_el3 =
1153  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1154 
1155  // The following could be refactored but it is following
1156  // spec description section 9.2.6 point by point.
1157 
1158  // PMHE
1159  if (haveEL(EL3)) {
1160  // PMHE is alias of ICC_CTLR_EL3.PMHE
1161 
1162  if (distributor->DS == 0) {
1163  // PMHE is RO
1164  } else if (distributor->DS == 1) {
1165  // PMHE is RW
1166  icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1167  icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE;
1168  }
1169  } else {
1170  // PMHE is RW (by implementation choice)
1171  icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE;
1172  }
1173 
1174  // EOImode
1175  icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode;
1176 
1177  if (inSecureState()) {
1178  // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S
1179  icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode;
1180  } else {
1181  // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS
1182  icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode;
1183  }
1184 
1185  // CBPR
1186  if (haveEL(EL3)) {
1187  // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS}
1188 
1189  if (distributor->DS == 0) {
1190  // CBPR is RO
1191  } else {
1192  // CBPR is RW
1193  icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1194 
1195  if (inSecureState()) {
1196  icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR;
1197  } else {
1198  icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR;
1199  }
1200  }
1201  } else {
1202  // CBPR is RW
1203  icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1204  }
1205 
1206  isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1207 
1208  setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1);
1209  return;
1210  }
1211 
1212  // Virtual Control Register
1213  case MISCREG_ICV_CTLR_EL1: {
1214  ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1215  ICV_CTLR_EL1 icv_ctlr_el1 =
1216  isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1217  icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;
1218  icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR;
1219  val = icv_ctlr_el1;
1220 
1221  // Aliases
1222  // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR.
1223  // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM.
1224  ICH_VMCR_EL2 ich_vmcr_el2 =
1225  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1226  ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR;
1227  ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode;
1228  isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1229  break;
1230  }
1231 
1232  // Control Register EL3
1233  case MISCREG_ICC_MCTLR:
1234  case MISCREG_ICC_CTLR_EL3: {
1235  /*
1236  * ExtRange is RO.
1237  * RSS is RO.
1238  * nDS is RO.
1239  * A3V is RO.
1240  * SEIS is RO.
1241  * IDbits is RO.
1242  * PRIbits is RO.
1243  * PMHE is RAO/WI, priority-based routing is always used.
1244  */
1245  ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1246 
1247  // Aliases
1248  if (haveEL(EL3))
1249  {
1250  ICC_CTLR_EL1 icc_ctlr_el1_s =
1251  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1252  ICC_CTLR_EL1 icc_ctlr_el1_ns =
1253  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1254 
1255  // ICC_CTLR_EL1(NS).EOImode is an alias of
1256  // ICC_CTLR_EL3.EOImode_EL1NS
1257  icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS;
1258  // ICC_CTLR_EL1(S).EOImode is an alias of
1259  // ICC_CTLR_EL3.EOImode_EL1S
1260  icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S;
1261  // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1262  icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS;
1263  // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1264  icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S;
1265 
1266  isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1267  isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS,
1268  icc_ctlr_el1_ns);
1269  }
1270 
1271  ICC_CTLR_EL3 icc_ctlr_el3 =
1272  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1273 
1274  icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM;
1275  icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS;
1276  icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S;
1277  icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3;
1278  icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS;
1279  icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S;
1280 
1281  val = icc_ctlr_el3;
1282  break;
1283  }
1284 
1285  // Priority Mask Register
1286  case MISCREG_ICC_PMR:
1287  case MISCREG_ICC_PMR_EL1: {
1288  if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1289  return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1290  }
1291 
1292  val &= 0xff;
1293  SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1294 
1295  if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1296  // Spec section 4.8.1
1297  // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
1298  RegVal old_icc_pmr_el1 =
1299  isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1300 
1301  if (!(old_icc_pmr_el1 & 0x80)) {
1302  // If the current priority mask value is in the range of
1303  // 0x00-0x7F then WI
1304  return;
1305  }
1306 
1307  // If the current priority mask value is in the range of
1308  // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
1309  // based on the Non-secure read of the priority mask value
1310  // written to the register.
1311 
1312  val = (val >> 1) | 0x80;
1313  }
1314 
1315  val &= ~0U << (8 - PRIORITY_BITS);
1316  break;
1317  }
1318 
1319  case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1320  ICH_VMCR_EL2 ich_vmcr_el2 =
1321  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1322  ich_vmcr_el2.VPMR = val & 0xff;
1323 
1324  isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1325  virtualUpdate();
1326  return;
1327  }
1328 
1329  // Interrupt Group 0 Enable Register EL1
1330  case MISCREG_ICC_IGRPEN0:
1331  case MISCREG_ICC_IGRPEN0_EL1: {
1332  if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1333  return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1334  }
1335 
1336  isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
1337  updateDistributor();
1338  return;
1339  }
1340 
1341  // Virtual Interrupt Group 0 Enable register
1342  case MISCREG_ICV_IGRPEN0_EL1: {
1343  bool enable = val & 0x1;
1344  ICH_VMCR_EL2 ich_vmcr_el2 =
1345  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1346  ich_vmcr_el2.VENG0 = enable;
1347  isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1348  virtualUpdate();
1349  return;
1350  }
1351 
1352  // Interrupt Group 1 Enable register EL1
1353  case MISCREG_ICC_IGRPEN1:
1354  case MISCREG_ICC_IGRPEN1_EL1: {
1355  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1356  return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1357  }
1358 
1359  setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1360  updateDistributor();
1361  return;
1362  }
1363 
1364  // Virtual Interrupt Group 1 Enable register
1365  case MISCREG_ICV_IGRPEN1_EL1: {
1366  bool enable = val & 0x1;
1367  ICH_VMCR_EL2 ich_vmcr_el2 =
1368  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1369  ich_vmcr_el2.VENG1 = enable;
1370  isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1371  virtualUpdate();
1372  return;
1373  }
1374 
1375  // Interrupt Group 1 Enable register
1376  case MISCREG_ICC_MGRPEN1:
1377  case MISCREG_ICC_IGRPEN1_EL3: {
1378  ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1379 
1380  isa->setMiscRegNoEffect(
1381  MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
1382  isa->setMiscRegNoEffect(
1383  MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
1384  updateDistributor();
1385  return;
1386  }
1387 
1388  // Software Generated Interrupt Group 0 Register
1389  case MISCREG_ICC_SGI0R:
1390  case MISCREG_ICC_SGI0R_EL1:
1391  generateSGI(val, Gicv3::G0S);
1392  break;
1393 
1394  // Software Generated Interrupt Group 1 Register
1395  case MISCREG_ICC_SGI1R:
1396  case MISCREG_ICC_SGI1R_EL1: {
1397  Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
1398 
1399  generateSGI(val, group);
1400  break;
1401  }
1402 
1403  // Alias Software Generated Interrupt Group 1 Register
1404  case MISCREG_ICC_ASGI1R:
1405  case MISCREG_ICC_ASGI1R_EL1: {
1406  Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S;
1407 
1408  generateSGI(val, group);
1409  break;
1410  }
1411 
1412  // System Register Enable Register EL1
1413  case MISCREG_ICC_SRE:
1414  case MISCREG_ICC_SRE_EL1:
1415  // System Register Enable Register EL2
1416  case MISCREG_ICC_HSRE:
1417  case MISCREG_ICC_SRE_EL2:
1418  // System Register Enable Register EL3
1419  case MISCREG_ICC_MSRE:
1420  case MISCREG_ICC_SRE_EL3:
1421  // All bits are RAO/WI
1422  return;
1423 
1424  // Hyp Control Register
1425  case MISCREG_ICH_HCR:
1426  case MISCREG_ICH_HCR_EL2: {
1427  ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1428  ICH_HCR_EL2 ich_hcr_el2 =
1429  isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1430 
1431  if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount)
1432  {
1433  // EOIcount - Permitted behaviors are:
1434  // - Increment EOIcount.
1435  // - Leave EOIcount unchanged.
1436  ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount;
1437  }
1438 
1439  ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR;
1440  ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI;
1441  ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;;
1442  ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;;
1443  ich_hcr_el2.TC = requested_ich_hcr_el2.TC;
1444  ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE;
1445  ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE;
1446  ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE;
1447  ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE;
1448  ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE;
1449  ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE;
1450  ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE;
1451  ich_hcr_el2.En = requested_ich_hcr_el2.En;
1452  val = ich_hcr_el2;
1453  do_virtual_update = true;
1454  break;
1455  }
1456 
1457  // List Registers
1458  case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {
1459  // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1460  ICH_LRC requested_ich_lrc = val;
1461  ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1462 
1463  ich_lrc.State = requested_ich_lrc.State;
1464  ich_lrc.HW = requested_ich_lrc.HW;
1465  ich_lrc.Group = requested_ich_lrc.Group;
1466 
1467  // Priority, bits [23:16]
1468  // At least five bits must be implemented.
1469  // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1470  // We implement 5 bits.
1471  ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) |
1472  (ich_lrc.Priority & 0x07);
1473 
1474  // pINTID, bits [12:0]
1475  // When ICH_LR<n>.HW is 0 this field has the following meaning:
1476  // - Bits[12:10] : RES0.
1477  // - Bit[9] : EOI.
1478  // - Bits[8:0] : RES0.
1479  // When ICH_LR<n>.HW is 1:
1480  // - This field is only required to implement enough bits to hold a
1481  // valid value for the implemented INTID size. Any unused higher
1482  // order bits are RES0.
1483  if (requested_ich_lrc.HW == 0) {
1484  ich_lrc.EOI = requested_ich_lrc.EOI;
1485  } else {
1486  ich_lrc.pINTID = requested_ich_lrc.pINTID;
1487  }
1488 
1489  val = ich_lrc;
1490  do_virtual_update = true;
1491  break;
1492  }
1493 
1494  // List Registers
1495  case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1496  // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1497  RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1498  val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1499  do_virtual_update = true;
1500  break;
1501  }
1502 
1503  // List Registers
1504  case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1505  ICH_LR_EL2 requested_ich_lr_el2 = val;
1506  ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1507 
1508  ich_lr_el2.State = requested_ich_lr_el2.State;
1509  ich_lr_el2.HW = requested_ich_lr_el2.HW;
1510  ich_lr_el2.Group = requested_ich_lr_el2.Group;
1511 
1512  // Priority, bits [55:48]
1513  // At least five bits must be implemented.
1514  // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1515  // We implement 5 bits.
1516  ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) |
1517  (ich_lr_el2.Priority & 0x07);
1518 
1519  // pINTID, bits [44:32]
1520  // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1521  // - Bits[44:42] : RES0.
1522  // - Bit[41] : EOI.
1523  // - Bits[40:32] : RES0.
1524  // When ICH_LR<n>_EL2.HW is 1:
1525  // - This field is only required to implement enough bits to hold a
1526  // valid value for the implemented INTID size. Any unused higher
1527  // order bits are RES0.
1528  if (requested_ich_lr_el2.HW == 0) {
1529  ich_lr_el2.EOI = requested_ich_lr_el2.EOI;
1530  } else {
1531  ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID;
1532  }
1533 
1534  // vINTID, bits [31:0]
1535  // It is IMPLEMENTATION DEFINED how many bits are implemented,
1536  // though at least 16 bits must be implemented.
1537  // Unimplemented bits are RES0.
1538  ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID;
1539 
1540  val = ich_lr_el2;
1541  do_virtual_update = true;
1542  break;
1543  }
1544 
1545  // Virtual Machine Control Register
1546  case MISCREG_ICH_VMCR:
1547  case MISCREG_ICH_VMCR_EL2: {
1548  ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1549  ICH_VMCR_EL2 ich_vmcr_el2 =
1550  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1551  ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR;
1552  uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
1553 
1554  if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) {
1555  ich_vmcr_el2.VBPR0 = min_vpr0;
1556  } else {
1557  ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0;
1558  }
1559 
1560  uint8_t min_vpr1 = min_vpr0 + 1;
1561 
1562  if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) {
1563  ich_vmcr_el2.VBPR1 = min_vpr1;
1564  } else {
1565  ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1;
1566  }
1567 
1568  ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM;
1569  ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR;
1570  ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1;
1571  ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0;
1572  val = ich_vmcr_el2;
1573  break;
1574  }
1575 
1576  // Hyp Active Priorities Group 0 Registers
1577  case MISCREG_ICH_AP0R0:
1578  case MISCREG_ICH_AP0R0_EL2:
1579  break;
1580 
1581  // only implemented if supporting 6 or more bits of priority
1582  case MISCREG_ICH_AP0R1:
1583  case MISCREG_ICH_AP0R1_EL2:
1584  // only implemented if supporting 7 or more bits of priority
1585  case MISCREG_ICH_AP0R2:
1586  case MISCREG_ICH_AP0R2_EL2:
1587  // only implemented if supporting 7 or more bits of priority
1588  case MISCREG_ICH_AP0R3:
1589  case MISCREG_ICH_AP0R3_EL2:
1590  // Unimplemented registers are RAZ/WI
1591  return;
1592 
1593  // Hyp Active Priorities Group 1 Registers
1594  case MISCREG_ICH_AP1R0:
1595  case MISCREG_ICH_AP1R0_EL2:
1596  break;
1597 
1598  // only implemented if supporting 6 or more bits of priority
1599  case MISCREG_ICH_AP1R1:
1600  case MISCREG_ICH_AP1R1_EL2:
1601  // only implemented if supporting 7 or more bits of priority
1602  case MISCREG_ICH_AP1R2:
1603  case MISCREG_ICH_AP1R2_EL2:
1604  // only implemented if supporting 7 or more bits of priority
1605  case MISCREG_ICH_AP1R3:
1606  case MISCREG_ICH_AP1R3_EL2:
1607  // Unimplemented registers are RAZ/WI
1608  return;
1609 
1610  default:
1611  panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
1612  misc_reg, miscRegName[misc_reg]);
1613  }
1614 
1615  isa->setMiscRegNoEffect(misc_reg, val);
1616 
1617  if (do_virtual_update) {
1618  virtualUpdate();
1619  }
1620 }
1621 
1622 RegVal
1623 Gicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const
1624 {
1625  return isa->readMiscRegNoEffect(
1626  isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()));
1627 }
1628 
1629 void
1630 Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
1631 {
1632  isa->setMiscRegNoEffect(
1633  isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val);
1634 }
1635 
1636 int
1637 Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
1638 {
1639  for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1640  ICH_LR_EL2 ich_lr_el2 =
1641  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1642 
1643  if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1644  (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1645  (ich_lr_el2.vINTID == int_id)) {
1646  return lr_idx;
1647  }
1648  }
1649 
1650  return -1;
1651 }
1652 
1653 uint32_t
1654 Gicv3CPUInterface::getHPPIR0() const
1655 {
1656  if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1657  return Gicv3::INTID_SPURIOUS;
1658  }
1659 
1660  bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1661 
1662  if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1663  // interrupt for the other state pending
1664  return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE;
1665  }
1666 
1667  if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1668  return Gicv3::INTID_SPURIOUS;
1669  }
1670 
1671  if (irq_is_secure && !inSecureState()) {
1672  // Secure interrupts not visible in Non-secure
1673  return Gicv3::INTID_SPURIOUS;
1674  }
1675 
1676  return hppi.intid;
1677 }
1678 
1679 uint32_t
1680 Gicv3CPUInterface::getHPPIR1() const
1681 {
1682  if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1683  return Gicv3::INTID_SPURIOUS;
1684  }
1685 
1686  ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1687  if ((currEL() == EL3) && icc_ctlr_el3.RM) {
1688  if (hppi.group == Gicv3::G0S) {
1689  return Gicv3::INTID_SECURE;
1690  } else if (hppi.group == Gicv3::G1NS) {
1691  return Gicv3::INTID_NONSECURE;
1692  }
1693  }
1694 
1695  if (hppi.group == Gicv3::G0S) {
1696  return Gicv3::INTID_SPURIOUS;
1697  }
1698 
1699  bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1700 
1701  if (irq_is_secure) {
1702  if (!inSecureState()) {
1703  // Secure interrupts not visible in Non-secure
1704  return Gicv3::INTID_SPURIOUS;
1705  }
1706  } else if (!isEL3OrMon() && inSecureState()) {
1707  // Group 1 non-secure interrupts not visible in Secure EL1
1708  return Gicv3::INTID_SPURIOUS;
1709  }
1710 
1711  return hppi.intid;
1712 }
1713 
1714 void
1715 Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1716 {
1717  int apr_misc_reg = 0;
1718 
1719  switch (group) {
1720  case Gicv3::G0S:
1721  apr_misc_reg = MISCREG_ICC_AP0R0_EL1;
1722  break;
1723  case Gicv3::G1S:
1724  apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S;
1725  break;
1726  case Gicv3::G1NS:
1727  apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS;
1728  break;
1729  default:
1730  panic("Invalid Gicv3::GroupId");
1731  }
1732 
1733  RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
1734 
1735  if (apr) {
1736  apr &= apr - 1;
1737  isa->setMiscRegNoEffect(apr_misc_reg, apr);
1738  }
1739 
1740  update();
1741 }
1742 
1743 uint8_t
1744 Gicv3CPUInterface::virtualDropPriority()
1745 {
1746  int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1747 
1748  for (int i = 0; i < apr_max; i++) {
1749  RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1750  RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1751 
1752  if (!vapr0 && !vapr1) {
1753  continue;
1754  }
1755 
1756  int vapr0_count = ctz32(vapr0);
1757  int vapr1_count = ctz32(vapr1);
1758 
1759  if (vapr0_count <= vapr1_count) {
1760  vapr0 &= vapr0 - 1;
1761  isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
1762  return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
1763  } else {
1764  vapr1 &= vapr1 - 1;
1765  isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1766  return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
1767  }
1768  }
1769 
1770  return 0xff;
1771 }
1772 
1773 void
1774 Gicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group)
1775 {
1776  uint8_t aff3 = bits(val, 55, 48);
1777  uint8_t aff2 = bits(val, 39, 32);
1778  uint8_t aff1 = bits(val, 23, 16);;
1779  uint16_t target_list = bits(val, 15, 0);
1780  uint32_t int_id = bits(val, 27, 24);
1781  bool irm = bits(val, 40, 40);
1782  uint8_t rs = bits(val, 47, 44);
1783 
1784  bool ns = !inSecureState();
1785 
1786  for (int i = 0; i < gic->getSystem()->threads.size(); i++) {
1787  Gicv3Redistributor * redistributor_i =
1788  gic->getRedistributor(i);
1789  uint32_t affinity_i = redistributor_i->getAffinity();
1790 
1791  if (irm) {
1792  // Interrupts routed to all PEs in the system,
1793  // excluding "self"
1794  if (affinity_i == redistributor->getAffinity()) {
1795  continue;
1796  }
1797  } else {
1798  // Interrupts routed to the PEs specified by
1799  // Aff3.Aff2.Aff1.<target list>
1800  if ((affinity_i >> 8) !=
1801  ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
1802  continue;
1803  }
1804 
1805  uint8_t aff0_i = bits(affinity_i, 7, 0);
1806 
1807  if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
1808  ((0x1 << (aff0_i - rs * 16)) & target_list))) {
1809  continue;
1810  }
1811  }
1812 
1813  redistributor_i->sendSGI(int_id, group, ns);
1814  }
1815 }
1816 
1817 void
1818 Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1819 {
1820  // Update active priority registers.
1821  uint32_t prio = hppi.prio & 0xf8;
1822  int apr_bit = prio >> (8 - PRIORITY_BITS);
1823  int reg_bit = apr_bit % 32;
1824 
1825  int apr_idx = 0;
1826  switch (group) {
1827  case Gicv3::G0S:
1828  apr_idx = MISCREG_ICC_AP0R0_EL1;
1829  break;
1830  case Gicv3::G1S:
1831  apr_idx = MISCREG_ICC_AP1R0_EL1_S;
1832  break;
1833  case Gicv3::G1NS:
1834  apr_idx = MISCREG_ICC_AP1R0_EL1_NS;
1835  break;
1836  default:
1837  panic("Invalid Gicv3::GroupId");
1838  }
1839 
1840  RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1841  apr |= (1 << reg_bit);
1842  isa->setMiscRegNoEffect(apr_idx, apr);
1843 
1844  // Move interrupt state from pending to active.
1845  if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1846  // SGI or PPI, redistributor
1847  redistributor->activateIRQ(int_id);
1848  } else if (int_id < Gicv3::INTID_SECURE) {
1849  // SPI, distributor
1850  distributor->activateIRQ(int_id);
1851  } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
1852  // LPI, Redistributor
1853  redistributor->setClrLPI(int_id, false);
1854  }
1855 
1856  // By setting the priority to 0xff we are effectively
1857  // making the int_id not pending anymore at the cpu
1858  // interface.
1859  resetHppi(int_id);
1860  updateDistributor();
1861 }
1862 
1863 void
1864 Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1865 {
1866  // Update active priority registers.
1867  ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1868  lr_idx);
1869  Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S;
1870  uint8_t prio = ich_lr_el.Priority & 0xf8;
1871  int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1872  int reg_no = apr_bit / 32;
1873  int reg_bit = apr_bit % 32;
1874  int apr_idx = group == Gicv3::G0S ?
1875  MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1876  RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1877  apr |= (1 << reg_bit);
1878  isa->setMiscRegNoEffect(apr_idx, apr);
1879  // Move interrupt state from pending to active.
1880  ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1881  isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1882 }
1883 
1884 void
1885 Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
1886 {
1887  if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1888  // SGI or PPI, redistributor
1889  redistributor->deactivateIRQ(int_id);
1890  } else if (int_id < Gicv3::INTID_SECURE) {
1891  // SPI, distributor
1892  distributor->deactivateIRQ(int_id);
1893  }
1894 
1895  updateDistributor();
1896 }
1897 
1898 void
1899 Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1900 {
1901  ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1902  lr_idx);
1903 
1904  if (ich_lr_el2.HW) {
1905  // Deactivate the associated physical interrupt
1906  if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) {
1907  Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ?
1908  distributor->getIntGroup(ich_lr_el2.pINTID) :
1909  redistributor->getIntGroup(ich_lr_el2.pINTID);
1910  deactivateIRQ(ich_lr_el2.pINTID, group);
1911  }
1912  }
1913 
1914  // Remove the active bit
1915  ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
1916  isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1917 }
1918 
1919 /*
1920  * Returns the priority group field for the current BPR value for the group.
1921  * GroupBits() Pseudocode from spec.
1922  */
1923 uint32_t
1924 Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
1925 {
1926  ICC_CTLR_EL1 icc_ctlr_el1_s =
1927  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1928  ICC_CTLR_EL1 icc_ctlr_el1_ns =
1929  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1930 
1931  if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1932  (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1933  group = Gicv3::G0S;
1934  }
1935 
1936  int bpr;
1937 
1938  if (group == Gicv3::G0S) {
1939  bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
1940  } else if (group == Gicv3::G1S) {
1941  bpr = bpr1(Gicv3::G1S) & 0x7;
1942  } else {
1943  bpr = bpr1(Gicv3::G1NS) & 0x7;
1944  }
1945 
1946  if (group == Gicv3::G1NS) {
1947  assert(bpr > 0);
1948  bpr--;
1949  }
1950 
1951  return ~0U << (bpr + 1);
1952 }
1953 
1954 uint32_t
1955 Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
1956 {
1957  ICH_VMCR_EL2 ich_vmcr_el2 =
1958  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1959 
1960  if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) {
1961  group = Gicv3::G0S;
1962  }
1963 
1964  int bpr;
1965 
1966  if (group == Gicv3::G0S) {
1967  bpr = ich_vmcr_el2.VBPR0;
1968  } else {
1969  bpr = ich_vmcr_el2.VBPR1;
1970  }
1971 
1972  if (group == Gicv3::G1NS) {
1973  assert(bpr > 0);
1974  bpr--;
1975  }
1976 
1977  return ~0U << (bpr + 1);
1978 }
1979 
1980 bool
1981 Gicv3CPUInterface::isEOISplitMode() const
1982 {
1983  if (isEL3OrMon()) {
1984  ICC_CTLR_EL3 icc_ctlr_el3 =
1985  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1986  return icc_ctlr_el3.EOImode_EL3;
1987  } else {
1988  ICC_CTLR_EL1 icc_ctlr_el1 = 0;
1989  if (inSecureState())
1990  icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1991  else
1992  icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1993  return icc_ctlr_el1.EOImode;
1994  }
1995 }
1996 
1997 bool
1998 Gicv3CPUInterface::virtualIsEOISplitMode() const
1999 {
2000  ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2001  return ich_vmcr_el2.VEOIM;
2002 }
2003 
2004 int
2005 Gicv3CPUInterface::highestActiveGroup() const
2006 {
2007  int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
2008  int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
2009  int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS));
2010 
2011  if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) {
2012  return Gicv3::G1NS;
2013  }
2014 
2015  if (gq_ctz < g0_ctz) {
2016  return Gicv3::G1S;
2017  }
2018 
2019  if (g0_ctz < 32) {
2020  return Gicv3::G0S;
2021  }
2022 
2023  return -1;
2024 }
2025 
2026 void
2027 Gicv3CPUInterface::updateDistributor()
2028 {
2029  distributor->update();
2030 }
2031 
2032 void
2033 Gicv3CPUInterface::update()
2034 {
2035  if (gic->blockIntUpdate())
2036  return;
2037 
2038  bool signal_IRQ = false;
2039  bool signal_FIQ = false;
2040 
2041  if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
2042  /*
2043  * Secure enabled GIC sending a G1S IRQ to a secure disabled
2044  * CPU -> send G0 IRQ
2045  */
2046  hppi.group = Gicv3::G0S;
2047  }
2048 
2049  if (hppiCanPreempt()) {
2050  InterruptTypes int_type = intSignalType(hppi.group);
2051  DPRINTF(GIC, "Gicv3CPUInterface::update(): "
2052  "posting int as %d!\n", int_type);
2053  int_type == INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
2054  }
2055 
2056  if (signal_IRQ) {
2057  gic->postInt(cpuId, INT_IRQ);
2058  } else {
2059  gic->deassertInt(cpuId, INT_IRQ);
2060  }
2061 
2062  if (signal_FIQ) {
2063  gic->postInt(cpuId, INT_FIQ);
2064  } else {
2065  gic->deassertInt(cpuId, INT_FIQ);
2066  }
2067 }
2068 
2069 void
2070 Gicv3CPUInterface::virtualUpdate()
2071 {
2072  if (gic->blockIntUpdate())
2073  return;
2074 
2075  bool signal_IRQ = false;
2076  bool signal_FIQ = false;
2077  int lr_idx = getHPPVILR();
2078 
2079  if (lr_idx >= 0) {
2080  ICH_LR_EL2 ich_lr_el2 =
2081  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2082 
2083  if (hppviCanPreempt(lr_idx)) {
2084  if (ich_lr_el2.Group) {
2085  signal_IRQ = true;
2086  } else {
2087  signal_FIQ = true;
2088  }
2089  }
2090  }
2091 
2092  ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2093 
2094  const bool maint_pending = redistributor->irqPending[
2095  maintenanceInterrupt->num()];
2096 
2097  if (ich_hcr_el2.En && !maint_pending && maintenanceInterruptStatus()) {
2098  maintenanceInterrupt->raise();
2099  } else if (maint_pending) {
2100  maintenanceInterrupt->clear();
2101  }
2102 
2103  if (signal_IRQ) {
2104  DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2105  "posting int as %d!\n", INT_VIRT_IRQ);
2106  gic->postInt(cpuId, INT_VIRT_IRQ);
2107  } else {
2108  gic->deassertInt(cpuId, INT_VIRT_IRQ);
2109  }
2110 
2111  if (signal_FIQ) {
2112  DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
2113  "posting int as %d!\n", INT_VIRT_FIQ);
2114  gic->postInt(cpuId, INT_VIRT_FIQ);
2115  } else {
2116  gic->deassertInt(cpuId, INT_VIRT_FIQ);
2117  }
2118 }
2119 
2120 // Returns the index of the LR with the HPPI
2121 int
2122 Gicv3CPUInterface::getHPPVILR() const
2123 {
2124  int idx = -1;
2125  ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2126 
2127  if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) {
2128  // VG0 and VG1 disabled...
2129  return idx;
2130  }
2131 
2132  uint8_t highest_prio = 0xff;
2133 
2134  for (int i = 0; i < 16; i++) {
2135  ICH_LR_EL2 ich_lr_el2 =
2136  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2137 
2138  if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2139  continue;
2140  }
2141 
2142  if (ich_lr_el2.Group) {
2143  // VG1
2144  if (!ich_vmcr_el2.VENG1) {
2145  continue;
2146  }
2147  } else {
2148  // VG0
2149  if (!ich_vmcr_el2.VENG0) {
2150  continue;
2151  }
2152  }
2153 
2154  uint8_t prio = ich_lr_el2.Priority;
2155 
2156  if (prio < highest_prio) {
2157  highest_prio = prio;
2158  idx = i;
2159  }
2160  }
2161 
2162  return idx;
2163 }
2164 
2165 bool
2166 Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
2167 {
2168  ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2169  if (!ich_hcr_el2.En) {
2170  // virtual interface is disabled
2171  return false;
2172  }
2173 
2174  ICH_LR_EL2 ich_lr_el2 =
2175  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2176  uint8_t prio = ich_lr_el2.Priority;
2177  uint8_t vpmr =
2178  bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2179 
2180  if (prio >= vpmr) {
2181  // prioriry masked
2182  return false;
2183  }
2184 
2185  uint8_t rprio = virtualHighestActivePriority();
2186 
2187  if (rprio == 0xff) {
2188  return true;
2189  }
2190 
2191  Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S;
2192  uint32_t prio_mask = virtualGroupPriorityMask(group);
2193 
2194  if ((prio & prio_mask) < (rprio & prio_mask)) {
2195  return true;
2196  }
2197 
2198  return false;
2199 }
2200 
2201 uint8_t
2202 Gicv3CPUInterface::virtualHighestActivePriority() const
2203 {
2204  uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2205 
2206  for (int i = 0; i < num_aprs; i++) {
2207  RegVal vapr =
2208  isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2209  isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2210 
2211  if (!vapr) {
2212  continue;
2213  }
2214 
2215  return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2216  }
2217 
2218  // no active interrups, return idle priority
2219  return 0xff;
2220 }
2221 
2222 void
2223 Gicv3CPUInterface::virtualIncrementEOICount()
2224 {
2225  // Increment the EOICOUNT field in ICH_HCR_EL2
2226  RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2227  uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2228  EOI_cout++;
2229  ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2230  isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2231 }
2232 
2233 // spec section 4.6.2
2234 InterruptTypes
2235 Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
2236 {
2237  bool is_fiq = false;
2238 
2239  switch (group) {
2240  case Gicv3::G0S:
2241  is_fiq = true;
2242  break;
2243 
2244  case Gicv3::G1S:
2245  is_fiq = (distributor->DS == 0) &&
2246  (!inSecureState() || ((currEL() == EL3) && isAA64()));
2247  break;
2248 
2249  case Gicv3::G1NS:
2250  is_fiq = (distributor->DS == 0) && inSecureState();
2251  break;
2252 
2253  default:
2254  panic("Gicv3CPUInterface::intSignalType(): invalid group!");
2255  }
2256 
2257  if (is_fiq) {
2258  return INT_FIQ;
2259  } else {
2260  return INT_IRQ;
2261  }
2262 }
2263 
2264 bool
2265 Gicv3CPUInterface::hppiCanPreempt()
2266 {
2267  if (hppi.prio == 0xff) {
2268  // there is no pending interrupt
2269  return false;
2270  }
2271 
2272  if (!groupEnabled(hppi.group)) {
2273  // group disabled at CPU interface
2274  return false;
2275  }
2276 
2277  if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2278  // priority masked
2279  return false;
2280  }
2281 
2282  uint8_t rprio = highestActivePriority();
2283 
2284  if (rprio == 0xff) {
2285  return true;
2286  }
2287 
2288  uint32_t prio_mask = groupPriorityMask(hppi.group);
2289 
2290  if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2291  return true;
2292  }
2293 
2294  return false;
2295 }
2296 
2297 uint8_t
2298 Gicv3CPUInterface::highestActivePriority() const
2299 {
2300  uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
2301  isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
2302  isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
2303 
2304  if (apr) {
2305  return ctz32(apr) << (GIC_MIN_BPR + 1);
2306  }
2307 
2308  // no active interrups, return idle priority
2309  return 0xff;
2310 }
2311 
2312 bool
2313 Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
2314 {
2315  switch (group) {
2316  case Gicv3::G0S: {
2317  ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
2318  isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
2319  return icc_igrpen0_el1.Enable && distributor->EnableGrp0;
2320  }
2321 
2322  case Gicv3::G1S: {
2323  ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
2324  isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
2325  return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S;
2326  }
2327 
2328  case Gicv3::G1NS: {
2329  ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
2330  isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
2331  return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS;
2332  }
2333 
2334  default:
2335  panic("Gicv3CPUInterface::groupEnable(): invalid group!\n");
2336  }
2337 }
2338 
2339 bool
2340 Gicv3CPUInterface::inSecureState() const
2341 {
2342  return isa->inSecureState();
2343 }
2344 
2345 ExceptionLevel
2346 Gicv3CPUInterface::currEL() const
2347 {
2348  return isa->currEL();
2349 }
2350 
2351 bool
2352 Gicv3CPUInterface::haveEL(ExceptionLevel el) const
2353 {
2354  switch (el) {
2355  case EL0:
2356  case EL1:
2357  return true;
2358 
2359  case EL2:
2360  return gic->getSystem()->has(ArmExtension::VIRTUALIZATION);
2361 
2362  case EL3:
2363  return gic->getSystem()->has(ArmExtension::SECURITY);
2364 
2365  default:
2366  warn("Unimplemented Exception Level\n");
2367  return false;
2368  }
2369 }
2370 
2371 bool
2372 Gicv3CPUInterface::isSecureBelowEL3() const
2373 {
2374  SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2375  return haveEL(EL3) && scr.ns == 0;
2376 }
2377 
2378 bool
2379 Gicv3CPUInterface::isAA64() const
2380 {
2381  CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2382  return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2383 }
2384 
2385 bool
2386 Gicv3CPUInterface::isEL3OrMon() const
2387 {
2388  if (haveEL(EL3)) {
2389  CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2390  bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2391 
2392  if (is_64 && (cpsr.el == EL3)) {
2393  return true;
2394  } else if (!is_64 && (cpsr.mode == MODE_MON)) {
2395  return true;
2396  }
2397  }
2398 
2399  return false;
2400 }
2401 
2402 // Computes ICH_EISR_EL2
2403 uint64_t
2404 Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const
2405 {
2406  // ICH_EISR_EL2
2407  // Bits [63:16] - RES0
2408  // Status<n>, bit [n], for n = 0 to 15
2409  // EOI maintenance interrupt status bit for List register <n>:
2410  // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI
2411  // maintenance interrupt.
2412  // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance
2413  // interrupt that has not been handled.
2414  //
2415  // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all
2416  // of the following are true:
2417  // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2418  // - ICH_LR<n>_EL2.HW is 0.
2419  // - ICH_LR<n>_EL2.EOI (bit [41]) is 1.
2420 
2421  uint64_t value = 0;
2422 
2423  for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2424  ICH_LR_EL2 ich_lr_el2 =
2425  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2426 
2427  if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2428  !ich_lr_el2.HW && ich_lr_el2.EOI) {
2429  value |= (1 << lr_idx);
2430  }
2431  }
2432 
2433  return value;
2434 }
2435 
2436 Gicv3CPUInterface::ICH_MISR_EL2
2437 Gicv3CPUInterface::maintenanceInterruptStatus() const
2438 {
2439  // Comments are copied from SPEC section 9.4.7 (ID012119)
2440  ICH_MISR_EL2 ich_misr_el2 = 0;
2441  ICH_HCR_EL2 ich_hcr_el2 =
2442  isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2443  ICH_VMCR_EL2 ich_vmcr_el2 =
2444  isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2445 
2446  // End Of Interrupt. [bit 0]
2447  // This maintenance interrupt is asserted when at least one bit in
2448  // ICH_EISR_EL2 is 1.
2449 
2450  if (eoiMaintenanceInterruptStatus()) {
2451  ich_misr_el2.EOI = 1;
2452  }
2453 
2454  // Underflow. [bit 1]
2455  // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and
2456  // zero or one of the List register entries are marked as a valid
2457  // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2458  // do not equal 0x0.
2459  uint32_t num_valid_interrupts = 0;
2460  uint32_t num_pending_interrupts = 0;
2461 
2462  for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2463  ICH_LR_EL2 ich_lr_el2 =
2464  isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2465 
2466  if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2467  num_valid_interrupts++;
2468  }
2469 
2470  if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {
2471  num_pending_interrupts++;
2472  }
2473  }
2474 
2475  if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) {
2476  ich_misr_el2.U = 1;
2477  }
2478 
2479  // List Register Entry Not Present. [bit 2]
2480  // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1
2481  // and ICH_HCR_EL2.EOIcount is non-zero.
2482  if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) {
2483  ich_misr_el2.LRENP = 1;
2484  }
2485 
2486  // No Pending. [bit 3]
2487  // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and
2488  // no List register is in pending state.
2489  if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) {
2490  ich_misr_el2.NP = 1;
2491  }
2492 
2493  // vPE Group 0 Enabled. [bit 4]
2494  // This maintenance interrupt is asserted when
2495  // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.
2496  if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) {
2497  ich_misr_el2.VGrp0E = 1;
2498  }
2499 
2500  // vPE Group 0 Disabled. [bit 5]
2501  // This maintenance interrupt is asserted when
2502  // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.
2503  if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) {
2504  ich_misr_el2.VGrp0D = 1;
2505  }
2506 
2507  // vPE Group 1 Enabled. [bit 6]
2508  // This maintenance interrupt is asserted when
2509  // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.
2510  if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) {
2511  ich_misr_el2.VGrp1E = 1;
2512  }
2513 
2514  // vPE Group 1 Disabled. [bit 7]
2515  // This maintenance interrupt is asserted when
2516  // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.
2517  if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) {
2518  ich_misr_el2.VGrp1D = 1;
2519  }
2520 
2521  return ich_misr_el2;
2522 }
2523 
2524 RegVal
2525 Gicv3CPUInterface::bpr1(Gicv3::GroupId group)
2526 {
2527  bool hcr_imo = getHCREL2IMO();
2528  if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
2529  return readMiscReg(MISCREG_ICV_BPR1_EL1);
2530  }
2531 
2532  RegVal bpr = 0;
2533 
2534  if (group == Gicv3::G1S) {
2535  ICC_CTLR_EL1 icc_ctlr_el1_s =
2536  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
2537 
2538  if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) {
2539  bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
2540  } else {
2541  bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S);
2542  bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR;
2543  }
2544  } else if (group == Gicv3::G1NS) {
2545  ICC_CTLR_EL1 icc_ctlr_el1_ns =
2546  isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
2547 
2548  // Check if EL3 is implemented and this is a non secure accesses at
2549  // EL1 and EL2
2550  if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) {
2551  // Reads return BPR0 + 1 saturated to 7, WI
2552  bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1;
2553  bpr = bpr < 7 ? bpr : 7;
2554  } else {
2555  bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS);
2556  bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS;
2557  }
2558  } else {
2559  panic("Should be used with G1S and G1NS only\n");
2560  }
2561 
2562  return bpr;
2563 }
2564 
2565 bool
2566 Gicv3CPUInterface::havePendingInterrupts() const
2567 {
2568  return gic->haveAsserted(cpuId) || hppi.prio != 0xff;
2569 }
2570 
2571 void
2572 Gicv3CPUInterface::clearPendingInterrupts()
2573 {
2574  gic->deassertAll(cpuId);
2575  resetHppi(hppi.intid);
2576 }
2577 
2578 void
2579 Gicv3CPUInterface::assertWakeRequest()
2580 {
2581  auto *tc = gic->getSystem()->threads[cpuId];
2582  if (ArmSystem::callSetWakeRequest(tc)) {
2583  Reset().invoke(tc);
2584  tc->activate();
2585  }
2586 }
2587 
2588 void
2589 Gicv3CPUInterface::deassertWakeRequest()
2590 {
2591  auto *tc = gic->getSystem()->threads[cpuId];
2592  ArmSystem::callClearWakeRequest(tc);
2593 }
2594 
2595 void
2596 Gicv3CPUInterface::copy(Gicv3Registers *from, Gicv3Registers *to)
2597 {
2598  const auto affinity = redistributor->getAffinity();
2599  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_PMR_EL1);
2600 
2601  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_AP1R0_EL1);
2602  if (PRIORITY_BITS >= 6) {
2603  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_AP1R1_EL1);
2604  }
2605 
2606  if (PRIORITY_BITS >= 7) {
2607  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_AP1R2_EL1);
2608  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_AP1R3_EL1);
2609  }
2610 
2611  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_BPR1_EL1);
2612  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_CTLR_EL1);
2613  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_SRE_EL1);
2614  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_IGRPEN0_EL1);
2615  gic->copyCpuRegister(from, to, affinity, MISCREG_ICC_IGRPEN1_EL1);
2616 }
2617 
2618 void
2619 Gicv3CPUInterface::serialize(CheckpointOut & cp) const
2620 {
2621  SERIALIZE_SCALAR(hppi.intid);
2622  SERIALIZE_SCALAR(hppi.prio);
2623  SERIALIZE_ENUM(hppi.group);
2624 }
2625 
2626 void
2627 Gicv3CPUInterface::unserialize(CheckpointIn & cp)
2628 {
2629  UNSERIALIZE_SCALAR(hppi.intid);
2630  UNSERIALIZE_SCALAR(hppi.prio);
2631  UNSERIALIZE_ENUM(hppi.group);
2632 }
2633 
2634 } // namespace gem5
gem5::Gicv3::G1NS
@ G1NS
Definition: gic_v3.hh:137
gem5::Gicv3::GroupId
GroupId
Definition: gic_v3.hh:133
gic_v3_cpu_interface.hh
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::Gicv3CPUInterface::groupEnabled
bool groupEnabled(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:2313
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS
@ MISCREG_ICC_CTLR_EL1_NS
Definition: misc.hh:871
gem5::ArmISA::MISCREG_ICV_EOIR0_EL1
@ MISCREG_ICV_EOIR0_EL1
Definition: misc.hh:919
gem5::ArmISA::MISCREG_ICC_CTLR_EL3
@ MISCREG_ICC_CTLR_EL3
Definition: misc.hh:881
gem5::ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition: misc.hh:888
gem5::Gicv3::INTID_NONSECURE
static const int INTID_NONSECURE
Definition: gic_v3.hh:115
gem5::Gicv3CPUInterface::highestActivePriority
uint8_t highestActivePriority() const
Definition: gic_v3_cpu_interface.cc:2298
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS
@ MISCREG_ICC_AP1R0_EL1_NS
Definition: misc.hh:848
gem5::ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition: misc.hh:846
gem5::ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition: misc.hh:989
gem5::Gicv3CPUInterface::setThreadContext
void setThreadContext(ThreadContext *tc) override
Definition: gic_v3_cpu_interface.cc:84
gem5::BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:114
gem5::ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition: misc.hh:842
gem5::ArmISA::ISA::currEL
ExceptionLevel currEL() const
Returns the current Exception Level (EL) of the ISA object.
Definition: isa.cc:2067
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::MISCREG_ICC_IAR0_EL1
@ MISCREG_ICC_IAR0_EL1
Definition: misc.hh:839
gem5::Gicv3CPUInterface::virtualHighestActivePriority
uint8_t virtualHighestActivePriority() const
Definition: gic_v3_cpu_interface.cc:2202
warn
#define warn(...)
Definition: logging.hh:246
gem5::Gicv3::getRedistributor
Gicv3Redistributor * getRedistributor(ContextID context_id) const
Definition: gic_v3.hh:191
gem5::ArmISA::MISCREG_ICC_EOIR1
@ MISCREG_ICC_EOIR1
Definition: misc.hh:986
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S
@ MISCREG_ICC_CTLR_EL1_S
Definition: misc.hh:872
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gic_v3_redistributor.hh
gem5::ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition: misc.hh:973
gem5::Gicv3CPUInterface::maintenanceInterrupt
ArmInterruptPin * maintenanceInterrupt
Definition: gic_v3_cpu_interface.hh:73
gem5::Gicv3Registers
Definition: gic_v3.hh:57
gem5::ArmISA::MISCREG_ICH_AP0R3_EL2
@ MISCREG_ICH_AP0R3_EL2
Definition: misc.hh:889
gem5::ps2::Reset
@ Reset
Definition: types.hh:70
gem5::Gicv3::haveAsserted
bool haveAsserted(uint32_t cpu) const
Definition: gic_v3.cc:311
gem5::ArmISA::MISCREG_ICV_AP0R0_EL1
@ MISCREG_ICV_AP0R0_EL1
Definition: misc.hh:922
gem5::ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:753
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::ArmISA::MISCREG_ICH_AP1R0_EL2
@ MISCREG_ICH_AP1R0_EL2
Definition: misc.hh:890
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_ICH_EISR
@ MISCREG_ICH_EISR
Definition: misc.hh:1018
gem5::Gicv3CPUInterface::currEL
ArmISA::ExceptionLevel currEL() const
Definition: gic_v3_cpu_interface.cc:2346
gem5::Gicv3CPUInterface::distributor
Gicv3Distributor * distributor
Definition: gic_v3_cpu_interface.hh:70
gem5::Gicv3::getDistributor
Gicv3Distributor * getDistributor() const
Definition: gic_v3.hh:185
gem5::ArmISA::MISCREG_ICH_MISR_EL2
@ MISCREG_ICH_MISR_EL2
Definition: misc.hh:896
gem5::ArmISA::MISCREG_ICC_IAR1
@ MISCREG_ICC_IAR1
Definition: misc.hh:991
gem5::Gicv3CPUInterface::isAA64
bool isAA64() const
Definition: gic_v3_cpu_interface.cc:2379
gem5::Gicv3CPUInterface::redistributor
Gicv3Redistributor * redistributor
Definition: gic_v3_cpu_interface.hh:69
gem5::Gicv3Redistributor
Definition: gic_v3_redistributor.hh:55
gem5::Gicv3CPUInterface::deassertWakeRequest
void deassertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2589
gem5::Gicv3CPUInterface::GIC_MIN_VBPR
static const uint8_t GIC_MIN_VBPR
Definition: gic_v3_cpu_interface.hh:161
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:594
gem5::ArmISA::MISCREG_ICC_EOIR0_EL1
@ MISCREG_ICC_EOIR0_EL1
Definition: misc.hh:840
gem5::ArmISA::MISCREG_ICH_AP0R1_EL2
@ MISCREG_ICH_AP0R1_EL2
Definition: misc.hh:887
gem5::ArmISA::MISCREG_ICV_IAR0_EL1
@ MISCREG_ICV_IAR0_EL1
Definition: misc.hh:918
gem5::CheckpointIn
Definition: serialize.hh:68
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::Gicv3CPUInterface::readBankedMiscReg
RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const
Definition: gic_v3_cpu_interface.cc:1623
gem5::ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition: misc.hh:860
gem5::ArmISA::MISCREG_ICH_LR0
@ MISCREG_ICH_LR0
Definition: misc.hh:1021
gem5::ArmISA::MISCREG_ICC_SRE_EL3
@ MISCREG_ICC_SRE_EL3
Definition: misc.hh:882
gem5::Gicv3CPUInterface::virtualGroupPriorityMask
uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:1955
gem5::ArmSystem::callClearWakeRequest
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:222
gem5::Gicv3CPUInterface::dropPriority
void dropPriority(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1715
gem5::ArmISA::INT_VIRT_FIQ
@ INT_VIRT_FIQ
Definition: interrupts.hh:67
gem5::ArmInterruptPin::num
uint32_t num() const
Get interrupt number.
Definition: base_gic.hh:216
gem5::ArmISA::INT_FIQ
@ INT_FIQ
Definition: interrupts.hh:64
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::Gicv3::deassertAll
void deassertAll(uint32_t cpu)
Definition: gic_v3.cc:304
gem5::Gicv3CPUInterface::getHPPVILR
int getHPPVILR() const
Definition: gic_v3_cpu_interface.cc:2122
gem5::Gicv3::PPI_MAX
static const int PPI_MAX
Definition: gic_v3.hh:121
gem5::ArmISA::INT_VIRT_IRQ
@ INT_VIRT_IRQ
Definition: interrupts.hh:66
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: misc.hh:861
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1273
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:332
gem5::Gicv3Distributor::update
void update()
Definition: gic_v3_distributor.cc:1086
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::Gicv3Redistributor::irqPending
std::vector< bool > irqPending
Definition: gic_v3_redistributor.hh:161
gem5::ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition: misc.hh:993
gem5::ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition: misc.hh:997
gem5::ArmISA::MISCREG_ICH_AP1R2
@ MISCREG_ICH_AP1R2
Definition: misc.hh:1013
gem5::Gicv3CPUInterface::clearPendingInterrupts
void clearPendingInterrupts(void)
Definition: gic_v3_cpu_interface.cc:2572
gem5::Gicv3CPUInterface::update
void update()
Definition: gic_v3_cpu_interface.cc:2033
gem5::ArmISA::MISCREG_ICC_PMR
@ MISCREG_ICC_PMR
Definition: misc.hh:999
gem5::ArmISA::MISCREG_ICV_IGRPEN0_EL1
@ MISCREG_ICV_IGRPEN0_EL1
Definition: misc.hh:955
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:915
gem5::Gicv3CPUInterface::hppiCanPreempt
bool hppiCanPreempt()
Definition: gic_v3_cpu_interface.cc:2265
gem5::ArmISA::MISCREG_ICC_EOIR0
@ MISCREG_ICC_EOIR0
Definition: misc.hh:985
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_ICH_AP0R0
@ MISCREG_ICH_AP0R0
Definition: misc.hh:1007
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: misc.hh:960
gem5::Gicv3Distributor::EnableGrp1NS
bool EnableGrp1NS
Definition: gic_v3_distributor.hh:155
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition: misc.hh:849
gem5::Gicv3CPUInterface::resetHppi
void resetHppi(uint32_t intid)
Definition: gic_v3_cpu_interface.cc:77
gem5::Gicv3CPUInterface::VIRTUAL_NUM_LIST_REGS
static const uint8_t VIRTUAL_NUM_LIST_REGS
Definition: gic_v3_cpu_interface.hh:159
gem5::Gicv3Redistributor::getIntGroup
Gicv3::GroupId getIntGroup(int int_id) const
Definition: gic_v3_redistributor.cc:973
gem5::Gicv3Distributor::activateIRQ
void activateIRQ(uint32_t int_id)
Definition: gic_v3_distributor.cc:1170
gem5::ArmISA::MISCREG_ICV_PMR_EL1
@ MISCREG_ICV_PMR_EL1
Definition: misc.hh:917
gem5::ArmISA::MISCREG_ICC_AP1R1
@ MISCREG_ICC_AP1R1
Definition: misc.hh:967
gem5::Gicv3CPUInterface::init
void init()
Definition: gic_v3_cpu_interface.cc:70
gem5::ArmISA::MISCREG_ICH_VTR_EL2
@ MISCREG_ICH_VTR_EL2
Definition: misc.hh:895
gem5::Gicv3CPUInterface::eoiMaintenanceInterruptStatus
uint64_t eoiMaintenanceInterruptStatus() const
Definition: gic_v3_cpu_interface.cc:2404
gem5::ArmISA::BaseISADevice::isa
ISA * isa
Definition: isa_device.hh:87
gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1
@ MISCREG_ICC_HPPIR0_EL1
Definition: misc.hh:841
gem5::Gicv3CPUInterface::havePendingInterrupts
bool havePendingInterrupts(void) const
Definition: gic_v3_cpu_interface.cc:2566
gem5::ArmISA::MISCREG_ICV_HPPIR1_EL1
@ MISCREG_ICV_HPPIR1_EL1
Definition: misc.hh:945
gem5::ArmISA::MISCREG_ICH_AP0R2
@ MISCREG_ICH_AP0R2
Definition: misc.hh:1009
gem5::ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:1089
gem5::ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition: misc.hh:992
gem5::Gicv3::postInt
void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:282
gem5::Gicv3CPUInterface::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3_cpu_interface.cc:2627
gem5::ArmISA::MISCREG_ICV_HPPIR0_EL1
@ MISCREG_ICV_HPPIR0_EL1
Definition: misc.hh:920
SERIALIZE_ENUM
#define SERIALIZE_ENUM(scalar)
Definition: serialize.hh:591
gem5::ArmISA::MISCREG_ICC_HPPIR1
@ MISCREG_ICC_HPPIR1
Definition: misc.hh:988
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition: misc_types.hh:175
gem5::Gicv3Distributor::DS
bool DS
Definition: gic_v3_distributor.hh:153
gem5::ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition: misc.hh:1037
gem5::PowerISA::to
Bitfield< 25, 21 > to
Definition: types.hh:96
gem5::BaseGic::blockIntUpdate
virtual bool blockIntUpdate() const
When trasferring the state between two GICs (essentially writing architectural registers) an interrup...
Definition: base_gic.hh:130
gem5::ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition: misc.hh:1012
gem5::Gicv3CPUInterface::isEL3OrMon
bool isEL3OrMon() const
Definition: gic_v3_cpu_interface.cc:2386
gem5::Gicv3CPUInterface::isEOISplitMode
bool isEOISplitMode() const
Definition: gic_v3_cpu_interface.cc:1981
gem5::ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition: misc.hh:894
gem5::Gicv3CPUInterface::generateSGI
EndBitUnion(ICV_CTLR_EL1) protected void generateSGI(RegVal val, Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1774
gem5::Gicv3CPUInterface::virtualUpdate
void virtualUpdate()
Definition: gic_v3_cpu_interface.cc:2070
gem5::ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition: misc.hh:996
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition: misc.hh:847
gem5::ArmISA::MISCREG_ICH_LR0_EL2
@ MISCREG_ICH_LR0_EL2
Definition: misc.hh:900
gem5::ArmISA::MISCREG_ICH_AP1R0
@ MISCREG_ICH_AP1R0
Definition: misc.hh:1011
gem5::Gicv3CPUInterface::gic
Gicv3 * gic
Definition: gic_v3_cpu_interface.hh:68
gem5::ArmISA::MISCREG_ICC_MSRE
@ MISCREG_ICC_MSRE
Definition: misc.hh:998
gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_PENDING
static const uint64_t ICH_LR_EL2_STATE_PENDING
Definition: gic_v3_cpu_interface.hh:240
gem5::ArmISA::MISCREG_ICC_AP0R1_EL1
@ MISCREG_ICC_AP0R1_EL1
Definition: misc.hh:844
gem5::ArmISA::MISCREG_ICV_DIR_EL1
@ MISCREG_ICV_DIR_EL1
Definition: misc.hh:938
gem5::Gicv3CPUInterface::highestActiveGroup
int highestActiveGroup() const
Definition: gic_v3_cpu_interface.cc:2005
gem5::Gicv3::INT_PENDING
@ INT_PENDING
Definition: gic_v3.hh:127
gem5::ArmISA::MISCREG_ICC_DIR_EL1
@ MISCREG_ICC_DIR_EL1
Definition: misc.hh:859
gem5::Gicv3Distributor::getIntGroup
Gicv3::GroupId getIntGroup(int int_id) const
Definition: gic_v3_distributor.cc:1143
gem5::ArmISA::MISCREG_ICH_VTR
@ MISCREG_ICH_VTR
Definition: misc.hh:1016
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: misc.hh:1052
gem5::X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1051
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Gicv3CPUInterface::hppviCanPreempt
bool hppviCanPreempt(int lrIdx) const
Definition: gic_v3_cpu_interface.cc:2166
gem5::ArmISA::MISCREG_ICV_RPR_EL1
@ MISCREG_ICV_RPR_EL1
Definition: misc.hh:939
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::ISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, bool ns) const
Definition: isa.hh:863
gem5::Gicv3CPUInterface::GIC_MIN_BPR_NS
static const uint8_t GIC_MIN_BPR_NS
Definition: gic_v3_cpu_interface.hh:155
isa.hh
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
gem5::Gicv3CPUInterface::intSignalType
ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:2235
gem5::Gicv3CPUInterface::hppi_t::intid
uint32_t intid
Definition: gic_v3_cpu_interface.hh:165
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: misc.hh:862
gem5::Gicv3CPUInterface::isSecureBelowEL3
bool isSecureBelowEL3() const
Definition: gic_v3_cpu_interface.cc:2372
gem5::ArmISA::MISCREG_ICH_AP0R1
@ MISCREG_ICH_AP0R1
Definition: misc.hh:1008
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:883
gem5::Gicv3::INTID_SPURIOUS
static const int INTID_SPURIOUS
Definition: gic_v3.hh:116
gem5::Gicv3CPUInterface::copy
void copy(Gicv3Registers *from, Gicv3Registers *to)
Definition: gic_v3_cpu_interface.cc:2596
gem5::ArmISA::MISCREG_ICH_AP1R1_EL2
@ MISCREG_ICH_AP1R1_EL2
Definition: misc.hh:891
gem5::Gicv3CPUInterface::virtualDeactivateIRQ
void virtualDeactivateIRQ(int lrIdx)
Definition: gic_v3_cpu_interface.cc:1899
gem5::ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition: misc.hh:1019
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition: misc.hh:868
gem5::ArmISA::MISCREG_ICC_EOIR1_EL1
@ MISCREG_ICC_EOIR1_EL1
Definition: misc.hh:865
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: misc.hh:976
gem5::ArmISA::MISCREG_ICC_BPR1_EL1
@ MISCREG_ICC_BPR1_EL1
Definition: misc.hh:867
gem5::BaseGic::params
const Params & params() const
Definition: base_gic.cc:78
gem5::ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:59
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Gicv3CPUInterface::getHCREL2FMO
bool getHCREL2FMO() const
Definition: gic_v3_cpu_interface.cc:92
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::Gicv3CPUInterface::getHCREL2IMO
bool getHCREL2IMO() const
Definition: gic_v3_cpu_interface.cc:106
gem5::Gicv3CPUInterface::hppi
hppi_t hppi
Definition: gic_v3_cpu_interface.hh:170
gem5::ArmISA::MISCREG_ICH_VMCR_EL2
@ MISCREG_ICH_VMCR_EL2
Definition: misc.hh:899
gem5::Gicv3Registers::copyCpuRegister
static void copyCpuRegister(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg)
Definition: gic_v3.cc:82
gem5::ArmISA::MISCREG_ICV_IAR1_EL1
@ MISCREG_ICV_IAR1_EL1
Definition: misc.hh:943
gem5::ArmISA::MISCREG_ICH_AP1R2_EL2
@ MISCREG_ICH_AP1R2_EL2
Definition: misc.hh:892
gem5::ArmSystem::callSetWakeRequest
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:213
gem5::ArmISA::MISCREG_ICV_BPR0_EL1
@ MISCREG_ICV_BPR0_EL1
Definition: misc.hh:921
faults.hh
gem5::Gicv3Distributor::EnableGrp0
bool EnableGrp0
Definition: gic_v3_distributor.hh:156
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition: misc.hh:879
gem5::Gicv3CPUInterface::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3_cpu_interface.cc:2619
gem5::Gicv3CPUInterface::updateDistributor
void updateDistributor()
Definition: gic_v3_cpu_interface.cc:2027
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1002
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S
@ MISCREG_ICC_BPR1_EL1_S
Definition: misc.hh:869
gem5::ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition: misc.hh:893
gem5::Gicv3CPUInterface::VIRTUAL_PREEMPTION_BITS
static const uint8_t VIRTUAL_PREEMPTION_BITS
Definition: gic_v3_cpu_interface.hh:158
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1
@ MISCREG_ICC_IGRPEN0_EL1
Definition: misc.hh:876
gem5::Gicv3CPUInterface::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition: gic_v3_cpu_interface.cc:740
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1
@ MISCREG_ICC_AP1R3_EL1
Definition: misc.hh:856
gem5::Gicv3::G0S
@ G0S
Definition: gic_v3.hh:135
gem5::Gicv3CPUInterface::cpuId
uint32_t cpuId
Definition: gic_v3_cpu_interface.hh:71
gem5::ArmISA::MISCREG_ICV_EOIR1_EL1
@ MISCREG_ICV_EOIR1_EL1
Definition: misc.hh:944
gem5::ArmSystem::has
bool has(ArmExtension ext) const
Definition: system.hh:154
gem5::ArmISA::MISCREG_ICH_LR15
@ MISCREG_ICH_LR15
Definition: misc.hh:1036
gem5::Gicv3CPUInterface::virtualIncrementEOICount
void virtualIncrementEOICount()
Definition: gic_v3_cpu_interface.cc:2223
gem5::Gicv3CPUInterface::deactivateIRQ
void deactivateIRQ(uint32_t intid, Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1885
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: misc.hh:1001
gem5::ArmISA::MISCREG_ICH_EISR_EL2
@ MISCREG_ICH_EISR_EL2
Definition: misc.hh:897
gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE_PENDING
static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING
Definition: gic_v3_cpu_interface.hh:242
gem5::Gicv3Distributor::EnableGrp1S
bool EnableGrp1S
Definition: gic_v3_distributor.hh:154
gem5::Gicv3
Definition: gic_v3.hh:95
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition: misc.hh:984
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: misc.hh:863
gem5::ArmISA::MISCREG_ICC_AP0R2
@ MISCREG_ICC_AP0R2
Definition: misc.hh:962
gem5::Gicv3CPUInterface::virtualDropPriority
uint8_t virtualDropPriority()
Definition: gic_v3_cpu_interface.cc:1744
gem5::ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition: misc.hh:963
gem5::ArmISA::INT_IRQ
@ INT_IRQ
Definition: interrupts.hh:63
gem5::Gicv3Redistributor::deactivateIRQ
void deactivateIRQ(uint32_t int_id)
Definition: gic_v3_redistributor.cc:1008
gem5::ArmISA::MISCREG_ICC_SRE
@ MISCREG_ICC_SRE
Definition: misc.hh:1003
gem5::Gicv3CPUInterface::hppi_t::group
Gicv3::GroupId group
Definition: gic_v3_cpu_interface.hh:167
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::Gicv3Redistributor::SMALLEST_LPI_ID
static const uint32_t SMALLEST_LPI_ID
Definition: gic_v3_redistributor.hh:200
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: misc.hh:886
gem5::ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition: misc.hh:898
gem5::ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition: misc.hh:1020
gem5::Gicv3::SGI_MAX
static const int SGI_MAX
Definition: gic_v3.hh:119
gem5::ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition: misc.hh:873
gem5::ArmISA::MISCREG_ICH_HCR
@ MISCREG_ICH_HCR
Definition: misc.hh:1015
gem5::Gicv3CPUInterface::Enable
Bitfield< 0 > Enable
Definition: gic_v3_cpu_interface.hh:113
gem5::ctz32
constexpr int ctz32(uint32_t value)
Count trailing zeros in a 32-bit value.
Definition: bitfield.hh:392
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:838
gem5::ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition: misc.hh:1010
gem5::ArmISA::aff2
Bitfield< 23, 16 > aff2
Definition: types.hh:207
gem5::Gicv3CPUInterface::inSecureState
bool inSecureState() const
Definition: gic_v3_cpu_interface.cc:2340
gem5::Gicv3CPUInterface::groupPriorityMask
uint32_t groupPriorityMask(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1924
gem5::ArmISA::MISCREG_ICC_IAR0
@ MISCREG_ICC_IAR0
Definition: misc.hh:990
gem5::ArmISA::MISCREG_ICC_CTLR
@ MISCREG_ICC_CTLR
Definition: misc.hh:981
gem5::ArmISA::MISCREG_ICC_BPR0
@ MISCREG_ICC_BPR0
Definition: misc.hh:977
gem5::Gicv3CPUInterface::maintenanceInterruptStatus
ICH_MISR_EL2 maintenanceInterruptStatus() const
Definition: gic_v3_cpu_interface.cc:2437
gem5::ArmISA::MISCREG_ICC_CTLR_EL1
@ MISCREG_ICC_CTLR_EL1
Definition: misc.hh:870
gem5::ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition: misc.hh:864
gem5::Gicv3::INTID_SECURE
static const int INTID_SECURE
Definition: gic_v3.hh:114
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3::G1S
@ G1S
Definition: gic_v3.hh:136
UNSERIALIZE_ENUM
#define UNSERIALIZE_ENUM(scalar)
Definition: serialize.hh:598
gem5::ArmInterruptPin::raise
virtual void raise()=0
Signal an interrupt.
gem5::Gicv3::deassertInt
void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
Definition: gic_v3.cc:297
gem5::ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition: misc.hh:961
gem5::Gicv3Redistributor::setClrLPI
void setClrLPI(uint64_t data, bool set)
Definition: gic_v3_redistributor.cc:923
gem5::ArmISA::aff3
aff3
Definition: types.hh:206
gem5::Gicv3CPUInterface::assertWakeRequest
void assertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2579
gem5::ArmISA::MISCREG_ICC_SRE_EL2
@ MISCREG_ICC_SRE_EL2
Definition: misc.hh:880
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_ICC_AP0R2_EL1
@ MISCREG_ICC_AP0R2_EL1
Definition: misc.hh:845
gem5::Gicv3CPUInterface::setBankedMiscReg
void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const
Definition: gic_v3_cpu_interface.cc:1630
gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1
@ MISCREG_ICC_HPPIR1_EL1
Definition: misc.hh:866
gem5::Gicv3CPUInterface::virtualFindActive
int virtualFindActive(uint32_t intid) const
Definition: gic_v3_cpu_interface.cc:1637
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5::ArmISA::MISCREG_ICV_BPR1_EL1
@ MISCREG_ICV_BPR1_EL1
Definition: misc.hh:946
gem5::Gicv3CPUInterface::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition: gic_v3_cpu_interface.cc:120
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gicv3CPUInterface::U
Bitfield< 1 > U
Definition: gic_v3_cpu_interface.hh:263
gem5::Gicv3CPUInterface::Gicv3CPUInterface
Gicv3CPUInterface(Gicv3 *gic, uint32_t cpu_id)
Definition: gic_v3_cpu_interface.cc:58
gem5::Gicv3CPUInterface::GIC_MIN_BPR
static const uint8_t GIC_MIN_BPR
Definition: gic_v3_cpu_interface.hh:153
gem5::ArmISA::MISCREG_ICV_AP1R0_EL1
@ MISCREG_ICV_AP1R0_EL1
Definition: misc.hh:926
gem5::Gicv3CPUInterface::bpr1
RegVal bpr1(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:2525
gem5::Gicv3CPUInterface::getHPPIR0
uint32_t getHPPIR0() const
Definition: gic_v3_cpu_interface.cc:1654
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1
@ MISCREG_ICC_IGRPEN1_EL1
Definition: misc.hh:877
gem5::Gicv3Distributor::deactivateIRQ
void deactivateIRQ(uint32_t int_id)
Definition: gic_v3_distributor.cc:1179
gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1
@ MISCREG_ICV_IGRPEN1_EL1
Definition: misc.hh:956
gem5::ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition: misc.hh:1014
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition: misc.hh:878
gic_v3_distributor.hh
gem5::ArmISA::MISCREG_ICC_HPPIR0
@ MISCREG_ICC_HPPIR0
Definition: misc.hh:987
gem5::ArmISA::MISCREG_ICC_AP1R2
@ MISCREG_ICC_AP1R2
Definition: misc.hh:970
gem5::Gicv3Redistributor::sendSGI
void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns)
Definition: gic_v3_redistributor.cc:736
gic_v3.hh
gem5::Gicv3Redistributor::activateIRQ
void activateIRQ(uint32_t int_id)
Definition: gic_v3_redistributor.cc:999
gem5::ArmISA::MISCREG_ICC_BPR1
@ MISCREG_ICC_BPR1
Definition: misc.hh:978
gem5::Gicv3CPUInterface::virtualActivateIRQ
void virtualActivateIRQ(uint32_t lrIdx)
Definition: gic_v3_cpu_interface.cc:1864
gem5::ArmISA::MISCREG_ICC_RPR
@ MISCREG_ICC_RPR
Definition: misc.hh:1000
gem5::ArmISA::MISCREG_ICV_CTLR_EL1
@ MISCREG_ICV_CTLR_EL1
Definition: misc.hh:949
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition: misc.hh:1017
gem5::Gicv3CPUInterface::virtualIsEOISplitMode
bool virtualIsEOISplitMode() const
Definition: gic_v3_cpu_interface.cc:1998
gem5::Gicv3CPUInterface::hppi_t::prio
uint8_t prio
Definition: gic_v3_cpu_interface.hh:166
gem5::ArmISA::rs
Bitfield< 9, 8 > rs
Definition: misc_types.hh:377
gem5::ArmISA::ISA::inSecureState
bool inSecureState() const
Return true if the PE is in Secure state.
Definition: isa.cc:2043
gem5::ArmISA::aff1
Bitfield< 15, 8 > aff1
Definition: types.hh:208
gem5::Gicv3CPUInterface::getHPPIR1
uint32_t getHPPIR1() const
Definition: gic_v3_cpu_interface.cc:1680
gem5::ArmISA::MISCREG_ICC_AP0R0_EL1
@ MISCREG_ICC_AP0R0_EL1
Definition: misc.hh:843
gem5::Gicv3CPUInterface::haveEL
bool haveEL(ArmISA::ExceptionLevel el) const
Definition: gic_v3_cpu_interface.cc:2352
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE
static const uint64_t ICH_LR_EL2_STATE_ACTIVE
Definition: gic_v3_cpu_interface.hh:241
gem5::ArmISA::MISCREG_ICC_AP1R0
@ MISCREG_ICC_AP1R0
Definition: misc.hh:964
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition: misc.hh:850
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1
@ MISCREG_ICC_AP1R2_EL1
Definition: misc.hh:853
gem5::Gicv3CPUInterface::VIRTUAL_PRIORITY_BITS
static const uint8_t VIRTUAL_PRIORITY_BITS
Definition: gic_v3_cpu_interface.hh:157
gem5::Gicv3Redistributor::getAffinity
uint32_t getAffinity() const
Definition: gic_v3_redistributor.cc:1014
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