#include <algorithm>
#include <cstdint>
#include <vector>
#include "base/types.hh"
#include "debug/HSAPacketProcessor.hh"
#include "dev/dma_virt_device.hh"
#include "dev/hsa/hsa.h"
#include "dev/hsa/hsa_queue.hh"
#include "enums/GfxVersion.hh"
#include "params/HSAPacketProcessor.hh"
#include "sim/eventq.hh"

Classes
class	gem5::HSAQueueDescriptor

class	gem5::AQLRingBuffer
	Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer. More...

struct	gem5::QCntxt

class	gem5::HSAPacketProcessor

class	gem5::HSAPacketProcessor::SignalState

class	gem5::HSAPacketProcessor::QueueProcessEvent

class	gem5::HSAPacketProcessor::RQLEntry

struct	gem5::HSAPacketProcessor::dma_series_ctx
	Calls getCurrentEntry once the queueEntry has been dmaRead. More...

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

Macros
#define	AQL_PACKET_SIZE 64

#define	PAGE_SIZE 4096

#define	NUM_DMA_BUFS 16

#define	DMA_BUF_SIZE (AQL_PACKET_SIZE * NUM_DMA_BUFS)

#define	NumSignalsPerBarrier 5

Enumerations
enum	gem5::Q_STATE { gem5::UNBLOCKED = 0, gem5::BLOCKED_BBIT, gem5::BLOCKED_BPKT }

Macro Definition Documentation

◆ AQL_PACKET_SIZE

#define AQL_PACKET_SIZE 64

Definition at line 48 of file hsa_packet_processor.hh.

◆ DMA_BUF_SIZE

#define DMA_BUF_SIZE (AQL_PACKET_SIZE * NUM_DMA_BUFS)

Definition at line 51 of file hsa_packet_processor.hh.

◆ NUM_DMA_BUFS

#define NUM_DMA_BUFS 16

Definition at line 50 of file hsa_packet_processor.hh.

◆ NumSignalsPerBarrier

#define NumSignalsPerBarrier 5

Definition at line 53 of file hsa_packet_processor.hh.

◆ PAGE_SIZE

#define PAGE_SIZE 4096

Definition at line 49 of file hsa_packet_processor.hh.

Classes

Namespaces