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gem5
v22.0.0.2
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Enumerations | |
| enum | : RegIndex { _NzIdx, _CIdx, _VIdx, _GeIdx, _FpIdx, _ZeroIdx, NumRegs } |
Functions | |
| constexpr RegId | Nz (CCRegClass, _NzIdx) |
| constexpr RegId | C (CCRegClass, _CIdx) |
| constexpr RegId | V (CCRegClass, _VIdx) |
| constexpr RegId | Ge (CCRegClass, _GeIdx) |
| constexpr RegId | Fp (CCRegClass, _FpIdx) |
| constexpr RegId | Zero (CCRegClass, _ZeroIdx) |
Variables | |
| const char *const | RegName [NumRegs] |
| anonymous enum : RegIndex |
| constexpr RegId gem5::ArmISA::cc_reg::C | ( | CCRegClass | , |
| _CIdx | |||
| ) |
Referenced by gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::ISA::readMiscReg(), SC_MODULE(), gem5::ArmISA::ISA::setMiscReg(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().
| constexpr RegId gem5::ArmISA::cc_reg::Fp | ( | CCRegClass | , |
| _FpIdx | |||
| ) |
| constexpr RegId gem5::ArmISA::cc_reg::Ge | ( | CCRegClass | , |
| _GeIdx | |||
| ) |
Referenced by gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().
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inlineconstexpr |
Referenced by gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::fastmodel::CortexA76TC::readCCRegFlat(), gem5::fastmodel::CortexR52TC::readCCRegFlat(), gem5::ArmISA::ISA::readMiscReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), gem5::ArmISA::ISA::setMiscReg(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().
| constexpr RegId gem5::ArmISA::cc_reg::V | ( | CCRegClass | , |
| _VIdx | |||
| ) |
Referenced by gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::ISA::readMiscReg(), SC_MODULE(), gem5::ArmISA::ISA::setMiscReg(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().
| constexpr RegId gem5::ArmISA::cc_reg::Zero | ( | CCRegClass | , |
| _ZeroIdx | |||
| ) |
Referenced by gem5::ArmISA::couldBeZero(), gem5::ArmISA::decodeMrsMsrBankedIntRegIndex(), gem5::ArmISA::EndBitUnion(), gem5::ArmISA::DataXImmOp::generateDisassembly(), gem5::ArmISA::DataXSRegOp::generateDisassembly(), gem5::ArmISA::DataXERegOp::generateDisassembly(), gem5::ArmISA::DataImmOp::generateDisassembly(), gem5::ArmISA::DataRegOp::generateDisassembly(), gem5::RegImmRegShiftOp::generateDisassembly(), gem5::ArmISA::isZero(), gem5::ArmISA::makeZero(), gem5::ArmISA::ArmStaticInst::printDataInst(), and gem5::ArmISA::ArmStaticInst::printShiftOperand().
| const char* const gem5::ArmISA::cc_reg::RegName[NumRegs] |
Definition at line 71 of file cc.hh.
Referenced by gem5::ArmISA::ArmStaticInst::printCCReg(), and gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateCC().