gem5::sinic::registers Namespace Reference

Classes
struct	Info

Functions
	__SINIC_REG32 (Config, 0x00) __SINIC_REG32(Command
	__SINIC_REG32 (IntrStatus, 0x08) __SINIC_REG32(IntrMask
	__SINIC_REG32 (RxMaxCopy, 0x10) __SINIC_REG32(TxMaxCopy
	__SINIC_REG32 (ZeroCopySize, 0x18) __SINIC_REG32(ZeroCopyMark
	__SINIC_REG32 (VirtualCount, 0x20) __SINIC_REG32(RxMaxIntr
	__SINIC_REG32 (RxFifoSize, 0x28) __SINIC_REG32(TxFifoSize
	__SINIC_REG32 (RxFifoLow, 0x30) __SINIC_REG32(TxFifoLow
	__SINIC_REG32 (RxFifoHigh, 0x38) __SINIC_REG32(TxFifoHigh
	__SINIC_REG32 (RxData, 0x40) __SINIC_REG32(RxDone
	__SINIC_REG32 (RxWait, 0x50) __SINIC_REG32(TxData
	__SINIC_REG32 (TxDone, 0x60) __SINIC_REG32(TxWait
	__SINIC_REG32 (HwAddr, 0x70) __SINIC_REG32(Size
	__SINIC_VAL32 (Config_ZeroCopy, 12, 1) __SINIC_VAL32(Config_DelayCopy
	__SINIC_VAL32 (Config_RSS, 10, 1) __SINIC_VAL32(Config_RxThread
	__SINIC_VAL32 (Config_TxThread, 8, 1) __SINIC_VAL32(Config_Filter
	__SINIC_VAL32 (Config_Vlan, 6, 1) __SINIC_VAL32(Config_Vaddr
	__SINIC_VAL32 (Config_Desc, 4, 1) __SINIC_VAL32(Config_Poll
	__SINIC_VAL32 (Config_IntEn, 2, 1) __SINIC_VAL32(Config_TxEn
	__SINIC_VAL32 (Config_RxEn, 0, 1) __SINIC_VAL32(Command_Intr
	__SINIC_VAL32 (Command_Reset, 0, 1) __SINIC_VAL32(Intr_Soft
	__SINIC_VAL32 (Intr_TxLow, 7, 1) __SINIC_VAL32(Intr_TxFull
	__SINIC_VAL32 (Intr_TxDMA, 5, 1) __SINIC_VAL32(Intr_TxPacket
	__SINIC_VAL32 (Intr_RxHigh, 3, 1) __SINIC_VAL32(Intr_RxEmpty
	__SINIC_VAL32 (Intr_RxDMA, 1, 1) __SINIC_VAL32(Intr_RxPacket
	__SINIC_REG32 (Intr_All, 0x01ff) __SINIC_REG32(Intr_NoDelay
	__SINIC_REG32 (Intr_Res, ~0x01ff) __SINIC_VAL64(RxData_NoDelay
	__SINIC_VAL64 (RxData_Vaddr, 60, 1) __SINIC_VAL64(RxData_Len
	__SINIC_VAL64 (RxData_Addr, 0, 40) __SINIC_VAL64(TxData_More
	__SINIC_VAL64 (TxData_Checksum, 62, 1) __SINIC_VAL64(TxData_Vaddr
	__SINIC_VAL64 (TxData_Len, 40, 20) __SINIC_VAL64(TxData_Addr
	__SINIC_VAL64 (RxDone_Packets, 32, 16) __SINIC_VAL64(RxDone_Busy
	__SINIC_VAL64 (RxDone_Complete, 30, 1) __SINIC_VAL64(RxDone_More
	__SINIC_VAL64 (RxDone_Empty, 28, 1) __SINIC_VAL64(RxDone_High
	__SINIC_VAL64 (RxDone_NotHigh, 26, 1) __SINIC_VAL64(RxDone_TcpError
	__SINIC_VAL64 (RxDone_UdpError, 24, 1) __SINIC_VAL64(RxDone_IpError
	__SINIC_VAL64 (RxDone_TcpPacket, 22, 1) __SINIC_VAL64(RxDone_UdpPacket
	__SINIC_VAL64 (RxDone_IpPacket, 20, 1) __SINIC_VAL64(RxDone_CopyLen
	__SINIC_VAL64 (TxDone_Packets, 32, 16) __SINIC_VAL64(TxDone_Busy
	__SINIC_VAL64 (TxDone_Complete, 30, 1) __SINIC_VAL64(TxDone_Full
	__SINIC_VAL64 (TxDone_Low, 28, 1) __SINIC_VAL64(TxDone_Res0
	__SINIC_VAL64 (TxDone_Res1, 26, 1) __SINIC_VAL64(TxDone_Res2
	__SINIC_VAL64 (TxDone_Res3, 24, 1) __SINIC_VAL64(TxDone_Res4
	__SINIC_VAL64 (TxDone_Res5, 22, 1) __SINIC_VAL64(TxDone_Res6
	__SINIC_VAL64 (TxDone_Res7, 20, 1) __SINIC_VAL64(TxDone_CopyLen

Variables
static const int	VirtualShift = 8
static const int	VirtualMask = 0xff

Function Documentation

__SINIC_REG32() [1/14]

gem5::sinic::registers::__SINIC_REG32	(	Config	,
		0x00
	)

__SINIC_REG32() [2/14]

gem5::sinic::registers::__SINIC_REG32	(	HwAddr	,
		0x70
	)

__SINIC_REG32() [3/14]

gem5::sinic::registers::__SINIC_REG32	(	Intr_All	,
		0x01ff
	)

__SINIC_REG32() [4/14]

gem5::sinic::registers::__SINIC_REG32	(	Intr_Res	,
		~	0x01ff
	)

__SINIC_REG32() [5/14]

gem5::sinic::registers::__SINIC_REG32	(	IntrStatus	,
		0x08
	)

__SINIC_REG32() [6/14]

gem5::sinic::registers::__SINIC_REG32	(	RxData	,
		0x40
	)

__SINIC_REG32() [7/14]

gem5::sinic::registers::__SINIC_REG32	(	RxFifoHigh	,
		0x38
	)

__SINIC_REG32() [8/14]

gem5::sinic::registers::__SINIC_REG32	(	RxFifoLow	,
		0x30
	)

__SINIC_REG32() [9/14]

gem5::sinic::registers::__SINIC_REG32	(	RxFifoSize	,
		0x28
	)

__SINIC_REG32() [10/14]

gem5::sinic::registers::__SINIC_REG32	(	RxMaxCopy	,
		0x10
	)

__SINIC_REG32() [11/14]

gem5::sinic::registers::__SINIC_REG32	(	RxWait	,
		0x50
	)

__SINIC_REG32() [12/14]

gem5::sinic::registers::__SINIC_REG32	(	TxDone	,
		0x60
	)

__SINIC_REG32() [13/14]

gem5::sinic::registers::__SINIC_REG32	(	VirtualCount	,
		0x20
	)

__SINIC_REG32() [14/14]

gem5::sinic::registers::__SINIC_REG32	(	ZeroCopySize	,
		0x18
	)

__SINIC_VAL32() [1/12]

gem5::sinic::registers::__SINIC_VAL32	(	Command_Reset	,
		0	,
		1
	)

__SINIC_VAL32() [2/12]

gem5::sinic::registers::__SINIC_VAL32	(	Config_Desc	,
		4	,
		1
	)

__SINIC_VAL32() [3/12]

gem5::sinic::registers::__SINIC_VAL32	(	Config_IntEn	,
		2	,
		1
	)

__SINIC_VAL32() [4/12]

gem5::sinic::registers::__SINIC_VAL32	(	Config_RSS	,
		10	,
		1
	)

__SINIC_VAL32() [5/12]

gem5::sinic::registers::__SINIC_VAL32	(	Config_RxEn	,
		0	,
		1
	)

__SINIC_VAL32() [6/12]

gem5::sinic::registers::__SINIC_VAL32	(	Config_TxThread	,
		8	,
		1
	)

__SINIC_VAL32() [7/12]

gem5::sinic::registers::__SINIC_VAL32	(	Config_Vlan	,
		6	,
		1
	)

__SINIC_VAL32() [8/12]

gem5::sinic::registers::__SINIC_VAL32	(	Config_ZeroCopy	,
		12	,
		1
	)

__SINIC_VAL32() [9/12]

gem5::sinic::registers::__SINIC_VAL32	(	Intr_RxDMA	,
		1	,
		1
	)

__SINIC_VAL32() [10/12]

gem5::sinic::registers::__SINIC_VAL32	(	Intr_RxHigh	,
		3	,
		1
	)

__SINIC_VAL32() [11/12]

gem5::sinic::registers::__SINIC_VAL32	(	Intr_TxDMA	,
		5	,
		1
	)

__SINIC_VAL32() [12/12]

gem5::sinic::registers::__SINIC_VAL32	(	Intr_TxLow	,
		7	,
		1
	)

__SINIC_VAL64() [1/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxData_Addr	,
		0	,
		40
	)

__SINIC_VAL64() [2/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxData_Vaddr	,
		60	,
		1
	)

__SINIC_VAL64() [3/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxDone_Complete	,
		30	,
		1
	)

__SINIC_VAL64() [4/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxDone_Empty	,
		28	,
		1
	)

__SINIC_VAL64() [5/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxDone_IpPacket	,
		20	,
		1
	)

__SINIC_VAL64() [6/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxDone_NotHigh	,
		26	,
		1
	)

__SINIC_VAL64() [7/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxDone_Packets	,
		32	,
		16
	)

__SINIC_VAL64() [8/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxDone_TcpPacket	,
		22	,
		1
	)

__SINIC_VAL64() [9/18]

gem5::sinic::registers::__SINIC_VAL64	(	RxDone_UdpError	,
		24	,
		1
	)

__SINIC_VAL64() [10/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxData_Checksum	,
		62	,
		1
	)

__SINIC_VAL64() [11/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxData_Len	,
		40	,
		20
	)

__SINIC_VAL64() [12/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxDone_Complete	,
		30	,
		1
	)

__SINIC_VAL64() [13/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxDone_Low	,
		28	,
		1
	)

__SINIC_VAL64() [14/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxDone_Packets	,
		32	,
		16
	)

__SINIC_VAL64() [15/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxDone_Res1	,
		26	,
		1
	)

__SINIC_VAL64() [16/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxDone_Res3	,
		24	,
		1
	)

__SINIC_VAL64() [17/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxDone_Res5	,
		22	,
		1
	)

__SINIC_VAL64() [18/18]

gem5::sinic::registers::__SINIC_VAL64	(	TxDone_Res7	,
		20	,
		1
	)

Variable Documentation

VirtualMask

const int gem5::sinic::registers::VirtualMask = 0xff

static

Definition at line 71 of file sinicreg.hh.

Referenced by gem5::sinic::Device::read(), and gem5::sinic::Device::write().

VirtualShift

const int gem5::sinic::registers::VirtualShift = 8

static

Definition at line 70 of file sinicreg.hh.

Referenced by gem5::sinic::Device::read(), and gem5::sinic::Device::write().