gem5
v22.0.0.2
arch
x86
regs
float.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_FLOATREGS_HH__
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#define __ARCH_X86_FLOATREGS_HH__
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#include "
arch/x86/x86_traits.hh
"
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#include "
base/bitunion.hh
"
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namespace
gem5
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{
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namespace
X86ISA
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{
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namespace
float_reg
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{
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enum
FloatRegIndex
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{
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// MMX/X87 registers
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MmxBase
,
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FprBase
=
MmxBase
,
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_Mmx0Idx
=
MmxBase
,
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_Mmx1Idx
,
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_Mmx2Idx
,
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_Mmx3Idx
,
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_Mmx4Idx
,
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_Mmx5Idx
,
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_Mmx6Idx
,
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_Mmx7Idx
,
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_Fpr0Idx
=
FprBase
,
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_Fpr1Idx
,
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_Fpr2Idx
,
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_Fpr3Idx
,
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_Fpr4Idx
,
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_Fpr5Idx
,
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_Fpr6Idx
,
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_Fpr7Idx
,
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XmmBase
=
MmxBase
+
NumMMXRegs
,
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_Xmm0LowIdx
=
XmmBase
,
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_Xmm0HighIdx
,
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_Xmm1LowIdx
,
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_Xmm1HighIdx
,
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_Xmm2LowIdx
,
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_Xmm2HighIdx
,
80
_Xmm3LowIdx
,
81
_Xmm3HighIdx
,
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_Xmm4LowIdx
,
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_Xmm4HighIdx
,
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_Xmm5LowIdx
,
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_Xmm5HighIdx
,
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_Xmm6LowIdx
,
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_Xmm6HighIdx
,
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_Xmm7LowIdx
,
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_Xmm7HighIdx
,
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_Xmm8LowIdx
,
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_Xmm8HighIdx
,
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_Xmm9LowIdx
,
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_Xmm9HighIdx
,
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_Xmm10LowIdx
,
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_Xmm10HighIdx
,
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_Xmm11LowIdx
,
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_Xmm11HighIdx
,
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_Xmm12LowIdx
,
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_Xmm12HighIdx
,
100
_Xmm13LowIdx
,
101
_Xmm13HighIdx
,
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_Xmm14LowIdx
,
103
_Xmm14HighIdx
,
104
_Xmm15LowIdx
,
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_Xmm15HighIdx
,
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MicrofpBase
=
XmmBase
+ 2 *
NumXMMRegs
,
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_Microfp0Idx
=
MicrofpBase
,
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_Microfp1Idx
,
110
_Microfp2Idx
,
111
_Microfp3Idx
,
112
_Microfp4Idx
,
113
_Microfp5Idx
,
114
_Microfp6Idx
,
115
_Microfp7Idx
,
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NumRegs
=
MicrofpBase
+
NumMicroFpRegs
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};
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static
inline
RegId
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mmx
(
int
index
)
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{
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return
RegId
(
FloatRegClass
,
MmxBase
+
index
);
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}
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static
inline
RegId
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fpr
(
int
index
)
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{
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return
RegId
(
FloatRegClass
,
FprBase
+
index
);
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}
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static
inline
RegId
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xmm
(
int
index
)
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{
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return
RegId
(
FloatRegClass
,
XmmBase
+
index
);
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}
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static
inline
RegId
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xmmLow
(
int
index
)
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{
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return
RegId
(
FloatRegClass
,
XmmBase
+ 2 *
index
);
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}
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static
inline
RegId
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xmmHigh
(
int
index
)
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{
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return
RegId
(
FloatRegClass
,
XmmBase
+ 2 *
index
+ 1);
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}
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static
inline
RegId
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microfp
(
int
index
)
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{
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return
RegId
(
FloatRegClass
,
MicrofpBase
+
index
);
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}
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static
inline
RegId
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stack
(
int
index
,
int
top
)
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{
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return
fpr
((
top
+
index
+ 8) % 8);
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}
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}
// namespace float_reg
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}
// namespace X86ISA
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}
// namespace gem5
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#endif // __ARCH_X86_FLOATREGS_HH__
gem5::X86ISA::float_reg::_Xmm0LowIdx
@ _Xmm0LowIdx
Definition:
float.hh:74
gem5::X86ISA::float_reg::_Xmm8LowIdx
@ _Xmm8LowIdx
Definition:
float.hh:90
x86_traits.hh
gem5::X86ISA::float_reg::_Xmm5LowIdx
@ _Xmm5LowIdx
Definition:
float.hh:84
gem5::X86ISA::float_reg::_Xmm11LowIdx
@ _Xmm11LowIdx
Definition:
float.hh:96
gem5::X86ISA::float_reg::_Xmm1LowIdx
@ _Xmm1LowIdx
Definition:
float.hh:76
gem5::X86ISA::float_reg::xmm
static RegId xmm(int index)
Definition:
float.hh:133
gem5::X86ISA::float_reg::_Fpr7Idx
@ _Fpr7Idx
Definition:
float.hh:71
gem5::X86ISA::float_reg::XmmBase
@ XmmBase
Definition:
float.hh:73
gem5::X86ISA::float_reg::_Xmm2LowIdx
@ _Xmm2LowIdx
Definition:
float.hh:78
gem5::X86ISA::float_reg::_Microfp1Idx
@ _Microfp1Idx
Definition:
float.hh:109
gem5::X86ISA::float_reg::FloatRegIndex
FloatRegIndex
Definition:
float.hh:50
top
Definition:
test.h:61
gem5::X86ISA::float_reg::MmxBase
@ MmxBase
Definition:
float.hh:53
gem5::X86ISA::float_reg::_Xmm2HighIdx
@ _Xmm2HighIdx
Definition:
float.hh:79
gem5::X86ISA::float_reg::_Xmm14HighIdx
@ _Xmm14HighIdx
Definition:
float.hh:103
gem5::X86ISA::float_reg::_Microfp4Idx
@ _Microfp4Idx
Definition:
float.hh:112
gem5::X86ISA::float_reg::_Xmm14LowIdx
@ _Xmm14LowIdx
Definition:
float.hh:102
gem5::X86ISA::float_reg::_Microfp3Idx
@ _Microfp3Idx
Definition:
float.hh:111
gem5::X86ISA::float_reg::_Microfp6Idx
@ _Microfp6Idx
Definition:
float.hh:114
gem5::X86ISA::float_reg::_Mmx6Idx
@ _Mmx6Idx
Definition:
float.hh:61
gem5::X86ISA::float_reg::_Xmm15HighIdx
@ _Xmm15HighIdx
Definition:
float.hh:105
gem5::X86ISA::float_reg::_Mmx0Idx
@ _Mmx0Idx
Definition:
float.hh:55
gem5::X86ISA::float_reg::_Xmm12LowIdx
@ _Xmm12LowIdx
Definition:
float.hh:98
gem5::X86ISA::float_reg::NumRegs
@ NumRegs
Definition:
float.hh:117
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition:
reg_class.hh:59
gem5::X86ISA::float_reg::_Xmm0HighIdx
@ _Xmm0HighIdx
Definition:
float.hh:75
gem5::X86ISA::float_reg::_Xmm1HighIdx
@ _Xmm1HighIdx
Definition:
float.hh:77
gem5::X86ISA::float_reg::_Xmm9LowIdx
@ _Xmm9LowIdx
Definition:
float.hh:92
gem5::X86ISA::float_reg::_Xmm13LowIdx
@ _Xmm13LowIdx
Definition:
float.hh:100
gem5::X86ISA::float_reg::_Xmm6HighIdx
@ _Xmm6HighIdx
Definition:
float.hh:87
gem5::X86ISA::float_reg::xmmLow
static RegId xmmLow(int index)
Definition:
float.hh:139
bitunion.hh
gem5::X86ISA::NumXMMRegs
const int NumXMMRegs
Definition:
x86_traits.hh:53
gem5::X86ISA::float_reg::xmmHigh
static RegId xmmHigh(int index)
Definition:
float.hh:145
gem5::X86ISA::float_reg::fpr
static RegId fpr(int index)
Definition:
float.hh:127
gem5::X86ISA::NumMMXRegs
const int NumMMXRegs
Definition:
x86_traits.hh:52
gem5::X86ISA::float_reg::_Xmm15LowIdx
@ _Xmm15LowIdx
Definition:
float.hh:104
gem5::X86ISA::float_reg::_Fpr5Idx
@ _Fpr5Idx
Definition:
float.hh:69
gem5::X86ISA::float_reg::_Mmx4Idx
@ _Mmx4Idx
Definition:
float.hh:59
gem5::X86ISA::float_reg::_Xmm4HighIdx
@ _Xmm4HighIdx
Definition:
float.hh:83
gem5::X86ISA::float_reg::mmx
static RegId mmx(int index)
Definition:
float.hh:121
gem5::X86ISA::float_reg::_Xmm11HighIdx
@ _Xmm11HighIdx
Definition:
float.hh:97
gem5::X86ISA::float_reg::stack
static RegId stack(int index, int top)
Definition:
float.hh:157
gem5::X86ISA::float_reg::_Xmm10LowIdx
@ _Xmm10LowIdx
Definition:
float.hh:94
gem5::X86ISA::float_reg::_Xmm12HighIdx
@ _Xmm12HighIdx
Definition:
float.hh:99
gem5::X86ISA::float_reg::_Xmm9HighIdx
@ _Xmm9HighIdx
Definition:
float.hh:93
gem5::X86ISA::float_reg::_Fpr1Idx
@ _Fpr1Idx
Definition:
float.hh:65
gem5::X86ISA::float_reg::_Xmm7HighIdx
@ _Xmm7HighIdx
Definition:
float.hh:89
gem5::X86ISA::float_reg::_Xmm6LowIdx
@ _Xmm6LowIdx
Definition:
float.hh:86
gem5::X86ISA::float_reg::_Mmx2Idx
@ _Mmx2Idx
Definition:
float.hh:57
gem5::X86ISA::float_reg::_Fpr6Idx
@ _Fpr6Idx
Definition:
float.hh:70
gem5::X86ISA::float_reg::_Xmm3LowIdx
@ _Xmm3LowIdx
Definition:
float.hh:80
gem5::X86ISA::float_reg::_Mmx1Idx
@ _Mmx1Idx
Definition:
float.hh:56
gem5::X86ISA::float_reg::_Fpr0Idx
@ _Fpr0Idx
Definition:
float.hh:64
gem5::X86ISA::float_reg::_Mmx3Idx
@ _Mmx3Idx
Definition:
float.hh:58
gem5::X86ISA::float_reg::FprBase
@ FprBase
Definition:
float.hh:54
gem5::X86ISA::float_reg::_Xmm13HighIdx
@ _Xmm13HighIdx
Definition:
float.hh:101
gem5::X86ISA::float_reg::_Fpr4Idx
@ _Fpr4Idx
Definition:
float.hh:68
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition:
types.hh:98
gem5::X86ISA::float_reg::_Xmm3HighIdx
@ _Xmm3HighIdx
Definition:
float.hh:81
gem5::X86ISA::float_reg::_Mmx5Idx
@ _Mmx5Idx
Definition:
float.hh:60
gem5::X86ISA::float_reg::_Xmm5HighIdx
@ _Xmm5HighIdx
Definition:
float.hh:85
gem5::X86ISA::float_reg::MicrofpBase
@ MicrofpBase
Definition:
float.hh:107
gem5::X86ISA::float_reg::_Microfp0Idx
@ _Microfp0Idx
Definition:
float.hh:108
gem5::X86ISA::float_reg::_Fpr3Idx
@ _Fpr3Idx
Definition:
float.hh:67
gem5::X86ISA::float_reg::_Microfp7Idx
@ _Microfp7Idx
Definition:
float.hh:115
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
gem5::X86ISA::float_reg::_Xmm8HighIdx
@ _Xmm8HighIdx
Definition:
float.hh:91
gem5::X86ISA::float_reg::_Xmm10HighIdx
@ _Xmm10HighIdx
Definition:
float.hh:95
gem5::X86ISA::float_reg::_Microfp5Idx
@ _Microfp5Idx
Definition:
float.hh:113
gem5::X86ISA::float_reg::_Mmx7Idx
@ _Mmx7Idx
Definition:
float.hh:62
gem5::X86ISA::float_reg::_Xmm4LowIdx
@ _Xmm4LowIdx
Definition:
float.hh:82
gem5::X86ISA::float_reg::_Microfp2Idx
@ _Microfp2Idx
Definition:
float.hh:110
gem5::X86ISA::float_reg::_Xmm7LowIdx
@ _Xmm7LowIdx
Definition:
float.hh:88
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition:
reg_class.hh:126
gem5::X86ISA::float_reg::_Fpr2Idx
@ _Fpr2Idx
Definition:
float.hh:66
gem5::X86ISA::float_reg::microfp
static RegId microfp(int index)
Definition:
float.hh:151
gem5::X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition:
x86_traits.hh:54
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