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| std::string | generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override |
| | Internal function to generate disassembly string. More...
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| | RiscvMicroInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass) |
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| | RiscvMicroInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass) |
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| void | advancePC (PCStateBase &pcState) const override |
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| void | advancePC (ThreadContext *tc) const override |
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| | RiscvStaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) |
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| bool | alignmentOk (ExecContext *xc, Addr addr, Addr size) const |
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| void | setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest) |
| | Set the pointers which point to the arrays of source and destination register indices. More...
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| | StaticInst (const char *_mnemonic, OpClass op_class) |
| | Constructor. More...
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| template<typename T > |
| size_t | simpleAsBytes (void *buf, size_t max_size, const T &t) |
| |
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| using | RegIdArrayPtr = RegId(StaticInst::*)[] |
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| std::unique_ptr< PCStateBase > | buildRetPC (const PCStateBase &cur_pc, const PCStateBase &call_pc) const override |
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| size_t | asBytes (void *buf, size_t size) override |
| | Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More...
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| uint8_t | numSrcRegs () const |
| | Number of source registers. More...
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| uint8_t | numDestRegs () const |
| | Number of destination registers. More...
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| uint8_t | numDestRegs (RegClassType type) const |
| | Number of destination registers of a particular type. More...
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| |
| bool | isNop () const |
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| bool | isMemRef () const |
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| bool | isLoad () const |
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| bool | isStore () const |
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| bool | isAtomic () const |
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| bool | isStoreConditional () const |
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| bool | isInstPrefetch () const |
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| bool | isDataPrefetch () const |
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| bool | isPrefetch () const |
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| bool | isInteger () const |
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| bool | isFloating () const |
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| bool | isVector () const |
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| bool | isControl () const |
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| bool | isCall () const |
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| bool | isReturn () const |
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| bool | isDirectCtrl () const |
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| bool | isIndirectCtrl () const |
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| bool | isCondCtrl () const |
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| bool | isUncondCtrl () const |
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| bool | isSerializing () const |
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| bool | isSerializeBefore () const |
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| bool | isSerializeAfter () const |
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| bool | isSquashAfter () const |
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| bool | isFullMemBarrier () const |
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| bool | isReadBarrier () const |
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| bool | isWriteBarrier () const |
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| bool | isNonSpeculative () const |
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| bool | isQuiesce () const |
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| bool | isUnverifiable () const |
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| bool | isSyscall () const |
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| bool | isMacroop () const |
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| bool | isMicroop () const |
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| bool | isDelayedCommit () const |
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| bool | isLastMicroop () const |
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| bool | isFirstMicroop () const |
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| bool | isHtmStart () const |
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| bool | isHtmStop () const |
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| bool | isHtmCancel () const |
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| bool | isHtmCmd () const |
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| void | setFirstMicroop () |
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| void | setLastMicroop () |
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| void | setDelayedCommit () |
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| void | setFlag (Flags f) |
| |
| OpClass | opClass () const |
| | Operation class. Used to select appropriate function unit in issue. More...
|
| |
| const RegId & | destRegIdx (int i) const |
| | Return logical index (architectural reg num) of i'th destination reg. More...
|
| |
| void | setDestRegIdx (int i, const RegId &val) |
| |
| const RegId & | srcRegIdx (int i) const |
| | Return logical index (architectural reg num) of i'th source reg. More...
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| void | setSrcRegIdx (int i, const RegId &val) |
| |
| virtual uint64_t | getEMI () const |
| |
| virtual | ~StaticInst () |
| |
| virtual Fault | execute (ExecContext *xc, trace::InstRecord *traceData) const =0 |
| |
| virtual Fault | initiateAcc (ExecContext *xc, trace::InstRecord *traceData) const |
| |
| virtual Fault | completeAcc (Packet *pkt, ExecContext *xc, trace::InstRecord *trace_data) const |
| |
| virtual StaticInstPtr | fetchMicroop (MicroPC upc) const |
| | Return the microop that goes with a particular micropc. More...
|
| |
| virtual std::unique_ptr< PCStateBase > | branchTarget (const PCStateBase &pc) const |
| | Return the target address for a PC-relative branch. More...
|
| |
| virtual std::unique_ptr< PCStateBase > | branchTarget (ThreadContext *tc) const |
| | Return the target address for an indirect branch (jump). More...
|
| |
| virtual const std::string & | disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const |
| | Return string representation of disassembled instruction. More...
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| |
| void | printFlags (std::ostream &outs, const std::string &separator) const |
| | Print a separator separated list of this instruction's set flag names on the given stream. More...
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| std::string | getName () |
| | Return name of machine instruction. More...
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| |
| | RefCounted () |
| | We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...
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| virtual | ~RefCounted () |
| | We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...
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| void | incref () const |
| | Increment the reference count. More...
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| void | decref () const |
| | Decrement the reference count and destroy the object if all references are gone. More...
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| ExtMachInst | machInst |
| |
| static StaticInstPtr | nullStaticInstPtr |
| | Pointer to a statically allocated "null" instruction object. More...
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| |
Definition at line 110 of file amo.hh.
Protected Member Functions inherited from gem5::RiscvISA::RiscvMicroInst