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gem5
v22.1.0.0
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#include <unordered_map>#include <vector>#include "arch/generic/isa.hh"#include "arch/riscv/pcstate.hh"#include "arch/riscv/regs/misc.hh"#include "arch/riscv/types.hh"#include "base/types.hh"Go to the source code of this file.
Classes | |
| class | gem5::RiscvISA::ISA |
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| gem5::RiscvISA | |
Enumerations | |
| enum | gem5::RiscvISA::PrivilegeMode { gem5::RiscvISA::PRV_U = 0 , gem5::RiscvISA::PRV_S = 1 , gem5::RiscvISA::PRV_M = 3 } |
| enum | gem5::RiscvISA::FPUStatus { gem5::RiscvISA::OFF = 0 , gem5::RiscvISA::INITIAL = 1 , gem5::RiscvISA::CLEAN = 2 , gem5::RiscvISA::DIRTY = 3 } |
Functions | |
| std::ostream & | operator<< (std::ostream &os, gem5::RiscvISA::PrivilegeMode pm) |
| std::ostream& operator<< | ( | std::ostream & | os, |
| gem5::RiscvISA::PrivilegeMode | pm | ||
| ) |
Definition at line 612 of file isa.cc.
References gem5::X86ISA::os, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, and gem5::RiscvISA::PRV_U.