TLB Invalidate by VA, All ASID. More...
#include <tlbi_op.hh>
Public Member Functions | |
| TLBIMVAA (ExceptionLevel _targetEL, bool _secure, Addr _addr, bool last_level) | |
| void | operator() (ThreadContext *tc) override |
| bool | match (TlbEntry *entry, vmid_t curr_vmid) const override |
 Public Member Functions inherited from gem5::ArmISA::TLBIOp | |
| TLBIOp (ExceptionLevel _targetEL, bool _secure) | |
| virtual | ~TLBIOp () |
| virtual void | operator() (ThreadContext *tc) |
| void | broadcast (ThreadContext *tc) |
| Broadcast the TLB Invalidate operation to all TLBs in the Arm system. | |
| virtual bool | match (TlbEntry *entry, vmid_t curr_vmid) const =0 |
| virtual bool | stage1Flush () const |
| Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. | |
| virtual bool | stage2Flush () const |
| Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. | |
Public Attributes | |
| Addr | addr |
| bool | inHost |
| bool | lastLevel |
| Public Attributes inherited from gem5::ArmISA::TLBIOp | |
| bool | secureLookup |
| ExceptionLevel | targetEL |
Detailed Description
TLB Invalidate by VA, All ASID.
Definition at line 301 of file tlbi_op.hh.
Constructor & Destructor Documentation
◆ TLBIMVAA()
|
inline |
Definition at line 304 of file tlbi_op.hh.
Member Function Documentation
◆ match()
Implements gem5::ArmISA::TLBIOp.
Definition at line 226 of file tlbi_op.cc.
References addr, gem5::ArmISA::EL2, gem5::ArmISA::TlbEntry::Lookup::functional, gem5::ArmISA::TlbEntry::Lookup::hyp, gem5::ArmISA::TlbEntry::Lookup::ignoreAsn, gem5::ArmISA::TlbEntry::Lookup::inHost, inHost, lastLevel, gem5::ArmISA::TlbEntry::Lookup::mode, gem5::BaseMMU::Read, gem5::ArmISA::TlbEntry::Lookup::secure, gem5::ArmISA::TLBIOp::secureLookup, gem5::ArmISA::TlbEntry::Lookup::targetEL, gem5::ArmISA::TLBIOp::targetEL, gem5::ArmISA::te, gem5::ArmISA::TlbEntry::Lookup::va, and gem5::ArmISA::TlbEntry::Lookup::vmid.
◆ operator()()
|
overridevirtual |
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 213 of file tlbi_op.cc.
References gem5::ArmISA::MMU::flushStage1(), gem5::ThreadContext::getCheckerCpuPtr(), gem5::ArmISA::getMMUPtr(), inHost, gem5::ArmISA::MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().
Member Data Documentation
◆ addr
| Addr gem5::ArmISA::TLBIMVAA::addr |
Definition at line 314 of file tlbi_op.hh.
Referenced by match().
◆ inHost
| bool gem5::ArmISA::TLBIMVAA::inHost |
Definition at line 315 of file tlbi_op.hh.
Referenced by match(), and operator()().
◆ lastLevel
| bool gem5::ArmISA::TLBIMVAA::lastLevel |
Definition at line 316 of file tlbi_op.hh.
Referenced by match().
The documentation for this class was generated from the following files:
- arch/arm/tlbi_op.hh
- arch/arm/tlbi_op.cc