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gem5 v23.0.0.1
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#include <tarmac_base.hh>
Classes | |
| struct | InstEntry |
| TARMAC instruction trace record. More... | |
| struct | MemEntry |
| TARMAC memory access trace record (stores only). More... | |
| struct | RegEntry |
| TARMAC register trace record. More... | |
Public Types | |
| enum | TarmacRecordType { TARMAC_INST , TARMAC_REG , TARMAC_MEM , TARMAC_UNSUPPORTED } |
| TARMAC trace record type. More... | |
| enum | ISetState { ISET_ARM , ISET_THUMB , ISET_A64 , ISET_UNSUPPORTED } |
| ARM instruction set state. More... | |
| enum | RegType { REG_R , REG_X , REG_S , REG_D , REG_P , REG_Q , REG_Z , REG_MISC } |
| ARM register type. More... | |
Public Member Functions | |
| TarmacBaseRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, const StaticInstPtr _macroStaticInst=nullptr) | |
| virtual void | dump ()=0 |
Public Member Functions inherited from gem5::trace::InstRecord | |
| InstRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, const StaticInstPtr _macroStaticInst=nullptr) | |
| virtual | ~InstRecord () |
| void | setWhen (Tick new_when) |
| void | setMem (Addr a, Addr s, unsigned f) |
| template<typename T , size_t N> | |
| void | setData (std::array< T, N > d) |
| void | setData (uint64_t d) |
| void | setData (uint32_t d) |
| void | setData (uint16_t d) |
| void | setData (uint8_t d) |
| void | setData (int64_t d) |
| void | setData (int32_t d) |
| void | setData (int16_t d) |
| void | setData (int8_t d) |
| void | setData (double d) |
| void | setData (const RegClass ®_class, RegVal val) |
| void | setData (const RegClass ®_class, const void *val) |
| void | setFetchSeq (InstSeqNum seq) |
| void | setCPSeq (InstSeqNum seq) |
| void | setPredicate (bool val) |
| void | setFaulting (bool val) |
| virtual void | dump ()=0 |
| Tick | getWhen () const |
| ThreadContext * | getThread () const |
| StaticInstPtr | getStaticInst () const |
| const PCStateBase & | getPCState () const |
| StaticInstPtr | getMacroStaticInst () const |
| Addr | getAddr () const |
| Addr | getSize () const |
| unsigned | getFlags () const |
| bool | getMemValid () const |
| uint64_t | getIntData () const |
| double | getFloatData () const |
| int | getDataStatus () const |
| InstSeqNum | getFetchSeq () const |
| bool | getFetchSeqValid () const |
| InstSeqNum | getCpSeq () const |
| bool | getCpSeqValid () const |
| bool | getFaulting () const |
Static Public Member Functions | |
| static ISetState | pcToISetState (const PCStateBase &pc) |
| Returns the Instruction Set State according to the current PCState. | |
Additional Inherited Members | |
Protected Types inherited from gem5::trace::InstRecord | |
| enum | DataStatus { DataInvalid = 0 , DataInt8 = 1 , DataInt16 = 2 , DataInt32 = 4 , DataInt64 = 8 , DataDouble = 3 , DataReg = 5 } |
| What size of data was written? More... | |
Protected Attributes inherited from gem5::trace::InstRecord | |
| Tick | when |
| ThreadContext * | thread |
| StaticInstPtr | staticInst |
| std::unique_ptr< PCStateBase > | pc |
| StaticInstPtr | macroStaticInst |
| Addr | addr = 0 |
| The address that was accessed. | |
| Addr | size = 0 |
| The size of the memory request. | |
| unsigned | flags = 0 |
| The flags that were assigned to the request. | |
| union gem5::trace::InstRecord::Data | data |
| InstSeqNum | fetch_seq = 0 |
| InstSeqNum | cp_seq = 0 |
| enum gem5::trace::InstRecord::DataStatus | dataStatus = DataInvalid |
| bool | mem_valid = false |
| Are the memory fields in the record valid? | |
| bool | fetch_seq_valid = false |
| Are the fetch sequence number fields valid? | |
| bool | cp_seq_valid = false |
| Are the commit sequence number fields valid? | |
| bool | predicate = true |
| is the predicate for execution this inst true or false (not execed)? | |
| bool | faulting = false |
| Did the execution of this instruction fault? (requires ExecFaulting to be enabled) | |
Definition at line 65 of file tarmac_base.hh.
ARM instruction set state.
| Enumerator | |
|---|---|
| ISET_ARM | |
| ISET_THUMB | |
| ISET_A64 | |
| ISET_UNSUPPORTED | |
Definition at line 78 of file tarmac_base.hh.
ARM register type.
| Enumerator | |
|---|---|
| REG_R | |
| REG_X | |
| REG_S | |
| REG_D | |
| REG_P | |
| REG_Q | |
| REG_Z | |
| REG_MISC | |
Definition at line 82 of file tarmac_base.hh.
TARMAC trace record type.
| Enumerator | |
|---|---|
| TARMAC_INST | |
| TARMAC_REG | |
| TARMAC_MEM | |
| TARMAC_UNSUPPORTED | |
Definition at line 69 of file tarmac_base.hh.
| gem5::trace::TarmacBaseRecord::TarmacBaseRecord | ( | Tick | _when, |
| ThreadContext * | _thread, | ||
| const StaticInstPtr | _staticInst, | ||
| const PCStateBase & | _pc, | ||
| const StaticInstPtr | _macroStaticInst = nullptr |
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| ) |
Definition at line 55 of file tarmac_base.cc.
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pure virtual |
Implements gem5::trace::InstRecord.
Implemented in gem5::trace::TarmacParserRecord, and gem5::trace::TarmacTracerRecord.
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static |
Returns the Instruction Set State according to the current PCState.
| pc | program counter (PCState) variable |
Definition at line 103 of file tarmac_base.cc.
References ISET_A64, ISET_ARM, ISET_THUMB, ISET_UNSUPPORTED, and gem5::trace::InstRecord::pc.
Referenced by gem5::trace::TarmacParserRecord::dump().