base.hh

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#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
#define __MEM_CACHE_PREFETCH_BASE_HH__
 
#include <cstdint>
 
#include "arch/generic/tlb.hh"
#include "base/compiler.hh"
#include "base/statistics.hh"
#include "base/types.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/clocked_object.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
class BaseCache;
struct BasePrefetcherParams;
 
namespace prefetch
{
 
class Base : public ClockedObject
{
    class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
    {
      public:
        PrefetchListener(Base &_parent, ProbeManager *pm,
                         const std::string &name, bool _isFill = false,
                         bool _miss = false)
            : ProbeListenerArgBase(pm, name),
              parent(_parent), isFill(_isFill), miss(_miss) {}
        void notify(const PacketPtr &pkt) override;
      protected:
        Base &parent;
        const bool isFill;
        const bool miss;
    };
 
    std::vector<PrefetchListener *> listeners;
 
  public:
 
    class PrefetchInfo
    {
        Addr address;
        Addr pc;
        RequestorID requestorId;
        bool validPC;
        bool secure;
        unsigned int size;
        bool write;
        Addr paddress;
        bool cacheMiss;
        uint8_t *data;
 
      public:
        Addr getAddr() const
        {
            return address;
        }
 
        bool isSecure() const
        {
            return secure;
        }
 
        Addr getPC() const
        {
            assert(hasPC());
            return pc;
        }
 
        bool hasPC() const
        {
            return validPC;
        }
 
        RequestorID getRequestorId() const
        {
            return requestorId;
        }
 
        unsigned int getSize() const
        {
            return size;
        }
 
        bool isWrite() const
        {
            return write;
        }
 
        Addr getPaddr() const
        {
            return paddress;
        }
 
        bool isCacheMiss() const
        {
            return cacheMiss;
        }
 
        template <typename T>
        inline T
        get(ByteOrder endian) const
        {
            if (data == nullptr) {
                panic("PrefetchInfo::get called with a request with no data.");
            }
            switch (endian) {
                case ByteOrder::big:
                    return betoh(*(T*)data);
 
                case ByteOrder::little:
                    return letoh(*(T*)data);
 
                default:
                    panic("Illegal byte order in PrefetchInfo::get()\n");
            };
        }
 
        bool sameAddr(PrefetchInfo const &pfi) const
        {
            return this->getAddr() == pfi.getAddr() &&
                this->isSecure() == pfi.isSecure();
        }
 
        PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
 
        PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
 
        ~PrefetchInfo()
        {
            delete[] data;
        }
    };
 
  protected:
 
    // PARAMETERS
 
    BaseCache* cache;
 
    unsigned blkSize;
 
    unsigned lBlkSize;
 
    const bool onMiss;
 
    const bool onRead;
 
    const bool onWrite;
 
    const bool onData;
 
    const bool onInst;
 
    const RequestorID requestorId;
 
    const Addr pageBytes;
 
    const bool prefetchOnAccess;
 
    const bool prefetchOnPfHit;
 
    const bool useVirtualAddresses;
 
    bool observeAccess(const PacketPtr &pkt, bool miss) const;
 
    bool inCache(Addr addr, bool is_secure) const;
 
    bool inMissQueue(Addr addr, bool is_secure) const;
 
    bool hasBeenPrefetched(Addr addr, bool is_secure) const;
 
    bool samePage(Addr a, Addr b) const;
    Addr blockAddress(Addr a) const;
    Addr blockIndex(Addr a) const;
    Addr pageAddress(Addr a) const;
    Addr pageOffset(Addr a) const;
    Addr pageIthBlockAddress(Addr page, uint32_t i) const;
    struct StatGroup : public statistics::Group
    {
        StatGroup(statistics::Group *parent);
        statistics::Scalar demandMshrMisses;
        statistics::Scalar pfIssued;
        statistics::Scalar pfUnused;
        statistics::Scalar pfUseful;
        statistics::Scalar pfUsefulButMiss;
        statistics::Formula accuracy;
        statistics::Formula coverage;
 
        statistics::Scalar pfHitInCache;
 
        statistics::Scalar pfHitInMSHR;
 
        statistics::Scalar pfHitInWB;
 
        statistics::Formula pfLate;
    } prefetchStats;
 
    uint64_t issuedPrefetches;
    uint64_t usefulPrefetches;
 
    BaseMMU * mmu;
 
  public:
    Base(const BasePrefetcherParams &p);
    virtual ~Base() = default;
 
    virtual void setCache(BaseCache *_cache);
 
    virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
 
    virtual void notifyFill(const PacketPtr &pkt)
    {}
 
    virtual PacketPtr getPacket() = 0;
 
    virtual Tick nextPrefetchReadyTime() const = 0;
 
    void
    prefetchUnused()
    {
        prefetchStats.pfUnused++;
    }
 
    void
    incrDemandMhsrMisses()
    {
        prefetchStats.demandMshrMisses++;
    }
 
    void
    pfHitInCache()
    {
        prefetchStats.pfHitInCache++;
    }
 
    void
    pfHitInMSHR()
    {
        prefetchStats.pfHitInMSHR++;
    }
 
    void
    pfHitInWB()
    {
        prefetchStats.pfHitInWB++;
    }
 
    void regProbeListeners() override;
 
    void probeNotify(const PacketPtr &pkt, bool miss);
 
    void addEventProbe(SimObject *obj, const char *name);
 
    void addMMU(BaseMMU *mmu);
};
 
} // namespace prefetch
} // namespace gem5
 
#endif //__MEM_CACHE_PREFETCH_BASE_HH__