fs_workload.cc

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/*
 * Copyright (c) 2018 TU Dresden
 * Copyright (c) 2020 Barkhausen Institut
 * All rights reserved
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#include "arch/riscv/bare_metal/fs_workload.hh"
 
#include "arch/riscv/faults.hh"
#include "base/loader/object_file.hh"
#include "sim/system.hh"
#include "sim/workload.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
BareMetal::BareMetal(const Params &p) : Workload(p),
    _isBareMetal(p.bare_metal), _resetVect(p.reset_vect),
    bootloader(loader::createObjectFile(p.bootloader))
{
    fatal_if(!bootloader, "Could not load bootloader file %s.", p.bootloader);
    _resetVect = bootloader->entryPoint();
    bootloaderSymtab = bootloader->symtab();
 
    loader::debugSymbolTable.insert(bootloaderSymtab);
}
 
BareMetal::~BareMetal()
{
    delete bootloader;
}
 
void
BareMetal::initState()
{
    Workload::initState();
 
    warn_if(!bootloader->buildImage().write(system->physProxy),
            "Could not load sections to memory.");
 
    for (auto *tc: system->threads) {
        RiscvISA::Reset().invoke(tc);
        tc->activate();
    }
}
 
} // namespace RiscvISA
} // namespace gem5