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gem5
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gem5
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Go to the source code of this file.
Classes | |
| class | gem5::AMDGPUNbio |
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
Macros | |
| #define | AMDGPU_MM_INDEX 0x00000 |
| MMIO offsets for NBIO. More... | |
| #define | AMDGPU_MM_INDEX_HI 0x00018 |
| #define | AMDGPU_MM_DATA 0x00004 |
| #define | AMDGPU_PCIE_DATA_REG 0x0003c |
| #define | AMDGPU_MP0_SMN_C2PMSG_33 0x58184 |
| #define | AMDGPU_MP0_SMN_C2PMSG_35 0x5818c |
| #define | AMDGPU_MP0_SMN_C2PMSG_64 0x58200 |
| #define | AMDGPU_MP0_SMN_C2PMSG_69 0x58214 |
| #define | AMDGPU_MP0_SMN_C2PMSG_70 0x58218 |
| #define | AMDGPU_MP0_SMN_C2PMSG_71 0x5821c |
| #define | AMDGPU_MP0_SMN_C2PMSG_81 0x58244 |
| #define | VEGA10_INV_ENG17_ACK1 0x0a318 |
| #define | VEGA10_INV_ENG17_ACK2 0x69c18 |
| #define | VEGA10_INV_ENG17_SEM1 0x0a288 |
| #define | VEGA10_INV_ENG17_SEM2 0x69b88 |
| #define | MI100_INV_ENG17_ACK1 0x0a318 |
| #define | MI100_INV_ENG17_ACK2 0x6a918 |
| #define | MI100_INV_ENG17_ACK3 0x76918 |
| #define | MI100_INV_ENG17_SEM1 0x0a288 |
| #define | MI100_INV_ENG17_SEM2 0x6a888 |
| #define | MI100_INV_ENG17_SEM3 0x76888 |
| #define | MI200_INV_ENG17_ACK1 0x0a318 |
| #define | MI200_INV_ENG17_ACK2 0x6b018 |
| #define | MI200_INV_ENG17_SEM1 0x0a288 |
| #define | MI200_INV_ENG17_SEM2 0x6af88 |
| #define AMDGPU_MM_DATA 0x00004 |
Definition at line 58 of file amdgpu_nbio.hh.
| #define AMDGPU_MM_INDEX 0x00000 |
MMIO offsets for NBIO.
NBIO handles initialization such as device discovery and psp functions. Values taken from:
https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
The addresses in the file are dword addresses. Here they are converted to byte addresses so gem5 does not need to do any shifting.
Definition at line 56 of file amdgpu_nbio.hh.
| #define AMDGPU_MM_INDEX_HI 0x00018 |
Definition at line 57 of file amdgpu_nbio.hh.
| #define AMDGPU_MP0_SMN_C2PMSG_33 0x58184 |
Definition at line 62 of file amdgpu_nbio.hh.
| #define AMDGPU_MP0_SMN_C2PMSG_35 0x5818c |
Definition at line 63 of file amdgpu_nbio.hh.
| #define AMDGPU_MP0_SMN_C2PMSG_64 0x58200 |
Definition at line 64 of file amdgpu_nbio.hh.
| #define AMDGPU_MP0_SMN_C2PMSG_69 0x58214 |
Definition at line 65 of file amdgpu_nbio.hh.
| #define AMDGPU_MP0_SMN_C2PMSG_70 0x58218 |
Definition at line 66 of file amdgpu_nbio.hh.
| #define AMDGPU_MP0_SMN_C2PMSG_71 0x5821c |
Definition at line 67 of file amdgpu_nbio.hh.
| #define AMDGPU_MP0_SMN_C2PMSG_81 0x58244 |
Definition at line 68 of file amdgpu_nbio.hh.
| #define AMDGPU_PCIE_DATA_REG 0x0003c |
Definition at line 59 of file amdgpu_nbio.hh.
| #define MI100_INV_ENG17_ACK1 0x0a318 |
Definition at line 76 of file amdgpu_nbio.hh.
| #define MI100_INV_ENG17_ACK2 0x6a918 |
Definition at line 77 of file amdgpu_nbio.hh.
| #define MI100_INV_ENG17_ACK3 0x76918 |
Definition at line 78 of file amdgpu_nbio.hh.
| #define MI100_INV_ENG17_SEM1 0x0a288 |
Definition at line 79 of file amdgpu_nbio.hh.
| #define MI100_INV_ENG17_SEM2 0x6a888 |
Definition at line 80 of file amdgpu_nbio.hh.
| #define MI100_INV_ENG17_SEM3 0x76888 |
Definition at line 81 of file amdgpu_nbio.hh.
| #define MI200_INV_ENG17_ACK1 0x0a318 |
Definition at line 83 of file amdgpu_nbio.hh.
| #define MI200_INV_ENG17_ACK2 0x6b018 |
Definition at line 84 of file amdgpu_nbio.hh.
| #define MI200_INV_ENG17_SEM1 0x0a288 |
Definition at line 85 of file amdgpu_nbio.hh.
| #define MI200_INV_ENG17_SEM2 0x6af88 |
Definition at line 86 of file amdgpu_nbio.hh.
| #define VEGA10_INV_ENG17_ACK1 0x0a318 |
Definition at line 71 of file amdgpu_nbio.hh.
| #define VEGA10_INV_ENG17_ACK2 0x69c18 |
Definition at line 72 of file amdgpu_nbio.hh.
| #define VEGA10_INV_ENG17_SEM1 0x0a288 |
Definition at line 73 of file amdgpu_nbio.hh.
| #define VEGA10_INV_ENG17_SEM2 0x69b88 |
Definition at line 74 of file amdgpu_nbio.hh.