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se_workload.hh
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27 
28 #ifndef __ARCH_X86_SE_WORKLOAD_HH__
29 #define __ARCH_X86_SE_WORKLOAD_HH__
30 
31 #include "base/types.hh"
32 
33 namespace gem5
34 {
35 
36 namespace X86ISA
37 {
38 
39 /* memory mappings for KVMCpu in SE mode */
40 const Addr syscallCodeVirtAddr = 0xffff800000000000;
41 const Addr GDTVirtAddr = 0xffff800000001000;
42 const Addr IDTVirtAddr = 0xffff800000002000;
43 const Addr TSSVirtAddr = 0xffff800000003000;
44 const Addr TSSPhysAddr = 0x63000;
45 const Addr ISTVirtAddr = 0xffff800000004000;
46 const Addr PFHandlerVirtAddr = 0xffff800000005000;
47 const Addr MMIORegionVirtAddr = 0xffffc90000000000;
48 
49 } // namespace X86ISA
50 } // namespace gem5
51 
52 #endif // __ARCH_X86_SE_WORKLOAD_HH__
gem5::X86ISA::PFHandlerVirtAddr
const Addr PFHandlerVirtAddr
Definition: se_workload.hh:46
gem5::X86ISA::TSSPhysAddr
const Addr TSSPhysAddr
Definition: se_workload.hh:44
gem5::X86ISA::TSSVirtAddr
const Addr TSSVirtAddr
Definition: se_workload.hh:43
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
types.hh
gem5::X86ISA::ISTVirtAddr
const Addr ISTVirtAddr
Definition: se_workload.hh:45
gem5::X86ISA::MMIORegionVirtAddr
const Addr MMIORegionVirtAddr
Definition: se_workload.hh:47
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::syscallCodeVirtAddr
const Addr syscallCodeVirtAddr
Definition: se_workload.hh:40
gem5::X86ISA::GDTVirtAddr
const Addr GDTVirtAddr
Definition: se_workload.hh:41
gem5::X86ISA::IDTVirtAddr
const Addr IDTVirtAddr
Definition: se_workload.hh:42
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