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sharing.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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13  distributed under the License is distributed on an "AS IS" BASIS,
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18  *****************************************************************************/
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20 /*****************************************************************************
21 
22  sharing.h --
23 
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "common.h"
39 
40 SC_MODULE( sharing )
41 {
42  SC_HAS_PROCESS( sharing );
43 
44  sc_in_clk clk;
45 
46  const sc_signal<bool>& reset ;
47  const sc_signal_bool_vector4& in_value1; // Input port
48  const sc_signal_bool_vector5& in_value2; // Input port
49  const sc_signal_bool_vector6& in_value3; // Input port
50  const sc_signal_bool_vector7& in_value4; // Input port
51  const sc_signal_bool_vector8& in_value5; // Input port
52  const sc_signal<bool>& in_valid; // Input port
53  sc_signal_bool_vector4& out_value1; // Output port
54  sc_signal_bool_vector5& out_value2; // Output port
55  sc_signal_bool_vector6& out_value3; // Output port
56  sc_signal_bool_vector7& out_value4; // Output port
57  sc_signal_bool_vector8& out_value5; // Output port
58  sc_signal<bool>& out_valid; // Output port
59 
60  //
61  // Constructor
62  //
63 
64  sharing (
65  sc_module_name NAME, // referense name
66  sc_clock& CLK, // clock
67  const sc_signal<bool>& RESET,
68  const sc_signal_bool_vector4& IN_VALUE1,
69  const sc_signal_bool_vector5& IN_VALUE2,
70  const sc_signal_bool_vector6& IN_VALUE3,
71  const sc_signal_bool_vector7& IN_VALUE4,
72  const sc_signal_bool_vector8& IN_VALUE5,
73  const sc_signal<bool>& IN_VALID, // Input port
74  sc_signal_bool_vector4& OUT_VALUE1,
75  sc_signal_bool_vector5& OUT_VALUE2,
76  sc_signal_bool_vector6& OUT_VALUE3,
77  sc_signal_bool_vector7& OUT_VALUE4,
78  sc_signal_bool_vector8& OUT_VALUE5,
79  sc_signal<bool>& OUT_VALID // Output port
80  )
81  :
82  reset (RESET),
83  in_value1 (IN_VALUE1),
84  in_value2 (IN_VALUE2),
85  in_value3 (IN_VALUE3),
86  in_value4 (IN_VALUE4),
87  in_value5 (IN_VALUE5),
88  in_valid (IN_VALID),
89  out_value1 (OUT_VALUE1),
90  out_value2 (OUT_VALUE2),
91  out_value3 (OUT_VALUE3),
92  out_value4 (OUT_VALUE4),
93  out_value5 (OUT_VALUE5),
94  out_valid (OUT_VALID)
95 
96  {
97  clk (CLK);
98  SC_CTHREAD( entry, clk.pos() );
99  reset_signal_is(reset,true);
100  };
101 
102  //
103 
104  void entry ();
105 
106 };
107 
108 // EOF
sc_signal_bool_vector4
sc_signal< sc_bv< 4 > > sc_signal_bool_vector4
Definition: common.h:43
sc_signal_bool_vector7
sc_signal< sc_bv< 7 > > sc_signal_bool_vector7
Definition: common.h:46
sc_signal_bool_vector8
sc_signal< sc_bv< 8 > > sc_signal_bool_vector8
Definition: common.h:44
SC_MODULE
SC_MODULE(sharing)
Definition: sharing.h:40
sc_signal_bool_vector5
sc_signal< sc_bv< 5 > > sc_signal_bool_vector5
Definition: common.h:44
common.h
gem5::statistics::reset
void reset()
Definition: statistics.cc:309
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
sc_signal_bool_vector6
sc_signal< sc_bv< 6 > > sc_signal_bool_vector6
Definition: common.h:44
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:323
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