gem5
[DEVELOP-FOR-23.0]
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Device model for an Intel PIIX4 IDE controller. More...
#include <ide_ctrl.hh>
Classes | |
class | Channel |
Public Member Functions | |
PARAMS (IdeController) | |
IdeController (const Params &p) | |
virtual void | postInterrupt (bool is_primary) |
virtual void | clearInterrupt (bool is_primary) |
Tick | writeConfig (PacketPtr pkt) override |
Write to the PCI config space data that is stored locally. More... | |
Tick | readConfig (PacketPtr pkt) override |
Read from the PCI config space data that is stored locally. More... | |
Tick | read (PacketPtr pkt) override |
Pure virtual function that the device must implement. More... | |
Tick | write (PacketPtr pkt) override |
Pure virtual function that the device must implement. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize this object to the given output stream. More... | |
void | unserialize (CheckpointIn &cp) override |
Reconstruct the state of this object from a checkpoint. More... | |
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Addr | pciToDma (Addr pci_addr) const |
void | intrPost () |
void | intrClear () |
uint8_t | interruptLine () const |
AddrRangeList | getAddrRanges () const override |
Determine the address ranges that this device responds to. More... | |
PciDevice (const PciDeviceParams ¶ms) | |
Constructor for PCI Dev. More... | |
const PciBusAddr & | busAddr () const |
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DmaDevice (const Params &p) | |
virtual | ~DmaDevice ()=default |
void | dmaWrite (Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) |
void | dmaWrite (Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) |
void | dmaRead (Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) |
void | dmaRead (Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) |
bool | dmaPending () const |
void | init () override |
init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
unsigned int | cacheBlockSize () const |
Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) override |
Get a port with a given name and index. More... | |
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PioDevice (const Params &p) | |
virtual | ~PioDevice () |
void | init () override |
init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) override |
Get a port with a given name and index. More... | |
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ClockedObject (const ClockedObjectParams &p) | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. More... | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. More... | |
virtual void | regProbePoints () |
Register probe points for this object. More... | |
virtual void | regProbeListeners () |
Register probe listeners for this object. More... | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. More... | |
virtual void | startup () |
startup() is the final initialization call before simulation. More... | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. More... | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. More... | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More... | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. More... | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. More... | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. More... | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. More... | |
virtual void | notifyFork () |
Notify a child process of a fork. More... | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. More... | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. More... | |
virtual void | resetStats () |
Callback to reset stats. More... | |
virtual void | preDumpStats () |
Callback before stats are dumped. More... | |
void | addStat (statistics::Info *info) |
Register a stat with this group. More... | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. More... | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. More... | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. More... | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. More... | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. More... | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
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void | updateClockPeriod () |
Update the tick to the current tick. More... | |
Tick | clockEdge (Cycles cycles=Cycles(0)) const |
Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More... | |
Cycles | curCycle () const |
Determine the current cycle, corresponding to a tick aligned to a clock edge. More... | |
Tick | nextCycle () const |
Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More... | |
uint64_t | frequency () const |
Tick | clockPeriod () const |
double | voltage () const |
Cycles | ticksToCycles (Tick t) const |
Tick | cyclesToTicks (Cycles c) const |
Private Member Functions | |
BitUnion8 (BMIStatusReg) Bitfield< 6 > dmaCap0 | |
EndBitUnion (BMIStatusReg) BitUnion8(BMICommandReg) Bitfield< 3 > rw | |
void | dispatchAccess (PacketPtr pkt, bool read) |
Private Attributes | |
Bitfield< 5 > | dmaCap1 |
Bitfield< 2 > | intStatus |
Bitfield< 1 > | dmaError |
Bitfield< 0 > | active |
Bitfield< 0 > | startStop |
EndBitUnion(BMICommandReg) class ConfigSpaceRegs ConfigSpaceRegs | configSpaceRegs |
Registers used in device specific PCI configuration. More... | |
Channel | primary |
Channel | secondary |
uint32_t | ioShift |
uint32_t | ctrlOffset |
Additional Inherited Members | |
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typedef DmaDeviceParams | Params |
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using | Params = PioDeviceParams |
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using | Params = ClockedObjectParams |
Parameters of ClockedObject. More... | |
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typedef SimObjectParams | Params |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. More... | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. More... | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. More... | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. More... | |
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PowerState * | powerState |
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bool | getBAR (Addr addr, int &num, Addr &offs) |
Which base address register (if any) maps the given address? More... | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. More... | |
void | signalDrainDone () const |
Signal that an object is drained. More... | |
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Clocked (ClockDomain &clk_domain) | |
Create a clocked object and set the clock domain based on the parameters. More... | |
Clocked (Clocked &)=delete | |
Clocked & | operator= (Clocked &)=delete |
virtual | ~Clocked () |
Virtual destructor due to inheritance. More... | |
void | resetClock () const |
Reset the object's clock using the current global tick value. More... | |
virtual void | clockPeriodUpdated () |
A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More... | |
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const PciBusAddr | _busAddr |
PCIConfig | config |
The current config space. More... | |
std::vector< MSIXTable > | msix_table |
MSIX Table and PBA Structures. More... | |
std::vector< MSIXPbaEntry > | msix_pba |
std::array< PciBar *, 6 > | BARs {} |
PciHost::DeviceInterface | hostInterface |
Tick | pioDelay |
Tick | configDelay |
const int | PMCAP_BASE |
The capability list structures and base addresses. More... | |
const int | PMCAP_ID_OFFSET |
const int | PMCAP_PC_OFFSET |
const int | PMCAP_PMCS_OFFSET |
PMCAP | pmcap |
const int | MSICAP_BASE |
MSICAP | msicap |
const int | MSIXCAP_BASE |
const int | MSIXCAP_ID_OFFSET |
const int | MSIXCAP_MXC_OFFSET |
const int | MSIXCAP_MTAB_OFFSET |
const int | MSIXCAP_MPBA_OFFSET |
int | MSIX_TABLE_OFFSET |
int | MSIX_TABLE_END |
int | MSIX_PBA_OFFSET |
int | MSIX_PBA_END |
MSIXCAP | msixcap |
const int | PXCAP_BASE |
PXCAP | pxcap |
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DmaPort | dmaPort |
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System * | sys |
PioPort< PioDevice > | pioPort |
The pioPort that handles the requests for us and provides us requests that it sees. More... | |
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const SimObjectParams & | _params |
Cached copy of the object parameters. More... | |
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EventQueue * | eventq |
A pointer to this object's event queue. More... | |
Device model for an Intel PIIX4 IDE controller.
Definition at line 52 of file ide_ctrl.hh.
gem5::IdeController::IdeController | ( | const Params & | p | ) |
Definition at line 73 of file ide_ctrl.cc.
References gem5::ArmISA::i, panic_if, gem5::SimObject::params(), primary, secondary, gem5::IdeController::Channel::select(), and gem5::IdeController::Channel::setDevice0().
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Reimplemented in gem5::X86IdeController.
Definition at line 149 of file ide_ctrl.cc.
References gem5::PciDevice::intrClear(), primary, and secondary.
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Definition at line 317 of file ide_ctrl.cc.
References gem5::IdeController::Channel::accessBMI(), gem5::IdeController::Channel::accessCommand(), gem5::IdeController::Channel::accessControl(), gem5::X86ISA::addr, gem5::PciDevice::config, ctrlOffset, data, DPRINTF, gem5::Packet::getAddr(), gem5::PciDevice::getBAR(), gem5::Packet::getLE(), gem5::Packet::getPtr(), gem5::Packet::getSize(), ioShift, gem5::letoh(), gem5::Packet::makeAtomicResponse(), gem5::ArmISA::offset, panic, panic_if, primary, read(), and secondary.
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gem5::IdeController::PARAMS | ( | IdeController | ) |
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Reimplemented in gem5::X86IdeController.
Definition at line 140 of file ide_ctrl.cc.
References gem5::PciDevice::intrPost(), primary, and secondary.
Referenced by gem5::IdeController::Channel::postInterrupt().
Pure virtual function that the device must implement.
Called when a read command is recieved by the port.
pkt | Packet describing this request |
Implements gem5::PioDevice.
Definition at line 387 of file ide_ctrl.cc.
References dispatchAccess(), and gem5::PciDevice::pioDelay.
Referenced by gem5::IdeController::Channel::accessBMI(), gem5::IdeController::Channel::accessCommand(), gem5::IdeController::Channel::accessControl(), and dispatchAccess().
Read from the PCI config space data that is stored locally.
This may be overridden by the device but at some point it will eventually call this for normal operations that it does not need to override.
pkt | packet containing the write the offset into config space |
Reimplemented from gem5::PciDevice.
Definition at line 158 of file ide_ctrl.cc.
References gem5::PciDevice::configDelay, configSpaceRegs, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getPtr(), gem5::Packet::getSize(), gem5::Packet::getUintX(), gem5::Packet::makeAtomicResponse(), gem5::ArmISA::offset, PCI_CONFIG_SIZE, PCI_DEVICE_SPECIFIC, and gem5::PciDevice::readConfig().
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Serialize this object to the given output stream.
os | The stream to serialize to. |
Reimplemented from gem5::PciDevice.
Definition at line 401 of file ide_ctrl.cc.
References configSpaceRegs, primary, secondary, gem5::IdeController::Channel::serialize(), and gem5::PciDevice::serialize().
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Reconstruct the state of this object from a checkpoint.
cp | The checkpoint use. |
section | The section name of this object |
Reimplemented from gem5::PciDevice.
Definition at line 429 of file ide_ctrl.cc.
References configSpaceRegs, primary, secondary, gem5::IdeController::Channel::unserialize(), and gem5::PciDevice::unserialize().
Pure virtual function that the device must implement.
Called when a write command is recieved by the port.
pkt | Packet describing this request |
Implements gem5::PioDevice.
Definition at line 394 of file ide_ctrl.cc.
References dispatchAccess(), and gem5::PciDevice::pioDelay.
Write to the PCI config space data that is stored locally.
This may be overridden by the device but at some point it will eventually call this for normal operations that it does not need to override.
pkt | packet containing the write the offset into config space |
Reimplemented from gem5::PciDevice.
Definition at line 177 of file ide_ctrl.cc.
References gem5::PciDevice::configDelay, configSpaceRegs, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getConstPtr(), gem5::Packet::getSize(), gem5::Packet::getUintX(), gem5::Packet::makeAtomicResponse(), gem5::ArmISA::offset, PCI_CONFIG_SIZE, PCI_DEVICE_SPECIFIC, and gem5::PciDevice::writeConfig().
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Definition at line 61 of file ide_ctrl.hh.
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Registers used in device specific PCI configuration.
Definition at line 67 of file ide_ctrl.hh.
Referenced by readConfig(), serialize(), unserialize(), and writeConfig().
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Definition at line 194 of file ide_ctrl.hh.
Referenced by dispatchAccess().
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Definition at line 58 of file ide_ctrl.hh.
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Definition at line 60 of file ide_ctrl.hh.
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Definition at line 59 of file ide_ctrl.hh.
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Definition at line 194 of file ide_ctrl.hh.
Referenced by dispatchAccess().
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Definition at line 191 of file ide_ctrl.hh.
Referenced by clearInterrupt(), dispatchAccess(), IdeController(), postInterrupt(), serialize(), and unserialize().
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Definition at line 192 of file ide_ctrl.hh.
Referenced by clearInterrupt(), dispatchAccess(), IdeController(), postInterrupt(), serialize(), and unserialize().
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Definition at line 66 of file ide_ctrl.hh.